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AMDGPU: Handle a few missing cases in getAddrModeArguments
This commit is contained in:
Matt Arsenault
parent
9df19f7114
commit
f9805ce38d
@ -1175,9 +1175,13 @@ bool SITargetLowering::getAddrModeArguments(IntrinsicInst *II,
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case Intrinsic::amdgcn_atomic_dec:
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case Intrinsic::amdgcn_ds_ordered_add:
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case Intrinsic::amdgcn_ds_ordered_swap:
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case Intrinsic::amdgcn_ds_append:
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case Intrinsic::amdgcn_ds_consume:
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case Intrinsic::amdgcn_ds_fadd:
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case Intrinsic::amdgcn_ds_fmin:
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case Intrinsic::amdgcn_ds_fmax: {
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case Intrinsic::amdgcn_ds_fmax:
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case Intrinsic::amdgcn_global_atomic_fadd:
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case Intrinsic::amdgcn_global_atomic_csub: {
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Value *Ptr = II->getArgOperand(0);
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AccessTy = II->getType();
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Ops.push_back(Ptr);
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75
test/CodeGen/AMDGPU/cgp-addressing-modes-gfx1030.ll
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75
test/CodeGen/AMDGPU/cgp-addressing-modes-gfx1030.ll
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@ -0,0 +1,75 @@
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: opt -S -codegenprepare -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 < %s | FileCheck -check-prefix=OPT %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 < %s | FileCheck -check-prefix=GCN %s
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; Make sure we match the addressing mode offset of csub intrinsics across blocks.
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define amdgpu_kernel void @test_sink_small_offset_global_atomic_csub_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
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; OPT-LABEL: @test_sink_small_offset_global_atomic_csub_i32(
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; OPT-NEXT: entry:
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; OPT-NEXT: [[OUT_GEP:%.*]] = getelementptr i32, i32 addrspace(1)* [[OUT:%.*]], i32 999999
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; OPT-NEXT: [[TID:%.*]] = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #3
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; OPT-NEXT: [[CMP:%.*]] = icmp eq i32 [[TID]], 0
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; OPT-NEXT: br i1 [[CMP]], label [[ENDIF:%.*]], label [[IF:%.*]]
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; OPT: if:
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; OPT-NEXT: [[TMP0:%.*]] = bitcast i32 addrspace(1)* [[IN:%.*]] to i8 addrspace(1)*
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; OPT-NEXT: [[SUNKADDR:%.*]] = getelementptr i8, i8 addrspace(1)* [[TMP0]], i64 28
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; OPT-NEXT: [[TMP1:%.*]] = bitcast i8 addrspace(1)* [[SUNKADDR]] to i32 addrspace(1)*
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; OPT-NEXT: [[VAL:%.*]] = call i32 @llvm.amdgcn.global.atomic.csub.p1i32(i32 addrspace(1)* [[TMP1]], i32 2)
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; OPT-NEXT: br label [[ENDIF]]
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; OPT: endif:
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; OPT-NEXT: [[X:%.*]] = phi i32 [ [[VAL]], [[IF]] ], [ 0, [[ENTRY:%.*]] ]
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; OPT-NEXT: store i32 [[X]], i32 addrspace(1)* [[OUT_GEP]], align 4
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; OPT-NEXT: ret void
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;
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; GCN-LABEL: test_sink_small_offset_global_atomic_csub_i32:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
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; GCN-NEXT: v_mbcnt_lo_u32_b32_e64 v0, -1, 0
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; GCN-NEXT: ; implicit-def: $vcc_hi
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; GCN-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
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; GCN-NEXT: v_mov_b32_e32 v0, 0
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; GCN-NEXT: s_and_saveexec_b32 s4, vcc_lo
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; GCN-NEXT: s_cbranch_execz BB0_2
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; GCN-NEXT: ; %bb.1: ; %if
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: v_mov_b32_e32 v0, s2
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; GCN-NEXT: v_mov_b32_e32 v1, s3
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; GCN-NEXT: v_mov_b32_e32 v2, 2
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; GCN-NEXT: global_atomic_csub v0, v[0:1], v2, off offset:28 glc
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; GCN-NEXT: BB0_2: ; %endif
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; GCN-NEXT: s_or_b32 exec_lo, exec_lo, s4
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: v_add_co_u32_e64 v1, s0, 0x3d0800, s0
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; GCN-NEXT: v_add_co_ci_u32_e64 v2, s0, 0, s1, s0
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: global_store_dword v[1:2], v0, off offset:252
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; GCN-NEXT: s_endpgm
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entry:
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%out.gep = getelementptr i32, i32 addrspace(1)* %out, i32 999999
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%in.gep = getelementptr i32, i32 addrspace(1)* %in, i32 7
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%tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0
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%cmp = icmp eq i32 %tid, 0
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br i1 %cmp, label %endif, label %if
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if:
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%val = call i32 @llvm.amdgcn.global.atomic.csub.p1i32(i32 addrspace(1)* %in.gep, i32 2)
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br label %endif
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endif:
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%x = phi i32 [ %val, %if ], [ 0, %entry ]
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store i32 %x, i32 addrspace(1)* %out.gep
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br label %done
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done:
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ret void
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}
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declare i32 @llvm.amdgcn.global.atomic.csub.p1i32(i32 addrspace(1)* nocapture, i32) #0
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declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #1
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declare void @llvm.amdgcn.global.atomic.fadd.p1f32.f32(float addrspace(1)* nocapture, float) #2
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attributes #0 = { argmemonly nounwind }
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attributes #1 = { nounwind readnone willreturn }
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attributes #2 = { argmemonly nounwind willreturn }
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78
test/CodeGen/AMDGPU/cgp-addressing-modes-gfx908.ll
Normal file
78
test/CodeGen/AMDGPU/cgp-addressing-modes-gfx908.ll
Normal file
@ -0,0 +1,78 @@
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: opt -S -codegenprepare -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 < %s | FileCheck -check-prefix=OPT %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 < %s | FileCheck -check-prefix=GCN %s
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; Make sure we match the addressing mode offset of globla.atomic.fadd intrinsics across blocks.
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define amdgpu_kernel void @test_sink_small_offset_global_atomic_fadd_f32(float addrspace(1)* %out, float addrspace(1)* %in) {
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; OPT-LABEL: @test_sink_small_offset_global_atomic_fadd_f32(
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; OPT-NEXT: entry:
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; OPT-NEXT: [[OUT_GEP:%.*]] = getelementptr float, float addrspace(1)* [[OUT:%.*]], i32 999999
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; OPT-NEXT: [[TID:%.*]] = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #3
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; OPT-NEXT: [[CMP:%.*]] = icmp eq i32 [[TID]], 0
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; OPT-NEXT: br i1 [[CMP]], label [[ENDIF:%.*]], label [[IF:%.*]]
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; OPT: if:
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; OPT-NEXT: [[TMP0:%.*]] = bitcast float addrspace(1)* [[IN:%.*]] to i8 addrspace(1)*
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; OPT-NEXT: [[SUNKADDR:%.*]] = getelementptr i8, i8 addrspace(1)* [[TMP0]], i64 28
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; OPT-NEXT: [[TMP1:%.*]] = bitcast i8 addrspace(1)* [[SUNKADDR]] to float addrspace(1)*
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; OPT-NEXT: call void @llvm.amdgcn.global.atomic.fadd.p1f32.f32(float addrspace(1)* [[TMP1]], float 2.000000e+00)
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; OPT-NEXT: [[VAL:%.*]] = load volatile float, float addrspace(1)* undef, align 4
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; OPT-NEXT: br label [[ENDIF]]
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; OPT: endif:
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; OPT-NEXT: [[X:%.*]] = phi float [ [[VAL]], [[IF]] ], [ 0.000000e+00, [[ENTRY:%.*]] ]
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; OPT-NEXT: store float [[X]], float addrspace(1)* [[OUT_GEP]], align 4
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; OPT-NEXT: ret void
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;
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; GCN-LABEL: test_sink_small_offset_global_atomic_fadd_f32:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
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; GCN-NEXT: v_mbcnt_lo_u32_b32 v0, -1, 0
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; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
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; GCN-NEXT: v_mov_b32_e32 v0, 0
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; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc
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; GCN-NEXT: s_cbranch_execz BB0_2
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; GCN-NEXT: ; %bb.1: ; %if
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: v_mov_b32_e32 v0, s2
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; GCN-NEXT: v_mov_b32_e32 v1, s3
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; GCN-NEXT: v_mov_b32_e32 v2, 2.0
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; GCN-NEXT: global_atomic_add_f32 v[0:1], v2, off offset:28
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; GCN-NEXT: global_load_dword v0, v[0:1], off
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; GCN-NEXT: BB0_2: ; %endif
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; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: v_mov_b32_e32 v1, s0
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; GCN-NEXT: v_add_co_u32_e32 v1, vcc, 0x3d0000, v1
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; GCN-NEXT: v_mov_b32_e32 v2, s1
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; GCN-NEXT: v_addc_co_u32_e32 v2, vcc, 0, v2, vcc
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: global_store_dword v[1:2], v0, off offset:2300
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; GCN-NEXT: s_endpgm
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entry:
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%out.gep = getelementptr float, float addrspace(1)* %out, i32 999999
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%in.gep = getelementptr float, float addrspace(1)* %in, i32 7
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%tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0
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%cmp = icmp eq i32 %tid, 0
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br i1 %cmp, label %endif, label %if
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if:
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call void @llvm.amdgcn.global.atomic.fadd.p1f32.f32(float addrspace(1)* %in.gep, float 2.0)
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%val = load volatile float, float addrspace(1)* undef
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br label %endif
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endif:
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%x = phi float [ %val, %if ], [ 0.0, %entry ]
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store float %x, float addrspace(1)* %out.gep
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br label %done
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done:
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ret void
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}
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declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #1
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declare void @llvm.amdgcn.global.atomic.fadd.p1f32.f32(float addrspace(1)* nocapture, float) #2
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attributes #0 = { argmemonly nounwind }
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attributes #1 = { nounwind readnone willreturn }
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attributes #2 = { argmemonly nounwind willreturn }
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@ -748,10 +748,65 @@ done:
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ret void
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}
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; OPT-LABEL: @test_sink_small_offset_ds_append(
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; OPT: %0 = bitcast i32 addrspace(3)* %in to i8 addrspace(3)*
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; OPT: %sunkaddr = getelementptr i8, i8 addrspace(3)* %0, i32 28
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; OPT: %1 = bitcast i8 addrspace(3)* %sunkaddr to i32 addrspace(3)*
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; OPT: %tmp1 = call i32 @llvm.amdgcn.ds.append.p3i32(i32 addrspace(3)* %1, i1 false)
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define amdgpu_kernel void @test_sink_small_offset_ds_append(i32 addrspace(3)* %out, i32 addrspace(3)* %in) {
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entry:
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%out.gep = getelementptr i32, i32 addrspace(3)* %out, i32 999999
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%in.gep = getelementptr i32, i32 addrspace(3)* %in, i32 7
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%tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0
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%tmp0 = icmp eq i32 %tid, 0
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br i1 %tmp0, label %endif, label %if
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if:
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%tmp1 = call i32 @llvm.amdgcn.ds.append.p3i32(i32 addrspace(3)* %in.gep, i1 false)
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br label %endif
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endif:
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%x = phi i32 [ %tmp1, %if ], [ 0, %entry ]
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store i32 %x, i32 addrspace(3)* %out.gep
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br label %done
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done:
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ret void
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}
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; OPT-LABEL: @test_sink_small_offset_ds_consume(
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; OPT: %0 = bitcast i32 addrspace(3)* %in to i8 addrspace(3)*
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; OPT: %sunkaddr = getelementptr i8, i8 addrspace(3)* %0, i32 28
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; OPT: %1 = bitcast i8 addrspace(3)* %sunkaddr to i32 addrspace(3)*
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; OPT: %tmp1 = call i32 @llvm.amdgcn.ds.consume.p3i32(i32 addrspace(3)* %1, i1 false)
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define amdgpu_kernel void @test_sink_small_offset_ds_consume(i32 addrspace(3)* %out, i32 addrspace(3)* %in) {
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entry:
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%out.gep = getelementptr i32, i32 addrspace(3)* %out, i32 999999
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%in.gep = getelementptr i32, i32 addrspace(3)* %in, i32 7
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%tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0
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%tmp0 = icmp eq i32 %tid, 0
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br i1 %tmp0, label %endif, label %if
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if:
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%tmp1 = call i32 @llvm.amdgcn.ds.consume.p3i32(i32 addrspace(3)* %in.gep, i1 false)
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br label %endif
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endif:
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%x = phi i32 [ %tmp1, %if ], [ 0, %entry ]
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store i32 %x, i32 addrspace(3)* %out.gep
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br label %done
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done:
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ret void
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}
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declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #0
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declare i32 @llvm.amdgcn.atomic.inc.i32.p3i32(i32 addrspace(3)* nocapture, i32, i32, i32, i1) #2
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declare i32 @llvm.amdgcn.atomic.dec.i32.p3i32(i32 addrspace(3)* nocapture, i32, i32, i32, i1) #2
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declare i32 @llvm.amdgcn.ds.append.p3i32(i32 addrspace(3)* nocapture, i1 immarg) #3
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declare i32 @llvm.amdgcn.ds.consume.p3i32(i32 addrspace(3)* nocapture, i1 immarg) #3
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attributes #0 = { nounwind readnone }
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attributes #1 = { nounwind }
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attributes #2 = { nounwind argmemonly }
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attributes #3 = { argmemonly convergent nounwind willreturn }
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