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[WebAssembly] Use named operands to identify loads and stores
Summary: Uses the named operands tablegen feature to look up the indices of offset, address, and p2align operands for all load and store instructions. This replaces brittle, incorrect logic for identifying loads and store when eliminating frame indices, which previously crashed on bulk-memory ops. It also cleans up the SetP2Alignment pass. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, hiraditya, sunfish, jfb, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59007 llvm-svn: 355770
This commit is contained in:
Thomas Lively
parent
7ca29a3649
commit
f98161801a
@ -331,14 +331,6 @@ inline unsigned GetDefaultP2Align(unsigned Opcode) {
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}
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}
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/// The operand number of the load or store address in load/store instructions.
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static const unsigned LoadAddressOperandNo = 3;
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static const unsigned StoreAddressOperandNo = 2;
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/// The operand number of the load or store p2align in load/store instructions.
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static const unsigned LoadP2AlignOperandNo = 1;
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static const unsigned StoreP2AlignOperandNo = 0;
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/// This is used to indicate block signatures.
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enum class ExprType : unsigned {
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Void = 0x40,
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@ -11,6 +11,7 @@
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///
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//===----------------------------------------------------------------------===//
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let UseNamedOperandTable = 1 in
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multiclass ATOMIC_I<dag oops_r, dag iops_r, dag oops_s, dag iops_s,
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list<dag> pattern_r, string asmstr_r = "",
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string asmstr_s = "", bits<32> atomic_op = -1> {
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@ -810,9 +811,9 @@ multiclass WebAssemblyTerRMW<WebAssemblyRegClass rc, string name,
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defm "" :
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ATOMIC_I<(outs rc:$dst),
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(ins P2Align:$p2align, offset32_op:$off, I32:$addr, rc:$exp,
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rc:$new),
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rc:$new_),
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(outs), (ins P2Align:$p2align, offset32_op:$off), [],
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!strconcat(name, "\t$dst, ${off}(${addr})${p2align}, $exp, $new"),
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!strconcat(name, "\t$dst, ${off}(${addr})${p2align}, $exp, $new_"),
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!strconcat(name, "\t${off}${p2align}"), atomic_op>;
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}
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@ -27,6 +27,10 @@ using namespace llvm;
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#define GET_INSTRINFO_CTOR_DTOR
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#include "WebAssemblyGenInstrInfo.inc"
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// defines WebAssembly::getNamedOperandIdx
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#define GET_INSTRINFO_NAMED_OPS
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#include "WebAssemblyGenInstrInfo.inc"
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WebAssemblyInstrInfo::WebAssemblyInstrInfo(const WebAssemblySubtarget &STI)
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: WebAssemblyGenInstrInfo(WebAssembly::ADJCALLSTACKDOWN,
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WebAssembly::ADJCALLSTACKUP,
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@ -21,8 +21,17 @@
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#define GET_INSTRINFO_HEADER
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#include "WebAssemblyGenInstrInfo.inc"
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#define GET_INSTRINFO_OPERAND_ENUM
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#include "WebAssemblyGenInstrInfo.inc"
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namespace llvm {
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namespace WebAssembly {
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int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIndex);
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}
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class WebAssemblySubtarget;
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class WebAssemblyInstrInfo final : public WebAssemblyGenInstrInfo {
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@ -52,7 +52,7 @@ def regPlusGA : PatFrag<(ops node:$addr, node:$off),
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// Defines atomic and non-atomic loads, regular and extending.
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multiclass WebAssemblyLoad<WebAssemblyRegClass rc, string Name, int Opcode> {
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let mayLoad = 1 in
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let mayLoad = 1, UseNamedOperandTable = 1 in
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defm "": I<(outs rc:$dst),
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(ins P2Align:$p2align, offset32_op:$off, I32:$addr),
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(outs), (ins P2Align:$p2align, offset32_op:$off),
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@ -294,7 +294,7 @@ def : LoadPatExternSymOffOnly<i64, extloadi32, LOAD32_U_I64>;
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// Defines atomic and non-atomic stores, regular and truncating
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multiclass WebAssemblyStore<WebAssemblyRegClass rc, string Name, int Opcode> {
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let mayStore = 1 in
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let mayStore = 1, UseNamedOperandTable = 1 in
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defm "" : I<(outs),
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(ins P2Align:$p2align, offset32_op:$off, I32:$addr, rc:$val),
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(outs),
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@ -41,12 +41,12 @@ def LaneIdx#SIZE : ImmLeaf<i32, "return 0 <= Imm && Imm < "#SIZE#";">;
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// Load: v128.load
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multiclass SIMDLoad<ValueType vec_t> {
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let mayLoad = 1 in
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let mayLoad = 1, UseNamedOperandTable = 1 in
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defm LOAD_#vec_t :
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SIMD_I<(outs V128:$dst), (ins P2Align:$align, offset32_op:$off, I32:$addr),
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(outs), (ins P2Align:$align, offset32_op:$off), [],
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"v128.load\t$dst, ${off}(${addr})$align",
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"v128.load\t$off$align", 0>;
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SIMD_I<(outs V128:$dst), (ins P2Align:$p2align, offset32_op:$off, I32:$addr),
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(outs), (ins P2Align:$p2align, offset32_op:$off), [],
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"v128.load\t$dst, ${off}(${addr})$p2align",
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"v128.load\t$off$p2align", 0>;
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}
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foreach vec_t = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in {
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@ -65,12 +65,12 @@ def : LoadPatExternSymOffOnly<vec_t, load, !cast<NI>("LOAD_"#vec_t)>;
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// Store: v128.store
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multiclass SIMDStore<ValueType vec_t> {
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let mayStore = 1 in
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let mayStore = 1, UseNamedOperandTable = 1 in
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defm STORE_#vec_t :
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SIMD_I<(outs), (ins P2Align:$align, offset32_op:$off, I32:$addr, V128:$vec),
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(outs), (ins P2Align:$align, offset32_op:$off), [],
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"v128.store\t${off}(${addr})$align, $vec",
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"v128.store\t$off$align", 1>;
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SIMD_I<(outs), (ins P2Align:$p2align, offset32_op:$off, I32:$addr, V128:$vec),
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(outs), (ins P2Align:$p2align, offset32_op:$off), [],
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"v128.store\t${off}(${addr})$p2align, $vec",
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"v128.store\t$off$p2align", 1>;
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}
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foreach vec_t = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in {
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@ -70,13 +70,16 @@ void WebAssemblyRegisterInfo::eliminateFrameIndex(
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// If this is the address operand of a load or store, make it relative to SP
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// and fold the frame offset directly in.
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if ((MI.mayLoad() && FIOperandNum == WebAssembly::LoadAddressOperandNo) ||
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(MI.mayStore() && FIOperandNum == WebAssembly::StoreAddressOperandNo)) {
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assert(FrameOffset >= 0 && MI.getOperand(FIOperandNum - 1).getImm() >= 0);
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int64_t Offset = MI.getOperand(FIOperandNum - 1).getImm() + FrameOffset;
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unsigned AddrOperandNum = WebAssembly::getNamedOperandIdx(
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MI.getOpcode(), WebAssembly::OpName::addr);
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if (AddrOperandNum == FIOperandNum) {
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unsigned OffsetOperandNum = WebAssembly::getNamedOperandIdx(
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MI.getOpcode(), WebAssembly::OpName::off);
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assert(FrameOffset >= 0 && MI.getOperand(OffsetOperandNum).getImm() >= 0);
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int64_t Offset = MI.getOperand(OffsetOperandNum).getImm() + FrameOffset;
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if (static_cast<uint64_t>(Offset) <= std::numeric_limits<uint32_t>::max()) {
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MI.getOperand(FIOperandNum - 1).setImm(Offset);
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MI.getOperand(OffsetOperandNum).setImm(Offset);
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MI.getOperand(FIOperandNum)
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.ChangeToRegister(FrameRegister, /*IsDef=*/false);
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return;
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@ -13,6 +13,7 @@
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#include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
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#include "WebAssembly.h"
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#include "WebAssemblyInstrInfo.h"
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#include "WebAssemblyMachineFunctionInfo.h"
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#include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
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#include "llvm/CodeGen/MachineMemOperand.h"
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@ -83,114 +84,11 @@ bool WebAssemblySetP2AlignOperands::runOnMachineFunction(MachineFunction &MF) {
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for (auto &MBB : MF) {
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for (auto &MI : MBB) {
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switch (MI.getOpcode()) {
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case WebAssembly::LOAD_I32:
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case WebAssembly::LOAD_I64:
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case WebAssembly::LOAD_F32:
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case WebAssembly::LOAD_F64:
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case WebAssembly::LOAD_v16i8:
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case WebAssembly::LOAD_v8i16:
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case WebAssembly::LOAD_v4i32:
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case WebAssembly::LOAD_v2i64:
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case WebAssembly::LOAD_v4f32:
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case WebAssembly::LOAD_v2f64:
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case WebAssembly::LOAD8_S_I32:
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case WebAssembly::LOAD8_U_I32:
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case WebAssembly::LOAD16_S_I32:
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case WebAssembly::LOAD16_U_I32:
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case WebAssembly::LOAD8_S_I64:
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case WebAssembly::LOAD8_U_I64:
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case WebAssembly::LOAD16_S_I64:
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case WebAssembly::LOAD16_U_I64:
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case WebAssembly::LOAD32_S_I64:
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case WebAssembly::LOAD32_U_I64:
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case WebAssembly::ATOMIC_LOAD_I32:
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case WebAssembly::ATOMIC_LOAD8_U_I32:
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case WebAssembly::ATOMIC_LOAD16_U_I32:
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case WebAssembly::ATOMIC_LOAD_I64:
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case WebAssembly::ATOMIC_LOAD8_U_I64:
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case WebAssembly::ATOMIC_LOAD16_U_I64:
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case WebAssembly::ATOMIC_LOAD32_U_I64:
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case WebAssembly::ATOMIC_RMW8_U_ADD_I32:
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case WebAssembly::ATOMIC_RMW8_U_ADD_I64:
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case WebAssembly::ATOMIC_RMW8_U_SUB_I32:
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case WebAssembly::ATOMIC_RMW8_U_SUB_I64:
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case WebAssembly::ATOMIC_RMW8_U_AND_I32:
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case WebAssembly::ATOMIC_RMW8_U_AND_I64:
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case WebAssembly::ATOMIC_RMW8_U_OR_I32:
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case WebAssembly::ATOMIC_RMW8_U_OR_I64:
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case WebAssembly::ATOMIC_RMW8_U_XOR_I32:
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case WebAssembly::ATOMIC_RMW8_U_XOR_I64:
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case WebAssembly::ATOMIC_RMW8_U_XCHG_I32:
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case WebAssembly::ATOMIC_RMW8_U_XCHG_I64:
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case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I32:
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case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I64:
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case WebAssembly::ATOMIC_RMW16_U_ADD_I32:
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case WebAssembly::ATOMIC_RMW16_U_ADD_I64:
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case WebAssembly::ATOMIC_RMW16_U_SUB_I32:
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case WebAssembly::ATOMIC_RMW16_U_SUB_I64:
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case WebAssembly::ATOMIC_RMW16_U_AND_I32:
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case WebAssembly::ATOMIC_RMW16_U_AND_I64:
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case WebAssembly::ATOMIC_RMW16_U_OR_I32:
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case WebAssembly::ATOMIC_RMW16_U_OR_I64:
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case WebAssembly::ATOMIC_RMW16_U_XOR_I32:
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case WebAssembly::ATOMIC_RMW16_U_XOR_I64:
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case WebAssembly::ATOMIC_RMW16_U_XCHG_I32:
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case WebAssembly::ATOMIC_RMW16_U_XCHG_I64:
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case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I32:
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case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I64:
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case WebAssembly::ATOMIC_RMW_ADD_I32:
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case WebAssembly::ATOMIC_RMW32_U_ADD_I64:
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case WebAssembly::ATOMIC_RMW_SUB_I32:
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case WebAssembly::ATOMIC_RMW32_U_SUB_I64:
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case WebAssembly::ATOMIC_RMW_AND_I32:
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case WebAssembly::ATOMIC_RMW32_U_AND_I64:
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case WebAssembly::ATOMIC_RMW_OR_I32:
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case WebAssembly::ATOMIC_RMW32_U_OR_I64:
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case WebAssembly::ATOMIC_RMW_XOR_I32:
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case WebAssembly::ATOMIC_RMW32_U_XOR_I64:
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case WebAssembly::ATOMIC_RMW_XCHG_I32:
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case WebAssembly::ATOMIC_RMW32_U_XCHG_I64:
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case WebAssembly::ATOMIC_RMW_CMPXCHG_I32:
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case WebAssembly::ATOMIC_RMW32_U_CMPXCHG_I64:
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case WebAssembly::ATOMIC_RMW_ADD_I64:
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case WebAssembly::ATOMIC_RMW_SUB_I64:
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case WebAssembly::ATOMIC_RMW_AND_I64:
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case WebAssembly::ATOMIC_RMW_OR_I64:
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case WebAssembly::ATOMIC_RMW_XOR_I64:
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case WebAssembly::ATOMIC_RMW_XCHG_I64:
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case WebAssembly::ATOMIC_RMW_CMPXCHG_I64:
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case WebAssembly::ATOMIC_NOTIFY:
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case WebAssembly::ATOMIC_WAIT_I32:
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case WebAssembly::ATOMIC_WAIT_I64:
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rewriteP2Align(MI, WebAssembly::LoadP2AlignOperandNo);
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break;
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case WebAssembly::STORE_I32:
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case WebAssembly::STORE_I64:
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case WebAssembly::STORE_F32:
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case WebAssembly::STORE_F64:
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case WebAssembly::STORE_v16i8:
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case WebAssembly::STORE_v8i16:
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case WebAssembly::STORE_v4i32:
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case WebAssembly::STORE_v2i64:
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case WebAssembly::STORE_v4f32:
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case WebAssembly::STORE_v2f64:
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case WebAssembly::STORE8_I32:
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case WebAssembly::STORE16_I32:
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case WebAssembly::STORE8_I64:
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case WebAssembly::STORE16_I64:
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case WebAssembly::STORE32_I64:
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case WebAssembly::ATOMIC_STORE_I32:
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case WebAssembly::ATOMIC_STORE8_I32:
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case WebAssembly::ATOMIC_STORE16_I32:
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case WebAssembly::ATOMIC_STORE_I64:
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case WebAssembly::ATOMIC_STORE8_I64:
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case WebAssembly::ATOMIC_STORE16_I64:
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case WebAssembly::ATOMIC_STORE32_I64:
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rewriteP2Align(MI, WebAssembly::StoreP2AlignOperandNo);
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break;
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default:
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break;
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int16_t P2AlignOpNum = WebAssembly::getNamedOperandIdx(
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MI.getOpcode(), WebAssembly::OpName::p2align);
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if (P2AlignOpNum != -1) {
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rewriteP2Align(MI, P2AlignOpNum);
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Changed = true;
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}
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}
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}
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@ -140,3 +140,68 @@ define void @memset_1024(i8* %dest, i8 %val) {
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call void @llvm.memset.p0i8.i32(i8* %dest, i8 %val, i32 1024, i1 0)
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ret void
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}
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; The following tests check that frame index elimination works for
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; bulk memory instructions. The stack pointer is bumped by 16 instead
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; of 10 because the stack pointer in WebAssembly is currently always
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; 16-byte aligned, even in leaf functions, although it is not written
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; back to the global in this case.
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; TODO: Change TransientStackAlignment to 1 to avoid this extra
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; arithmetic. This will require forcing the use of StackAlignment in
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; PrologEpilogEmitter.cpp when
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; WebAssemblyFrameLowering::needsSPWriteback would be true.
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; CHECK-LABEL: memcpy_alloca_src:
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; NO-BULK-MEM-NOT: memory.copy
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; BULK-MEM-NEXT: .functype memcpy_alloca_src (i32) -> ()
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; BULK-MEM-NEXT: global.get $push[[L0:[0-9]+]]=, __stack_pointer
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; BULK-MEM-NEXT: i32.const $push[[L1:[0-9]+]]=, 16
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; BULK-MEM-NEXT: i32.sub $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]]
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; BULK-MEM-NEXT: i32.const $push[[L3:[0-9]+]]=, 6
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; BULK-MEM-NEXT: i32.add $push[[L4:[0-9]+]]=, $pop[[L2]], $pop[[L3]]
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; BULK-MEM-NEXT: i32.const $push[[L5:[0-9]+]]=, 10
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; BULK-MEM-NEXT: memory.copy 0, 0, $0, $pop[[L4]], $pop[[L5]]
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; BULK-MEM-NEXT: return
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define void @memcpy_alloca_src(i8* %dst) {
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%a = alloca [10 x i8]
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%p = bitcast [10 x i8]* %a to i8*
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call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dst, i8* %p, i32 10, i1 false)
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ret void
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}
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; CHECK-LABEL: memcpy_alloca_dst:
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; NO-BULK-MEM-NOT: memory.copy
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; BULK-MEM-NEXT: .functype memcpy_alloca_dst (i32) -> ()
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; BULK-MEM-NEXT: global.get $push[[L0:[0-9]+]]=, __stack_pointer
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; BULK-MEM-NEXT: i32.const $push[[L1:[0-9]+]]=, 16
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; BULK-MEM-NEXT: i32.sub $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]]
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; BULK-MEM-NEXT: i32.const $push[[L3:[0-9]+]]=, 6
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; BULK-MEM-NEXT: i32.add $push[[L4:[0-9]+]]=, $pop[[L2]], $pop[[L3]]
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; BULK-MEM-NEXT: i32.const $push[[L5:[0-9]+]]=, 10
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; BULK-MEM-NEXT: memory.copy 0, 0, $pop[[L4]], $0, $pop[[L5]]
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; BULK-MEM-NEXT: return
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define void @memcpy_alloca_dst(i8* %src) {
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%a = alloca [10 x i8]
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%p = bitcast [10 x i8]* %a to i8*
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call void @llvm.memcpy.p0i8.p0i8.i32(i8* %p, i8* %src, i32 10, i1 false)
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ret void
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}
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; CHECK-LABEL: memset_alloca:
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; NO-BULK-MEM-NOT: memory.fill
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; BULK-MEM-NEXT: .functype memset_alloca (i32) -> ()
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; BULK-MEM-NEXT: global.get $push[[L0:[0-9]+]]=, __stack_pointer
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; BULK-MEM-NEXT: i32.const $push[[L1:[0-9]+]]=, 16
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; BULK-MEM-NEXT: i32.sub $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]]
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; BULK-MEM-NEXT: i32.const $push[[L3:[0-9]+]]=, 6
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; BULK-MEM-NEXT: i32.add $push[[L4:[0-9]+]]=, $pop[[L2]], $pop[[L3]]
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; BULK-MEM-NEXT: i32.const $push[[L5:[0-9]+]]=, 10
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; BULK-MEM-NEXT: memory.fill 0, $pop[[L4]], $0, $pop[[L5]]
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; BULK-MEM-NEXT: return
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define void @memset_alloca(i8 %val) {
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%a = alloca [10 x i8]
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%p = bitcast [10 x i8]* %a to i8*
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call void @llvm.memset.p0i8.i32(i8* %p, i8 %val, i32 10, i1 false)
|
||||
ret void
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user