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[DAG] hoist DL(N) and fix formatting; NFC
llvm-svn: 284170
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af8dd6b82e
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@ -1694,6 +1694,7 @@ SDValue DAGCombiner::visitADD(SDNode *N) {
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SDValue N0 = N->getOperand(0);
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SDValue N1 = N->getOperand(1);
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EVT VT = N0.getValueType();
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SDLoc DL(N);
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// fold vector ops
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if (VT.isVector()) {
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@ -1710,62 +1711,73 @@ SDValue DAGCombiner::visitADD(SDNode *N) {
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// fold (add x, undef) -> undef
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if (N0.isUndef())
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return N0;
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if (N1.isUndef())
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return N1;
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if (DAG.isConstantIntBuildVectorOrConstantInt(N0)) {
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// canonicalize constant to RHS
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if (!DAG.isConstantIntBuildVectorOrConstantInt(N1))
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return DAG.getNode(ISD::ADD, SDLoc(N), VT, N1, N0);
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return DAG.getNode(ISD::ADD, DL, VT, N1, N0);
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// fold (add c1, c2) -> c1+c2
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return DAG.FoldConstantArithmetic(ISD::ADD, SDLoc(N), VT,
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N0.getNode(), N1.getNode());
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return DAG.FoldConstantArithmetic(ISD::ADD, DL, VT, N0.getNode(),
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N1.getNode());
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}
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// fold (add x, 0) -> x
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if (isNullConstant(N1))
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return N0;
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// fold ((c1-A)+c2) -> (c1+c2)-A
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if (isConstantOrConstantVector(N1, /* NoOpaque */ true)) {
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if (N0.getOpcode() == ISD::SUB)
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if (isConstantOrConstantVector(N0.getOperand(0), /* NoOpaque */ true)) {
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SDLoc DL(N);
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return DAG.getNode(ISD::SUB, DL, VT,
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DAG.getNode(ISD::ADD, DL, VT, N1, N0.getOperand(0)),
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N0.getOperand(1));
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}
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}
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// reassociate add
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if (SDValue RADD = ReassociateOps(ISD::ADD, SDLoc(N), N0, N1))
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if (SDValue RADD = ReassociateOps(ISD::ADD, DL, N0, N1))
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return RADD;
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// fold ((0-A) + B) -> B-A
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if (N0.getOpcode() == ISD::SUB &&
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isNullConstantOrNullSplatConstant(N0.getOperand(0)))
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return DAG.getNode(ISD::SUB, SDLoc(N), VT, N1, N0.getOperand(1));
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return DAG.getNode(ISD::SUB, DL, VT, N1, N0.getOperand(1));
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// fold (A + (0-B)) -> A-B
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if (N1.getOpcode() == ISD::SUB &&
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isNullConstantOrNullSplatConstant(N1.getOperand(0)))
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return DAG.getNode(ISD::SUB, SDLoc(N), VT, N0, N1.getOperand(1));
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return DAG.getNode(ISD::SUB, DL, VT, N0, N1.getOperand(1));
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// fold (A+(B-A)) -> B
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if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
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return N1.getOperand(0);
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// fold ((B-A)+A) -> B
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if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1))
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return N0.getOperand(0);
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// fold (A+(B-(A+C))) to (B-C)
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if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
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N0 == N1.getOperand(1).getOperand(0))
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return DAG.getNode(ISD::SUB, SDLoc(N), VT, N1.getOperand(0),
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return DAG.getNode(ISD::SUB, DL, VT, N1.getOperand(0),
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N1.getOperand(1).getOperand(1));
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// fold (A+(B-(C+A))) to (B-C)
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if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
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N0 == N1.getOperand(1).getOperand(1))
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return DAG.getNode(ISD::SUB, SDLoc(N), VT, N1.getOperand(0),
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return DAG.getNode(ISD::SUB, DL, VT, N1.getOperand(0),
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N1.getOperand(1).getOperand(0));
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// fold (A+((B-A)+or-C)) to (B+or-C)
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if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) &&
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N1.getOperand(0).getOpcode() == ISD::SUB &&
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N0 == N1.getOperand(0).getOperand(1))
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return DAG.getNode(N1.getOpcode(), SDLoc(N), VT,
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N1.getOperand(0).getOperand(0), N1.getOperand(1));
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return DAG.getNode(N1.getOpcode(), DL, VT, N1.getOperand(0).getOperand(0),
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N1.getOperand(1));
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// fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant
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if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) {
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@ -1774,9 +1786,8 @@ SDValue DAGCombiner::visitADD(SDNode *N) {
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SDValue N10 = N1.getOperand(0);
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SDValue N11 = N1.getOperand(1);
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if (isConstantOrConstantVector(N00) ||
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isConstantOrConstantVector(N10))
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return DAG.getNode(ISD::SUB, SDLoc(N), VT,
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if (isConstantOrConstantVector(N00) || isConstantOrConstantVector(N10))
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return DAG.getNode(ISD::SUB, DL, VT,
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DAG.getNode(ISD::ADD, SDLoc(N0), VT, N00, N10),
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DAG.getNode(ISD::ADD, SDLoc(N1), VT, N01, N11));
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}
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@ -1787,19 +1798,19 @@ SDValue DAGCombiner::visitADD(SDNode *N) {
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// fold (a+b) -> (a|b) iff a and b share no bits.
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if ((!LegalOperations || TLI.isOperationLegal(ISD::OR, VT)) &&
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VT.isInteger() && DAG.haveNoCommonBitsSet(N0, N1))
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return DAG.getNode(ISD::OR, SDLoc(N), VT, N0, N1);
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return DAG.getNode(ISD::OR, DL, VT, N0, N1);
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// fold (add x, shl(0 - y, n)) -> sub(x, shl(y, n))
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if (N1.getOpcode() == ISD::SHL && N1.getOperand(0).getOpcode() == ISD::SUB &&
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isNullConstantOrNullSplatConstant(N1.getOperand(0).getOperand(0)))
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return DAG.getNode(ISD::SUB, SDLoc(N), VT, N0,
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DAG.getNode(ISD::SHL, SDLoc(N), VT,
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return DAG.getNode(ISD::SUB, DL, VT, N0,
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DAG.getNode(ISD::SHL, DL, VT,
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N1.getOperand(0).getOperand(1),
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N1.getOperand(1)));
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if (N0.getOpcode() == ISD::SHL && N0.getOperand(0).getOpcode() == ISD::SUB &&
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isNullConstantOrNullSplatConstant(N0.getOperand(0).getOperand(0)))
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return DAG.getNode(ISD::SUB, SDLoc(N), VT, N1,
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DAG.getNode(ISD::SHL, SDLoc(N), VT,
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return DAG.getNode(ISD::SUB, DL, VT, N1,
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DAG.getNode(ISD::SHL, DL, VT,
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N0.getOperand(0).getOperand(1),
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N0.getOperand(1)));
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@ -1811,17 +1822,14 @@ SDValue DAGCombiner::visitADD(SDNode *N) {
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// (add z, (and (sbbl x, x), 1)) -> (sub z, (sbbl x, x))
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// and similar xforms where the inner op is either ~0 or 0.
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if (NumSignBits == DestBits &&
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isOneConstantOrOneSplatConstant(N1->getOperand(1))) {
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SDLoc DL(N);
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isOneConstantOrOneSplatConstant(N1->getOperand(1)))
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return DAG.getNode(ISD::SUB, DL, VT, N->getOperand(0), AndOp0);
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}
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}
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// add (sext i1), X -> sub X, (zext i1)
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if (N0.getOpcode() == ISD::SIGN_EXTEND &&
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N0.getOperand(0).getValueType() == MVT::i1 &&
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!TLI.isOperationLegal(ISD::SIGN_EXTEND, MVT::i1)) {
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SDLoc DL(N);
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SDValue ZExt = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0));
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return DAG.getNode(ISD::SUB, DL, VT, N1, ZExt);
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}
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@ -1830,7 +1838,6 @@ SDValue DAGCombiner::visitADD(SDNode *N) {
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if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) {
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VTSDNode *TN = cast<VTSDNode>(N1.getOperand(1));
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if (TN->getVT() == MVT::i1) {
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SDLoc DL(N);
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SDValue ZExt = DAG.getNode(ISD::AND, DL, VT, N1.getOperand(0),
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DAG.getConstant(1, DL, VT));
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return DAG.getNode(ISD::SUB, DL, VT, N0, ZExt);
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