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fix an oversight which caused us to compile the testcase (and other
less trivial things) into a dummy lea. Before we generated: _test: ## @test movq _G@GOTPCREL(%rip), %rax leaq (%rax), %rax ret now we produce: _test: ## @test movq _G@GOTPCREL(%rip), %rax ret This is part of rdar://9289558 llvm-svn: 129662
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@ -421,10 +421,9 @@ bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
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return true;
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}
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void
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SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin,
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BasicBlock::const_iterator End,
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bool &HadTailCall) {
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void SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin,
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BasicBlock::const_iterator End,
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bool &HadTailCall) {
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// Lower all of the non-terminator instructions. If a call is emitted
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// as a tail call, cease emitting nodes for this block. Terminators
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// are handled below.
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@ -438,7 +437,6 @@ SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin,
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// Final step, emit the lowered DAG as machine code.
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CodeGenAndEmitDAG();
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return;
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}
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void SelectionDAGISel::ComputeLiveOutVRegInfo() {
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@ -1859,10 +1859,13 @@ unsigned X86FastISel::TargetMaterializeConstant(const Constant *C) {
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if (isa<GlobalValue>(C)) {
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X86AddressMode AM;
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if (X86SelectAddress(C, AM)) {
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if (TLI.getPointerTy() == MVT::i32)
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Opc = X86::LEA32r;
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else
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Opc = X86::LEA64r;
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// If the expression is just a basereg, then we're done, otherwise we need
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// to emit an LEA.
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if (AM.BaseType == X86AddressMode::RegBase &&
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AM.IndexReg == 0 && AM.Disp == 0 && AM.GV == 0)
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return AM.Base.Reg;
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Opc = TLI.getPointerTy() == MVT::i32 ? X86::LEA32r : X86::LEA64r;
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unsigned ResultReg = createResultReg(RC);
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addFullAddress(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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TII.get(Opc), ResultReg), AM);
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@ -33,3 +33,15 @@ if.end: ; preds = %if.then, %entry
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; CHECK: test2:
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; CHECK: movq %rdi, -8(%rsp)
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; CHECK: cmpq $42, -8(%rsp)
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@G = external global i32
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define i64 @test3() nounwind {
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%A = ptrtoint i32* @G to i64
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ret i64 %A
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}
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; CHECK: test3:
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; CHECK: movq _G@GOTPCREL(%rip), %rax
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; CHECK-NEXT: ret
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