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Use the right kind of booleans: we were emitting 0/1 booleans, instead of 0/-1
booleans. Patch by James Benton. llvm-svn: 159739
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commit
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@ -2390,21 +2390,29 @@ TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
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}
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if (N0 == N1) {
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// The sext(setcc()) => setcc() optimization relies on the appropriate
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// constant being emitted.
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uint64_t EqVal;
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switch (getBooleanContents(N0.getValueType().isVector())) {
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default: llvm_unreachable("Unknown boolean contents!");
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case UndefinedBooleanContent:
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case ZeroOrOneBooleanContent:
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EqVal = ISD::isTrueWhenEqual(Cond);
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break;
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case ZeroOrNegativeOneBooleanContent:
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EqVal = ISD::isTrueWhenEqual(Cond) ? -1 : 0;
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break;
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}
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// We can always fold X == X for integer setcc's.
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if (N0.getValueType().isInteger()) {
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switch (getBooleanContents(N0.getValueType().isVector())) {
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case UndefinedBooleanContent:
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case ZeroOrOneBooleanContent:
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return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
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case ZeroOrNegativeOneBooleanContent:
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return DAG.getConstant(ISD::isTrueWhenEqual(Cond) ? -1 : 0, VT);
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}
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return DAG.getConstant(EqVal, VT);
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}
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unsigned UOF = ISD::getUnorderedFlavor(Cond);
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if (UOF == 2) // FP operators that are undefined on NaNs.
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return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
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return DAG.getConstant(EqVal, VT);
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if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
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return DAG.getConstant(UOF, VT);
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return DAG.getConstant(EqVal, VT);
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// Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
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// if it is not already.
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ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
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55
test/CodeGen/X86/sext-setcc-self.ll
Normal file
55
test/CodeGen/X86/sext-setcc-self.ll
Normal file
@ -0,0 +1,55 @@
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; RUN: llc -march=x86 -mcpu=nehalem < %s | FileCheck %s
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define <4 x i32> @test_ueq(<4 x float> %in) {
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entry:
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; CHECK: pcmpeqd %xmm0, %xmm0
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; CHECK-NEXT: ret
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%0 = fcmp ueq <4 x float> %in, %in
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%1 = sext <4 x i1> %0 to <4 x i32>
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ret <4 x i32> %1
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}
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define <4 x i32> @test_uge(<4 x float> %in) {
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entry:
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; CHECK: pcmpeqd %xmm0, %xmm0
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; CHECK-NEXT: ret
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%0 = fcmp uge <4 x float> %in, %in
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%1 = sext <4 x i1> %0 to <4 x i32>
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ret <4 x i32> %1
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}
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define <4 x i32> @test_ule(<4 x float> %in) {
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entry:
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; CHECK: pcmpeqd %xmm0, %xmm0
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; CHECK-NEXT: ret
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%0 = fcmp ule <4 x float> %in, %in
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%1 = sext <4 x i1> %0 to <4 x i32>
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ret <4 x i32> %1
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}
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define <4 x i32> @test_one(<4 x float> %in) {
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entry:
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; CHECK: xorps %xmm0, %xmm0
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; CHECK-NEXT: ret
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%0 = fcmp one <4 x float> %in, %in
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%1 = sext <4 x i1> %0 to <4 x i32>
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ret <4 x i32> %1
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}
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define <4 x i32> @test_ogt(<4 x float> %in) {
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entry:
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; CHECK: xorps %xmm0, %xmm0
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; CHECK-NEXT: ret
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%0 = fcmp ogt <4 x float> %in, %in
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%1 = sext <4 x i1> %0 to <4 x i32>
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ret <4 x i32> %1
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}
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define <4 x i32> @test_olt(<4 x float> %in) {
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entry:
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; CHECK: xorps %xmm0, %xmm0
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; CHECK-NEXT: ret
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%0 = fcmp olt <4 x float> %in, %in
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%1 = sext <4 x i1> %0 to <4 x i32>
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ret <4 x i32> %1
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}
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