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[llvm-exegesis][mips] Add SnippetGeneratorTest unit test

Test latency with explicit register dependency, without and with
forbidden registers.

Differential Revision: https://reviews.llvm.org/D71471
This commit is contained in:
Miloš Stojanović 2019-12-16 16:49:09 +01:00
parent ba8a8f5cc6
commit f9f3b550e4
2 changed files with 112 additions and 0 deletions

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@ -15,6 +15,7 @@ set(LLVM_LINK_COMPONENTS
add_llvm_unittest(LLVMExegesisMipsTests
BenchmarkResultTest.cpp
SnippetGeneratorTest.cpp
TargetTest.cpp
)
target_link_libraries(LLVMExegesisMipsTests PRIVATE

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@ -0,0 +1,111 @@
//===-- SnippetGeneratorTest.cpp --------------------------------*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
#include "../Common/AssemblerUtils.h"
#include "Latency.h"
#include "LlvmState.h"
#include "MCInstrDescView.h"
#include "RegisterAliasing.h"
#include "MipsInstrInfo.h"
#include <unordered_set>
namespace llvm {
namespace exegesis {
void InitializeMipsExegesisTarget();
namespace {
using testing::AnyOf;
using testing::ElementsAre;
using testing::SizeIs;
MATCHER(IsInvalid, "") { return !arg.isValid(); }
MATCHER(IsReg, "") { return arg.isReg(); }
class MipsSnippetGeneratorTest : public ::testing::Test {
protected:
MipsSnippetGeneratorTest() : State("mips-unknown-linux", "mips32"),
InstrInfo(State.getInstrInfo()) {}
static void SetUpTestCase() {
LLVMInitializeMipsTargetInfo();
LLVMInitializeMipsTarget();
LLVMInitializeMipsTargetMC();
InitializeMipsExegesisTarget();
}
LLVMState State;
const MCInstrInfo &InstrInfo;
};
template <typename SnippetGeneratorT>
class SnippetGeneratorTest : public MipsSnippetGeneratorTest {
protected:
SnippetGeneratorTest() : Generator(State, SnippetGenerator::Options()) {}
std::vector<CodeTemplate> checkAndGetCodeTemplates(unsigned Opcode) {
randomGenerator().seed(0); // Initialize seed.
const Instruction &Instr = State.getIC().getInstr(Opcode);
auto CodeTemplateOrError = Generator.generateCodeTemplates(
Instr, State.getRATC().emptyRegisters());
EXPECT_FALSE(CodeTemplateOrError.takeError()); // Valid configuration.
return std::move(CodeTemplateOrError.get());
}
SnippetGeneratorT Generator;
};
using LatencySnippetGeneratorTest =
SnippetGeneratorTest<LatencySnippetGenerator>;
TEST_F(LatencySnippetGeneratorTest, ImplicitSelfDependencyThroughExplicitRegs) {
// - ADD
// - Op0 Explicit Def RegClass(GPR32)
// - Op1 Explicit Use RegClass(GPR32)
// - Op2 Explicit Use RegClass(GPR32)
// - Var0 [Op0]
// - Var1 [Op1]
// - Var2 [Op2]
const unsigned Opcode = Mips::ADD;
const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
ASSERT_THAT(CodeTemplates, SizeIs(1));
const auto &CT = CodeTemplates[0];
EXPECT_THAT(CT.Execution, ExecutionMode::SERIAL_VIA_EXPLICIT_REGS);
ASSERT_THAT(CT.Instructions, SizeIs(1));
const InstructionTemplate &IT = CT.Instructions[0];
EXPECT_THAT(IT.getOpcode(), Opcode);
ASSERT_THAT(IT.VariableValues, SizeIs(3));
EXPECT_THAT(IT.VariableValues,
AnyOf(ElementsAre(IsReg(), IsInvalid(), IsReg()),
ElementsAre(IsReg(), IsReg(), IsInvalid())))
<< "Op0 is either set to Op1 or to Op2";
}
TEST_F(LatencySnippetGeneratorTest,
ImplicitSelfDependencyThroughExplicitRegsForbidAll) {
// - XOR
// - Op0 Explicit Def RegClass(GPR32)
// - Op1 Explicit Use RegClass(GPR32)
// - Op2 Explicit Use RegClass(GPR32)
// - Var0 [Op0]
// - Var1 [Op1]
// - Var2 [Op2]
randomGenerator().seed(0); // Initialize seed.
const Instruction &Instr = State.getIC().getInstr(Mips::XOR);
auto AllRegisters = State.getRATC().emptyRegisters();
AllRegisters.flip();
auto Error = Generator.generateCodeTemplates(Instr, AllRegisters).takeError();
EXPECT_TRUE((bool)Error);
consumeError(std::move(Error));
}
} // namespace
} // namespace exegesis
} // namespace llvm