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Split some PPC itinerary classes
In preparation for adding scheduling definitions for the POWER7, split some PPC itinerary classes so that the P7's latencies and hazards can be better described. For the most part, this means differentiating indexed from non-index pre-increment loads and stores. Also, differentiate single from double-precision sqrt. No functionality change intended (except for a more-specific latency for single-precision sqrt on the A2). llvm-svn: 195980
This commit is contained in:
Hal Finkel
parent
14673817db
commit
fa2b249f38
@ -276,7 +276,7 @@ def MTCRF8 : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, g8rc:$rS),
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let hasExtraSrcRegAllocReq = 1 in // to enable post-ra anti-dep breaking.
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def MFOCRF8: XFXForm_5a<31, 19, (outs g8rc:$rT), (ins crbitm:$FXM),
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"mfocrf $rT, $FXM", IIC_SprMFCR>,
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"mfocrf $rT, $FXM", IIC_SprMFCRF>,
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PPC970_DGroup_First, PPC970_Unit_CRU;
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def MFCR8 : XFXForm_3<31, 19, (outs g8rc:$rT), (ins),
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@ -665,12 +665,12 @@ def LHAU8 : DForm_1<43, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
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let Interpretation64Bit = 1 in
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def LHAUX8 : XForm_1<31, 375, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
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(ins memrr:$addr),
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"lhaux $rD, $addr", IIC_LdStLHAU,
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"lhaux $rD, $addr", IIC_LdStLHAUX,
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[]>, RegConstraint<"$addr.ptrreg = $ea_result">,
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NoEncode<"$ea_result">;
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def LWAUX : XForm_1<31, 373, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
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(ins memrr:$addr),
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"lwaux $rD, $addr", IIC_LdStLHAU,
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"lwaux $rD, $addr", IIC_LdStLHAUX,
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[]>, RegConstraint<"$addr.ptrreg = $ea_result">,
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NoEncode<"$ea_result">, isPPC64;
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}
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@ -717,17 +717,17 @@ def LWZU8 : DForm_1<33, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$add
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def LBZUX8 : XForm_1<31, 119, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
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(ins memrr:$addr),
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"lbzux $rD, $addr", IIC_LdStLoadUpd,
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"lbzux $rD, $addr", IIC_LdStLoadUpdX,
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[]>, RegConstraint<"$addr.ptrreg = $ea_result">,
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NoEncode<"$ea_result">;
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def LHZUX8 : XForm_1<31, 311, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
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(ins memrr:$addr),
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"lhzux $rD, $addr", IIC_LdStLoadUpd,
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"lhzux $rD, $addr", IIC_LdStLoadUpdX,
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[]>, RegConstraint<"$addr.ptrreg = $ea_result">,
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NoEncode<"$ea_result">;
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def LWZUX8 : XForm_1<31, 55, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
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(ins memrr:$addr),
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"lwzux $rD, $addr", IIC_LdStLoadUpd,
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"lwzux $rD, $addr", IIC_LdStLoadUpdX,
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[]>, RegConstraint<"$addr.ptrreg = $ea_result">,
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NoEncode<"$ea_result">;
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}
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@ -782,7 +782,7 @@ def LDU : DSForm_1<58, 1, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memrix:
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def LDUX : XForm_1<31, 53, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
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(ins memrr:$addr),
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"ldux $rD, $addr", IIC_LdStLDU,
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"ldux $rD, $addr", IIC_LdStLDUX,
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[]>, RegConstraint<"$addr.ptrreg = $ea_result">,
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NoEncode<"$ea_result">, isPPC64;
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}
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@ -936,7 +936,7 @@ def STWUX8: XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$d
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} // Interpretation64Bit
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def STDUX : XForm_8<31, 181, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst),
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"stdux $rS, $dst", IIC_LdStSTDU, []>,
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"stdux $rS, $dst", IIC_LdStSTDUX, []>,
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RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
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PPC970_DGroup_Cracked, isPPC64;
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}
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@ -1330,37 +1330,37 @@ def LFDU : DForm_1<51, (outs f8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr
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// Indexed (r+r) Loads with Update (preinc).
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def LBZUX : XForm_1<31, 119, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
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(ins memrr:$addr),
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"lbzux $rD, $addr", IIC_LdStLoadUpd,
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"lbzux $rD, $addr", IIC_LdStLoadUpdX,
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[]>, RegConstraint<"$addr.ptrreg = $ea_result">,
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NoEncode<"$ea_result">;
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def LHAUX : XForm_1<31, 375, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
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(ins memrr:$addr),
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"lhaux $rD, $addr", IIC_LdStLHAU,
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"lhaux $rD, $addr", IIC_LdStLHAUX,
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[]>, RegConstraint<"$addr.ptrreg = $ea_result">,
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NoEncode<"$ea_result">;
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def LHZUX : XForm_1<31, 311, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
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(ins memrr:$addr),
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"lhzux $rD, $addr", IIC_LdStLoadUpd,
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"lhzux $rD, $addr", IIC_LdStLoadUpdX,
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[]>, RegConstraint<"$addr.ptrreg = $ea_result">,
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NoEncode<"$ea_result">;
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def LWZUX : XForm_1<31, 55, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
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(ins memrr:$addr),
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"lwzux $rD, $addr", IIC_LdStLoadUpd,
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"lwzux $rD, $addr", IIC_LdStLoadUpdX,
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[]>, RegConstraint<"$addr.ptrreg = $ea_result">,
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NoEncode<"$ea_result">;
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def LFSUX : XForm_1<31, 567, (outs f4rc:$rD, ptr_rc_nor0:$ea_result),
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(ins memrr:$addr),
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"lfsux $rD, $addr", IIC_LdStLFDU,
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"lfsux $rD, $addr", IIC_LdStLFDUX,
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[]>, RegConstraint<"$addr.ptrreg = $ea_result">,
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NoEncode<"$ea_result">;
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def LFDUX : XForm_1<31, 631, (outs f8rc:$rD, ptr_rc_nor0:$ea_result),
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(ins memrr:$addr),
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"lfdux $rD, $addr", IIC_LdStLFDU,
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"lfdux $rD, $addr", IIC_LdStLFDUX,
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[]>, RegConstraint<"$addr.ptrreg = $ea_result">,
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NoEncode<"$ea_result">;
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}
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@ -1740,10 +1740,10 @@ let Uses = [RM] in {
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[(set f32:$frD, (ffloor f32:$frB))]>;
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defm FSQRT : XForm_26r<63, 22, (outs f8rc:$frD), (ins f8rc:$frB),
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"fsqrt", "$frD, $frB", IIC_FPSqrt,
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"fsqrt", "$frD, $frB", IIC_FPSqrtD,
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[(set f64:$frD, (fsqrt f64:$frB))]>;
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defm FSQRTS : XForm_26r<59, 22, (outs f4rc:$frD), (ins f4rc:$frB),
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"fsqrts", "$frD, $frB", IIC_FPSqrt,
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"fsqrts", "$frD, $frB", IIC_FPSqrtS,
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[(set f32:$frD, (fsqrt f32:$frB))]>;
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}
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}
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@ -1948,7 +1948,7 @@ def MTCRF : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, gprc:$rS),
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let hasExtraSrcRegAllocReq = 1 in // to enable post-ra anti-dep breaking.
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def MFOCRF: XFXForm_5a<31, 19, (outs gprc:$rT), (ins crbitm:$FXM),
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"mfocrf $rT, $FXM", IIC_SprMFCR>,
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"mfocrf $rT, $FXM", IIC_SprMFCRF>,
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PPC970_DGroup_First, PPC970_Unit_CRU;
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def MFCR : XFXForm_3<31, 19, (outs gprc:$rT), (ins),
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@ -39,17 +39,21 @@ def IIC_LdStDCBF : InstrItinClass;
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def IIC_LdStDCBI : InstrItinClass;
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def IIC_LdStLoad : InstrItinClass;
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def IIC_LdStLoadUpd : InstrItinClass;
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def IIC_LdStLoadUpdX : InstrItinClass;
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def IIC_LdStStore : InstrItinClass;
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def IIC_LdStStoreUpd : InstrItinClass;
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def IIC_LdStDSS : InstrItinClass;
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def IIC_LdStICBI : InstrItinClass;
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def IIC_LdStLD : InstrItinClass;
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def IIC_LdStLDU : InstrItinClass;
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def IIC_LdStLDUX : InstrItinClass;
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def IIC_LdStLDARX : InstrItinClass;
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def IIC_LdStLFD : InstrItinClass;
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def IIC_LdStLFDU : InstrItinClass;
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def IIC_LdStLFDUX : InstrItinClass;
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def IIC_LdStLHA : InstrItinClass;
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def IIC_LdStLHAU : InstrItinClass;
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def IIC_LdStLHAUX : InstrItinClass;
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def IIC_LdStLMW : InstrItinClass;
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def IIC_LdStLVecX : InstrItinClass;
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def IIC_LdStLWA : InstrItinClass;
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@ -59,6 +63,7 @@ def IIC_LdStSLBIE : InstrItinClass;
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def IIC_LdStSTD : InstrItinClass;
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def IIC_LdStSTDCX : InstrItinClass;
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def IIC_LdStSTDU : InstrItinClass;
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def IIC_LdStSTDUX : InstrItinClass;
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def IIC_LdStSTFD : InstrItinClass;
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def IIC_LdStSTFDU : InstrItinClass;
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def IIC_LdStSTVEBX : InstrItinClass;
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@ -70,6 +75,7 @@ def IIC_SprMTMSR : InstrItinClass;
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def IIC_SprMTSR : InstrItinClass;
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def IIC_SprTLBSYNC : InstrItinClass;
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def IIC_SprMFCR : InstrItinClass;
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def IIC_SprMFCRF : InstrItinClass;
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def IIC_SprMFMSR : InstrItinClass;
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def IIC_SprMFSPR : InstrItinClass;
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def IIC_SprMFTB : InstrItinClass;
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@ -84,7 +90,8 @@ def IIC_FPDivD : InstrItinClass;
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def IIC_FPDivS : InstrItinClass;
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def IIC_FPFused : InstrItinClass;
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def IIC_FPRes : InstrItinClass;
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def IIC_FPSqrt : InstrItinClass;
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def IIC_FPSqrtD : InstrItinClass;
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def IIC_FPSqrtS : InstrItinClass;
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def IIC_VecGeneral : InstrItinClass;
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def IIC_VecFP : InstrItinClass;
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def IIC_VecFPCompare : InstrItinClass;
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@ -202,37 +209,37 @@ include "PPCScheduleE5500.td"
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// frsp IIC_FPGeneral
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// frsqrte IIC_FPGeneral
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// fsel IIC_FPGeneral
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// fsqrt IIC_FPSqrt
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// fsqrts IIC_FPSqrt
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// fsqrt IIC_FPSqrtD
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// fsqrts IIC_FPSqrtS
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// fsub IIC_FPAddSub
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// fsubs IIC_FPGeneral
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// icbi IIC_LdStICBI
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// isync IIC_SprISYNC
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// lbz IIC_LdStLoad
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// lbzu IIC_LdStLoadUpd
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// lbzux IIC_LdStLoadUpd
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// lbzux IIC_LdStLoadUpdX
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// lbzx IIC_LdStLoad
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// ld IIC_LdStLD
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// ldarx IIC_LdStLDARX
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// ldu IIC_LdStLDU
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// ldux IIC_LdStLDU
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// ldux IIC_LdStLDUX
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// ldx IIC_LdStLD
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// lfd IIC_LdStLFD
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// lfdu IIC_LdStLFDU
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// lfdux IIC_LdStLFDU
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// lfdux IIC_LdStLFDUX
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// lfdx IIC_LdStLFD
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// lfs IIC_LdStLFD
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// lfsu IIC_LdStLFDU
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// lfsux IIC_LdStLFDU
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// lfsux IIC_LdStLFDUX
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// lfsx IIC_LdStLFD
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// lha IIC_LdStLHA
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// lhau IIC_LdStLHAU
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// lhaux IIC_LdStLHAU
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// lhaux IIC_LdStLHAUX
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// lhax IIC_LdStLHA
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// lhbrx IIC_LdStLoad
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// lhz IIC_LdStLoad
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// lhzu IIC_LdStLoadUpd
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// lhzux IIC_LdStLoadUpd
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// lhzux IIC_LdStLoadUpdX
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// lhzx IIC_LdStLoad
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// lmw IIC_LdStLMW
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// lswi IIC_LdStLMW
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@ -246,12 +253,12 @@ include "PPCScheduleE5500.td"
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// lvxl IIC_LdStLVecX
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// lwa IIC_LdStLWA
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// lwarx IIC_LdStLWARX
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// lwaux IIC_LdStLHAU
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// lwaux IIC_LdStLHAUX
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// lwax IIC_LdStLHA
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// lwbrx IIC_LdStLoad
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// lwz IIC_LdStLoad
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// lwzu IIC_LdStLoadUpd
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// lwzux IIC_LdStLoadUpd
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// lwzux IIC_LdStLoadUpdX
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// lwzx IIC_LdStLoad
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// mcrf IIC_BrMCR
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// mcrfs IIC_FPGeneral
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@ -320,7 +327,7 @@ include "PPCScheduleE5500.td"
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// std IIC_LdStSTD
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// stdcx. IIC_LdStSTDCX
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// stdu IIC_LdStSTDU
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// stdux IIC_LdStSTDU
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// stdux IIC_LdStSTDUX
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// stdx IIC_LdStSTD
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// stfd IIC_LdStSTFD
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// stfdu IIC_LdStSTFDU
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@ -258,6 +258,13 @@ def PPC440Itineraries : ProcessorItineraries<
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InstrStage<2, [P440_LWB]>],
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[5, 2, 1, 1],
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[P440_GPR_Bypass, P440_GPR_Bypass]>,
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InstrItinData<IIC_LdStLoadUpdX,[InstrStage<1, [P440_DISS1, P440_DISS2]>,
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InstrStage<1, [P440_LRACC]>,
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InstrStage<1, [P440_AGEN]>,
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InstrStage<1, [P440_CRD]>,
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InstrStage<2, [P440_LWB]>],
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[5, 2, 1, 1],
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[P440_GPR_Bypass, P440_GPR_Bypass]>,
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InstrItinData<IIC_LdStStore, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
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InstrStage<1, [P440_LRACC]>,
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InstrStage<1, [P440_AGEN]>,
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@ -307,6 +314,13 @@ def PPC440Itineraries : ProcessorItineraries<
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InstrStage<1, [P440_LWB]>],
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[5, 2, 1, 1],
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[NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
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InstrItinData<IIC_LdStLFDUX, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
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InstrStage<1, [P440_LRACC]>,
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InstrStage<1, [P440_AGEN]>,
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InstrStage<1, [P440_CRD]>,
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InstrStage<1, [P440_LWB]>],
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[5, 2, 1, 1],
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[NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
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InstrItinData<IIC_LdStLHA, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
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InstrStage<1, [P440_LRACC]>,
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InstrStage<1, [P440_AGEN]>,
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@ -321,6 +335,13 @@ def PPC440Itineraries : ProcessorItineraries<
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InstrStage<1, [P440_LWB]>],
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[4, 1, 1],
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[NoBypass, P440_GPR_Bypass]>,
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InstrItinData<IIC_LdStLHAUX, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
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InstrStage<1, [P440_LRACC]>,
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InstrStage<1, [P440_AGEN]>,
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InstrStage<1, [P440_CRD]>,
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InstrStage<1, [P440_LWB]>],
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[4, 1, 1],
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[NoBypass, P440_GPR_Bypass]>,
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InstrItinData<IIC_LdStLMW, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
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InstrStage<1, [P440_LRACC]>,
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InstrStage<1, [P440_AGEN]>,
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@ -351,6 +372,13 @@ def PPC440Itineraries : ProcessorItineraries<
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InstrStage<2, [P440_LWB]>],
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[2, 1, 1, 1],
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[NoBypass, P440_GPR_Bypass]>,
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InstrItinData<IIC_LdStSTDUX, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
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InstrStage<1, [P440_LRACC]>,
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InstrStage<1, [P440_AGEN]>,
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InstrStage<1, [P440_CRD]>,
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InstrStage<2, [P440_LWB]>],
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[2, 1, 1, 1],
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[NoBypass, P440_GPR_Bypass]>,
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InstrItinData<IIC_LdStSTDCX, [InstrStage<1, [P440_DISS1]>,
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InstrStage<1, [P440_IRACC], 0>,
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InstrStage<4, [P440_LWARX_Hold], 0>,
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@ -71,8 +71,12 @@ def PPCA2Itineraries : ProcessorItineraries<
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[6, 0, 0]>,
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InstrItinData<IIC_LdStLoadUpd, [InstrStage<1, [A2_XU]>],
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[6, 8, 0, 0]>,
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InstrItinData<IIC_LdStLoadUpdX,[InstrStage<1, [A2_XU]>],
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[6, 8, 0, 0]>,
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InstrItinData<IIC_LdStLDU, [InstrStage<1, [A2_XU]>],
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[6, 0, 0]>,
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InstrItinData<IIC_LdStLDUX, [InstrStage<1, [A2_XU]>],
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[6, 0, 0]>,
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InstrItinData<IIC_LdStStore, [InstrStage<1, [A2_XU]>],
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[0, 0, 0]>,
|
||||
InstrItinData<IIC_LdStStoreUpd,[InstrStage<1, [A2_XU]>],
|
||||
@ -87,16 +91,22 @@ def PPCA2Itineraries : ProcessorItineraries<
|
||||
[7, 0, 0]>,
|
||||
InstrItinData<IIC_LdStLFDU, [InstrStage<1, [A2_XU]>],
|
||||
[7, 9, 0, 0]>,
|
||||
InstrItinData<IIC_LdStLFDUX, [InstrStage<1, [A2_XU]>],
|
||||
[7, 9, 0, 0]>,
|
||||
InstrItinData<IIC_LdStLHA, [InstrStage<1, [A2_XU]>],
|
||||
[6, 0, 0]>,
|
||||
InstrItinData<IIC_LdStLHAU, [InstrStage<1, [A2_XU]>],
|
||||
[6, 8, 0, 0]>,
|
||||
InstrItinData<IIC_LdStLHAUX, [InstrStage<1, [A2_XU]>],
|
||||
[6, 8, 0, 0]>,
|
||||
InstrItinData<IIC_LdStLWARX, [InstrStage<1, [A2_XU]>],
|
||||
[82, 0, 0]>, // L2 latency
|
||||
InstrItinData<IIC_LdStSTD, [InstrStage<1, [A2_XU]>],
|
||||
[0, 0, 0]>,
|
||||
InstrItinData<IIC_LdStSTDU, [InstrStage<1, [A2_XU]>],
|
||||
[2, 0, 0, 0]>,
|
||||
InstrItinData<IIC_LdStSTDUX, [InstrStage<1, [A2_XU]>],
|
||||
[2, 0, 0, 0]>,
|
||||
InstrItinData<IIC_LdStSTDCX, [InstrStage<1, [A2_XU]>],
|
||||
[82, 0, 0]>, // L2 latency
|
||||
InstrItinData<IIC_LdStSTWCX, [InstrStage<1, [A2_XU]>],
|
||||
@ -109,6 +119,8 @@ def PPCA2Itineraries : ProcessorItineraries<
|
||||
[16, 0]>,
|
||||
InstrItinData<IIC_SprMFCR, [InstrStage<1, [A2_XU]>],
|
||||
[6, 0]>,
|
||||
InstrItinData<IIC_SprMFCRF, [InstrStage<1, [A2_XU]>],
|
||||
[1, 0]>,
|
||||
InstrItinData<IIC_SprMFMSR, [InstrStage<1, [A2_XU]>],
|
||||
[4, 0]>,
|
||||
InstrItinData<IIC_SprMFSPR, [InstrStage<1, [A2_XU]>],
|
||||
@ -131,8 +143,10 @@ def PPCA2Itineraries : ProcessorItineraries<
|
||||
[72, 0, 0]>,
|
||||
InstrItinData<IIC_FPDivS, [InstrStage<1, [A2_FU]>],
|
||||
[59, 0, 0]>,
|
||||
InstrItinData<IIC_FPSqrt, [InstrStage<1, [A2_FU]>],
|
||||
InstrItinData<IIC_FPSqrtD, [InstrStage<1, [A2_FU]>],
|
||||
[69, 0, 0]>,
|
||||
InstrItinData<IIC_FPSqrtS, [InstrStage<1, [A2_FU]>],
|
||||
[65, 0, 0]>,
|
||||
InstrItinData<IIC_FPFused, [InstrStage<1, [A2_FU]>],
|
||||
[6, 0, 0, 0]>,
|
||||
InstrItinData<IIC_FPRes, [InstrStage<1, [A2_FU]>],
|
||||
|
||||
@ -141,6 +141,12 @@ def PPCE500mcItineraries : ProcessorItineraries<
|
||||
[6, 1], // Latency = 3
|
||||
[E500_GPR_Bypass, E500_GPR_Bypass],
|
||||
2>, // 2 micro-ops
|
||||
InstrItinData<IIC_LdStLoadUpdX,[InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
|
||||
InstrStage<1, [E500_SFX0, E500_SFX1], 0>,
|
||||
InstrStage<1, [E500_LSU_0]>],
|
||||
[6, 1], // Latency = 3
|
||||
[E500_GPR_Bypass, E500_GPR_Bypass],
|
||||
2>, // 2 micro-ops
|
||||
InstrItinData<IIC_LdStStore, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
|
||||
InstrStage<1, [E500_LSU_0]>],
|
||||
[6, 1], // Latency = 3
|
||||
@ -179,6 +185,13 @@ def PPCE500mcItineraries : ProcessorItineraries<
|
||||
[E500_FPR_Bypass,
|
||||
E500_GPR_Bypass, E500_GPR_Bypass],
|
||||
2>, // 2 micro-ops
|
||||
InstrItinData<IIC_LdStLFDUX, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
|
||||
InstrStage<1, [E500_SFX0, E500_SFX1], 0>,
|
||||
InstrStage<1, [E500_LSU_0]>],
|
||||
[7, 1, 1], // Latency = 4
|
||||
[E500_FPR_Bypass,
|
||||
E500_GPR_Bypass, E500_GPR_Bypass],
|
||||
2>, // 2 micro-ops
|
||||
InstrItinData<IIC_LdStLHA, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
|
||||
InstrStage<1, [E500_LSU_0]>],
|
||||
[6, 1], // Latency = 3
|
||||
@ -188,6 +201,11 @@ def PPCE500mcItineraries : ProcessorItineraries<
|
||||
InstrStage<1, [E500_LSU_0]>],
|
||||
[6, 1], // Latency = 3
|
||||
[E500_GPR_Bypass, E500_GPR_Bypass]>,
|
||||
InstrItinData<IIC_LdStLHAUX, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
|
||||
InstrStage<1, [E500_SFX0, E500_SFX1], 0>,
|
||||
InstrStage<1, [E500_LSU_0]>],
|
||||
[6, 1], // Latency = 3
|
||||
[E500_GPR_Bypass, E500_GPR_Bypass]>,
|
||||
InstrItinData<IIC_LdStLMW, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
|
||||
InstrStage<1, [E500_LSU_0]>],
|
||||
[7, 1], // Latency = r+3
|
||||
@ -221,6 +239,10 @@ def PPCE500mcItineraries : ProcessorItineraries<
|
||||
InstrStage<5, [E500_SFX0]>],
|
||||
[8, 1],
|
||||
[E500_GPR_Bypass, E500_CR_Bypass]>,
|
||||
InstrItinData<IIC_SprMFCRF, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
|
||||
InstrStage<5, [E500_SFX0]>],
|
||||
[8, 1],
|
||||
[E500_GPR_Bypass, E500_CR_Bypass]>,
|
||||
InstrItinData<IIC_SprMFMSR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
|
||||
InstrStage<4, [E500_SFX0]>],
|
||||
[7, 1], // Latency = 4, Repeat rate = 4
|
||||
|
||||
@ -170,6 +170,12 @@ def PPCE5500Itineraries : ProcessorItineraries<
|
||||
[7, 2], // Latency = 3, Repeat rate = 1
|
||||
[E5500_GPR_Bypass, E5500_GPR_Bypass],
|
||||
2>, // 2 micro-ops
|
||||
InstrItinData<IIC_LdStLoadUpdX,[InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
|
||||
InstrStage<1, [E5500_SFX0, E5500_SFX1], 0>,
|
||||
InstrStage<1, [E5500_LSU_0]>],
|
||||
[7, 2], // Latency = 3, Repeat rate = 1
|
||||
[E5500_GPR_Bypass, E5500_GPR_Bypass],
|
||||
2>, // 2 micro-ops
|
||||
InstrItinData<IIC_LdStLD, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
|
||||
InstrStage<1, [E5500_LSU_0]>],
|
||||
[7, 2], // Latency = 3, Repeat rate = 1
|
||||
@ -184,6 +190,12 @@ def PPCE5500Itineraries : ProcessorItineraries<
|
||||
[7, 2], // Latency = 3, Repeat rate = 1
|
||||
[E5500_GPR_Bypass, E5500_GPR_Bypass],
|
||||
2>, // 2 micro-ops
|
||||
InstrItinData<IIC_LdStLDUX, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
|
||||
InstrStage<1, [E5500_SFX0, E5500_SFX1], 0>,
|
||||
InstrStage<1, [E5500_LSU_0]>],
|
||||
[7, 2], // Latency = 3, Repeat rate = 1
|
||||
[E5500_GPR_Bypass, E5500_GPR_Bypass],
|
||||
2>, // 2 micro-ops
|
||||
InstrItinData<IIC_LdStStore, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
|
||||
InstrStage<1, [E5500_LSU_0]>],
|
||||
[7, 2], // Latency = 3, Repeat rate = 1
|
||||
@ -223,6 +235,13 @@ def PPCE5500Itineraries : ProcessorItineraries<
|
||||
[E5500_FPR_Bypass,
|
||||
E5500_GPR_Bypass, E5500_GPR_Bypass],
|
||||
2>, // 2 micro-ops
|
||||
InstrItinData<IIC_LdStLFDUX, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
|
||||
InstrStage<1, [E5500_SFX0, E5500_SFX1], 0>,
|
||||
InstrStage<1, [E5500_LSU_0]>],
|
||||
[8, 2, 2], // Latency = 4, Repeat rate = 1
|
||||
[E5500_FPR_Bypass,
|
||||
E5500_GPR_Bypass, E5500_GPR_Bypass],
|
||||
2>, // 2 micro-ops
|
||||
InstrItinData<IIC_LdStLHA, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
|
||||
InstrStage<1, [E5500_LSU_0]>],
|
||||
[7, 2], // Latency = 3
|
||||
@ -233,6 +252,12 @@ def PPCE5500Itineraries : ProcessorItineraries<
|
||||
[7, 2], // Latency = 3, Repeat rate = 1
|
||||
[E5500_GPR_Bypass, E5500_GPR_Bypass],
|
||||
2>, // 2 micro-ops
|
||||
InstrItinData<IIC_LdStLHAUX, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
|
||||
InstrStage<1, [E5500_SFX0, E5500_SFX1], 0>,
|
||||
InstrStage<1, [E5500_LSU_0]>],
|
||||
[7, 2], // Latency = 3, Repeat rate = 1
|
||||
[E5500_GPR_Bypass, E5500_GPR_Bypass],
|
||||
2>, // 2 micro-ops
|
||||
InstrItinData<IIC_LdStLMW, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
|
||||
InstrStage<4, [E5500_LSU_0]>],
|
||||
[8, 2], // Latency = r+3, Repeat rate = r+3
|
||||
@ -256,6 +281,12 @@ def PPCE5500Itineraries : ProcessorItineraries<
|
||||
[7, 2], // Latency = 3, Repeat rate = 1
|
||||
[NoBypass, E5500_GPR_Bypass],
|
||||
2>, // 2 micro-ops
|
||||
InstrItinData<IIC_LdStSTDUX, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
|
||||
InstrStage<1, [E5500_SFX0, E5500_SFX1], 0>,
|
||||
InstrStage<1, [E5500_LSU_0]>],
|
||||
[7, 2], // Latency = 3, Repeat rate = 1
|
||||
[NoBypass, E5500_GPR_Bypass],
|
||||
2>, // 2 micro-ops
|
||||
InstrItinData<IIC_LdStSTWCX, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
|
||||
InstrStage<1, [E5500_LSU_0]>],
|
||||
[7, 2], // Latency = 3, Repeat rate = 1
|
||||
@ -272,6 +303,10 @@ def PPCE5500Itineraries : ProcessorItineraries<
|
||||
InstrStage<5, [E5500_CFX_0]>],
|
||||
[9, 2], // Latency = 5, Repeat rate = 5
|
||||
[E5500_GPR_Bypass, E5500_CR_Bypass]>,
|
||||
InstrItinData<IIC_SprMFCRF, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
|
||||
InstrStage<5, [E5500_CFX_0]>],
|
||||
[9, 2], // Latency = 5, Repeat rate = 5
|
||||
[E5500_GPR_Bypass, E5500_CR_Bypass]>,
|
||||
InstrItinData<IIC_SprMFMSR, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
|
||||
InstrStage<4, [E5500_SFX0]>],
|
||||
[8, 2], // Latency = 4, Repeat rate = 4
|
||||
|
||||
@ -41,6 +41,7 @@ def G3Itineraries : ProcessorItineraries<
|
||||
InstrItinData<IIC_LdStDCBI , [InstrStage<3, [G3_SLU]>]>,
|
||||
InstrItinData<IIC_LdStLoad , [InstrStage<2, [G3_SLU]>]>,
|
||||
InstrItinData<IIC_LdStLoadUpd , [InstrStage<2, [G3_SLU]>]>,
|
||||
InstrItinData<IIC_LdStLoadUpdX, [InstrStage<2, [G3_SLU]>]>,
|
||||
InstrItinData<IIC_LdStStore , [InstrStage<2, [G3_SLU]>]>,
|
||||
InstrItinData<IIC_LdStStoreUpd, [InstrStage<2, [G3_SLU]>]>,
|
||||
InstrItinData<IIC_LdStICBI , [InstrStage<3, [G3_SLU]>]>,
|
||||
@ -48,8 +49,10 @@ def G3Itineraries : ProcessorItineraries<
|
||||
InstrItinData<IIC_LdStSTFDU , [InstrStage<2, [G3_SLU]>]>,
|
||||
InstrItinData<IIC_LdStLFD , [InstrStage<2, [G3_SLU]>]>,
|
||||
InstrItinData<IIC_LdStLFDU , [InstrStage<2, [G3_SLU]>]>,
|
||||
InstrItinData<IIC_LdStLFDUX , [InstrStage<2, [G3_SLU]>]>,
|
||||
InstrItinData<IIC_LdStLHA , [InstrStage<2, [G3_SLU]>]>,
|
||||
InstrItinData<IIC_LdStLHAU , [InstrStage<2, [G3_SLU]>]>,
|
||||
InstrItinData<IIC_LdStLHAUX , [InstrStage<2, [G3_SLU]>]>,
|
||||
InstrItinData<IIC_LdStLMW , [InstrStage<34, [G3_SLU]>]>,
|
||||
InstrItinData<IIC_LdStLWARX , [InstrStage<3, [G3_SLU]>]>,
|
||||
InstrItinData<IIC_LdStSTWCX , [InstrStage<8, [G3_SLU]>]>,
|
||||
|
||||
@ -46,6 +46,7 @@ def G4Itineraries : ProcessorItineraries<
|
||||
InstrItinData<IIC_LdStDCBI , [InstrStage<2, [G4_SLU]>]>,
|
||||
InstrItinData<IIC_LdStLoad , [InstrStage<2, [G4_SLU]>]>,
|
||||
InstrItinData<IIC_LdStLoadUpd , [InstrStage<2, [G4_SLU]>]>,
|
||||
InstrItinData<IIC_LdStLoadUpdX, [InstrStage<2, [G4_SLU]>]>,
|
||||
InstrItinData<IIC_LdStStore , [InstrStage<2, [G4_SLU]>]>,
|
||||
InstrItinData<IIC_LdStStoreUpd, [InstrStage<2, [G4_SLU]>]>,
|
||||
InstrItinData<IIC_LdStDSS , [InstrStage<2, [G4_SLU]>]>,
|
||||
@ -54,8 +55,10 @@ def G4Itineraries : ProcessorItineraries<
|
||||
InstrItinData<IIC_LdStSTFDU , [InstrStage<2, [G4_SLU]>]>,
|
||||
InstrItinData<IIC_LdStLFD , [InstrStage<2, [G4_SLU]>]>,
|
||||
InstrItinData<IIC_LdStLFDU , [InstrStage<2, [G4_SLU]>]>,
|
||||
InstrItinData<IIC_LdStLFDUX , [InstrStage<2, [G4_SLU]>]>,
|
||||
InstrItinData<IIC_LdStLHA , [InstrStage<2, [G4_SLU]>]>,
|
||||
InstrItinData<IIC_LdStLHAU , [InstrStage<2, [G4_SLU]>]>,
|
||||
InstrItinData<IIC_LdStLHAUX , [InstrStage<2, [G4_SLU]>]>,
|
||||
InstrItinData<IIC_LdStLMW , [InstrStage<34, [G4_SLU]>]>,
|
||||
InstrItinData<IIC_LdStLVecX , [InstrStage<2, [G4_SLU]>]>,
|
||||
InstrItinData<IIC_LdStLWARX , [InstrStage<3, [G4_SLU]>]>,
|
||||
|
||||
@ -54,6 +54,7 @@ def G4PlusItineraries : ProcessorItineraries<
|
||||
InstrItinData<IIC_LdStDCBI , [InstrStage<3, [G4P_SLU]>]>,
|
||||
InstrItinData<IIC_LdStLoad , [InstrStage<3, [G4P_SLU]>]>,
|
||||
InstrItinData<IIC_LdStLoadUpd , [InstrStage<3, [G4P_SLU]>]>,
|
||||
InstrItinData<IIC_LdStLoadUpdX, [InstrStage<3, [G4P_SLU]>]>,
|
||||
InstrItinData<IIC_LdStStore , [InstrStage<3, [G4P_SLU]>]>,
|
||||
InstrItinData<IIC_LdStStoreUpd, [InstrStage<3, [G4P_SLU]>]>,
|
||||
InstrItinData<IIC_LdStDSS , [InstrStage<3, [G4P_SLU]>]>,
|
||||
@ -62,8 +63,10 @@ def G4PlusItineraries : ProcessorItineraries<
|
||||
InstrItinData<IIC_LdStSTFDU , [InstrStage<3, [G4P_SLU]>]>,
|
||||
InstrItinData<IIC_LdStLFD , [InstrStage<4, [G4P_SLU]>]>,
|
||||
InstrItinData<IIC_LdStLFDU , [InstrStage<4, [G4P_SLU]>]>,
|
||||
InstrItinData<IIC_LdStLFDUX , [InstrStage<4, [G4P_SLU]>]>,
|
||||
InstrItinData<IIC_LdStLHA , [InstrStage<3, [G4P_SLU]>]>,
|
||||
InstrItinData<IIC_LdStLHAU , [InstrStage<3, [G4P_SLU]>]>,
|
||||
InstrItinData<IIC_LdStLHAUX , [InstrStage<3, [G4P_SLU]>]>,
|
||||
InstrItinData<IIC_LdStLMW , [InstrStage<37, [G4P_SLU]>]>,
|
||||
InstrItinData<IIC_LdStLVecX , [InstrStage<3, [G4P_SLU]>]>,
|
||||
InstrItinData<IIC_LdStLWA , [InstrStage<3, [G4P_SLU]>]>,
|
||||
@ -71,6 +74,7 @@ def G4PlusItineraries : ProcessorItineraries<
|
||||
InstrItinData<IIC_LdStSTD , [InstrStage<3, [G4P_SLU]>]>,
|
||||
InstrItinData<IIC_LdStSTDCX , [InstrStage<3, [G4P_SLU]>]>,
|
||||
InstrItinData<IIC_LdStSTDU , [InstrStage<3, [G4P_SLU]>]>,
|
||||
InstrItinData<IIC_LdStSTDUX , [InstrStage<3, [G4P_SLU]>]>,
|
||||
InstrItinData<IIC_LdStSTVEBX , [InstrStage<3, [G4P_SLU]>]>,
|
||||
InstrItinData<IIC_LdStSTWCX , [InstrStage<3, [G4P_SLU]>]>,
|
||||
InstrItinData<IIC_LdStSync , [InstrStage<35, [G4P_SLU]>]>,
|
||||
|
||||
@ -52,6 +52,7 @@ def G5Itineraries : ProcessorItineraries<
|
||||
InstrItinData<IIC_LdStDCBF , [InstrStage<3, [G5_SLU]>]>,
|
||||
InstrItinData<IIC_LdStLoad , [InstrStage<3, [G5_SLU]>]>,
|
||||
InstrItinData<IIC_LdStLoadUpd , [InstrStage<3, [G5_SLU]>]>,
|
||||
InstrItinData<IIC_LdStLoadUpdX, [InstrStage<3, [G5_SLU]>]>,
|
||||
InstrItinData<IIC_LdStStore , [InstrStage<3, [G5_SLU]>]>,
|
||||
InstrItinData<IIC_LdStStoreUpd, [InstrStage<3, [G5_SLU]>]>,
|
||||
InstrItinData<IIC_LdStDSS , [InstrStage<10, [G5_SLU]>]>,
|
||||
@ -60,11 +61,14 @@ def G5Itineraries : ProcessorItineraries<
|
||||
InstrItinData<IIC_LdStSTFDU , [InstrStage<4, [G5_SLU]>]>,
|
||||
InstrItinData<IIC_LdStLD , [InstrStage<3, [G5_SLU]>]>,
|
||||
InstrItinData<IIC_LdStLDU , [InstrStage<3, [G5_SLU]>]>,
|
||||
InstrItinData<IIC_LdStLDUX , [InstrStage<3, [G5_SLU]>]>,
|
||||
InstrItinData<IIC_LdStLDARX , [InstrStage<11, [G5_SLU]>]>,
|
||||
InstrItinData<IIC_LdStLFD , [InstrStage<3, [G5_SLU]>]>,
|
||||
InstrItinData<IIC_LdStLFDU , [InstrStage<5, [G5_SLU]>]>,
|
||||
InstrItinData<IIC_LdStLFDUX , [InstrStage<5, [G5_SLU]>]>,
|
||||
InstrItinData<IIC_LdStLHA , [InstrStage<5, [G5_SLU]>]>,
|
||||
InstrItinData<IIC_LdStLHAU , [InstrStage<5, [G5_SLU]>]>,
|
||||
InstrItinData<IIC_LdStLHAUX , [InstrStage<5, [G5_SLU]>]>,
|
||||
InstrItinData<IIC_LdStLMW , [InstrStage<64, [G5_SLU]>]>,
|
||||
InstrItinData<IIC_LdStLVecX , [InstrStage<3, [G5_SLU]>]>,
|
||||
InstrItinData<IIC_LdStLWA , [InstrStage<5, [G5_SLU]>]>,
|
||||
@ -73,6 +77,7 @@ def G5Itineraries : ProcessorItineraries<
|
||||
InstrItinData<IIC_LdStSLBIE , [InstrStage<2, [G5_SLU]>]>,
|
||||
InstrItinData<IIC_LdStSTD , [InstrStage<3, [G5_SLU]>]>,
|
||||
InstrItinData<IIC_LdStSTDU , [InstrStage<3, [G5_SLU]>]>,
|
||||
InstrItinData<IIC_LdStSTDUX , [InstrStage<3, [G5_SLU]>]>,
|
||||
InstrItinData<IIC_LdStSTDCX , [InstrStage<11, [G5_SLU]>]>,
|
||||
InstrItinData<IIC_LdStSTVEBX , [InstrStage<5, [G5_SLU]>]>,
|
||||
InstrItinData<IIC_LdStSTWCX , [InstrStage<11, [G5_SLU]>]>,
|
||||
@ -83,6 +88,7 @@ def G5Itineraries : ProcessorItineraries<
|
||||
InstrItinData<IIC_SprMTSR , [InstrStage<3, [G5_SLU]>]>,
|
||||
InstrItinData<IIC_SprTLBSYNC , [InstrStage<3, [G5_SLU]>]>,
|
||||
InstrItinData<IIC_SprMFCR , [InstrStage<2, [G5_IU2]>]>,
|
||||
InstrItinData<IIC_SprMFCRF , [InstrStage<2, [G5_IU2]>]>,
|
||||
InstrItinData<IIC_SprMFMSR , [InstrStage<3, [G5_IU2]>]>,
|
||||
InstrItinData<IIC_SprMFSPR , [InstrStage<3, [G5_IU2]>]>,
|
||||
InstrItinData<IIC_SprMFTB , [InstrStage<10, [G5_IU2]>]>,
|
||||
@ -95,7 +101,8 @@ def G5Itineraries : ProcessorItineraries<
|
||||
InstrItinData<IIC_FPDivS , [InstrStage<33, [G5_FPU1, G5_FPU2]>]>,
|
||||
InstrItinData<IIC_FPFused , [InstrStage<6, [G5_FPU1, G5_FPU2]>]>,
|
||||
InstrItinData<IIC_FPRes , [InstrStage<6, [G5_FPU1, G5_FPU2]>]>,
|
||||
InstrItinData<IIC_FPSqrt , [InstrStage<40, [G5_FPU1, G5_FPU2]>]>,
|
||||
InstrItinData<IIC_FPSqrtD , [InstrStage<40, [G5_FPU1, G5_FPU2]>]>,
|
||||
InstrItinData<IIC_FPSqrtS , [InstrStage<40, [G5_FPU1, G5_FPU2]>]>,
|
||||
InstrItinData<IIC_VecGeneral , [InstrStage<2, [G5_VIU1]>]>,
|
||||
InstrItinData<IIC_VecFP , [InstrStage<8, [G5_VFPU]>]>,
|
||||
InstrItinData<IIC_VecFPCompare, [InstrStage<2, [G5_VFPU]>]>,
|
||||
|
||||
Loading…
Reference in New Issue
Block a user