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[Hexagon] Adding skeleton of HVX extension instructions.

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llvm-svn: 250600
This commit is contained in:
Colin LeMahieu 2015-10-17 01:33:04 +00:00
parent 3b9509b65c
commit fa53018d3f
18 changed files with 4260 additions and 15 deletions
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75
lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
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@ -58,6 +58,18 @@ public:
static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeVectorRegsRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeVecDblRegsRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeVecPredRegsRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
@ -95,6 +107,10 @@ static DecodeStatus s4_2ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus s4_3ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, static DecodeStatus s4_3ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus s4_6ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
const void *Decoder);
static DecodeStatus s3_6ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
const void *Decoder);
static const uint16_t IntRegDecoderTable[] = { static const uint16_t IntRegDecoderTable[] = {
Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4, Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4,
@ -383,6 +399,51 @@ DecodeStatus HexagonDisassembler::getSingleInstruction(
return Result; return Result;
} }
static DecodeStatus DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address,
const void *Decoder) {
return DecodeIntRegsRegisterClass(Inst, RegNo, Address, Decoder);
}
static DecodeStatus DecodeVectorRegsRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t /*Address*/,
const void *Decoder) {
static const uint16_t VecRegDecoderTable[] = {
Hexagon::V0, Hexagon::V1, Hexagon::V2, Hexagon::V3, Hexagon::V4,
Hexagon::V5, Hexagon::V6, Hexagon::V7, Hexagon::V8, Hexagon::V9,
Hexagon::V10, Hexagon::V11, Hexagon::V12, Hexagon::V13, Hexagon::V14,
Hexagon::V15, Hexagon::V16, Hexagon::V17, Hexagon::V18, Hexagon::V19,
Hexagon::V20, Hexagon::V21, Hexagon::V22, Hexagon::V23, Hexagon::V24,
Hexagon::V25, Hexagon::V26, Hexagon::V27, Hexagon::V28, Hexagon::V29,
Hexagon::V30, Hexagon::V31};
return (DecodeRegisterClass(Inst, RegNo, VecRegDecoderTable,
sizeof(VecRegDecoderTable)));
}
static DecodeStatus DecodeVecDblRegsRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t /*Address*/,
const void *Decoder) {
static const uint16_t VecDblRegDecoderTable[] = {
Hexagon::W0, Hexagon::W1, Hexagon::W2, Hexagon::W3,
Hexagon::W4, Hexagon::W5, Hexagon::W6, Hexagon::W7,
Hexagon::W8, Hexagon::W9, Hexagon::W10, Hexagon::W11,
Hexagon::W12, Hexagon::W13, Hexagon::W14, Hexagon::W15};
return (DecodeRegisterClass(Inst, RegNo >> 1, VecDblRegDecoderTable,
sizeof(VecDblRegDecoderTable)));
}
static DecodeStatus DecodeVecPredRegsRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t /*Address*/,
const void *Decoder) {
static const uint16_t VecPredRegDecoderTable[] = {Hexagon::Q0, Hexagon::Q1,
Hexagon::Q2, Hexagon::Q3};
return (DecodeRegisterClass(Inst, RegNo, VecPredRegDecoderTable,
sizeof(VecPredRegDecoderTable)));
}
static DecodeStatus s16ImmDecoder(MCInst &MI, unsigned tmp, static DecodeStatus s16ImmDecoder(MCInst &MI, unsigned tmp,
uint64_t /*Address*/, const void *Decoder) { uint64_t /*Address*/, const void *Decoder) {
@ -475,6 +536,20 @@ static DecodeStatus s4_3ImmDecoder(MCInst &MI, unsigned tmp,
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus s4_6ImmDecoder(MCInst &MI, unsigned tmp,
uint64_t /*Address*/, const void *Decoder) {
uint64_t imm = SignExtend64<10>(tmp);
MI.addOperand(MCOperand::createImm(imm));
return MCDisassembler::Success;
}
static DecodeStatus s3_6ImmDecoder(MCInst &MI, unsigned tmp,
uint64_t /*Address*/, const void *Decoder) {
uint64_t imm = SignExtend64<9>(tmp);
MI.addOperand(MCOperand::createImm(imm));
return MCDisassembler::Success;
}
// These values are from HexagonGenMCCodeEmitter.inc and HexagonIsetDx.td // These values are from HexagonGenMCCodeEmitter.inc and HexagonIsetDx.td
enum subInstBinaryValues { enum subInstBinaryValues {
V4_SA1_addi_BITS = 0x0000, V4_SA1_addi_BITS = 0x0000,

25
lib/Target/Hexagon/Hexagon.td
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@ -24,14 +24,29 @@ include "llvm/Target/Target.td"
// Hexagon Architectures // Hexagon Architectures
def ArchV4: SubtargetFeature<"v4", "HexagonArchVersion", "V4", "Hexagon V4">; def ArchV4: SubtargetFeature<"v4", "HexagonArchVersion", "V4", "Hexagon V4">;
def ArchV5: SubtargetFeature<"v5", "HexagonArchVersion", "V5", "Hexagon V5">; def ArchV5: SubtargetFeature<"v5", "HexagonArchVersion", "V5", "Hexagon V5">;
def ArchV55: SubtargetFeature<"v55", "HexagonArchVersion", "V55", "Hexagon V55">;
def ArchV60: SubtargetFeature<"v60", "HexagonArchVersion", "V60", "Hexagon V60">;
// Hexagon ISA Extensions
def ExtensionHVX: SubtargetFeature<"hvx", "UseHVXOps",
"true", "Hexagon HVX instructions">;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Hexagon Instruction Predicate Definitions. // Hexagon Instruction Predicate Definitions.
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
def HasV5T : Predicate<"HST->hasV5TOps()">; def HasV5T : Predicate<"HST->hasV5TOps()">;
def NoV5T : Predicate<"!HST->hasV5TOps()">; def NoV5T : Predicate<"!HST->hasV5TOps()">;
def HasV55T : Predicate<"HST->hasV55TOps()">,
AssemblerPredicate<"ArchV55">;
def HasV60T : Predicate<"HST->hasV60TOps()">,
AssemblerPredicate<"ArchV60">;
def UseMEMOP : Predicate<"HST->useMemOps()">; def UseMEMOP : Predicate<"HST->useMemOps()">;
def IEEERndNearV5T : Predicate<"HST->modeIEEERndNear()">; def IEEERndNearV5T : Predicate<"HST->modeIEEERndNear()">;
def UseHVXDbl : Predicate<"HST->useHVXDblOps()">,
AssemblerPredicate<"ExtensionHVXDbl">;
def UseHVXSgl : Predicate<"HST->useHVXSglOps()">;
def UseHVX : Predicate<"HST->useHVXOps()">,
AssemblerPredicate<"ExtensionHVX">;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Classes used for relation maps. // Classes used for relation maps.
@ -62,7 +77,7 @@ class AddrModeRel: NewValueRel;
def getPredOpcode : InstrMapping { def getPredOpcode : InstrMapping {
let FilterClass = "PredRel"; let FilterClass = "PredRel";
// Instructions with the same BaseOpcode and isNVStore values form a row. // Instructions with the same BaseOpcode and isNVStore values form a row.
let RowFields = ["BaseOpcode", "isNVStore", "PNewValue"]; let RowFields = ["BaseOpcode", "isNVStore", "PNewValue", "isNT"];
// Instructions with the same predicate sense form a column. // Instructions with the same predicate sense form a column.
let ColFields = ["PredSense"]; let ColFields = ["PredSense"];
// The key column is the unpredicated instructions. // The key column is the unpredicated instructions.
@ -77,7 +92,7 @@ def getPredOpcode : InstrMapping {
// //
def getFalsePredOpcode : InstrMapping { def getFalsePredOpcode : InstrMapping {
let FilterClass = "PredRel"; let FilterClass = "PredRel";
let RowFields = ["BaseOpcode", "PNewValue", "isNVStore", "isBrTaken"]; let RowFields = ["BaseOpcode", "PNewValue", "isNVStore", "isBrTaken", "isNT"];
let ColFields = ["PredSense"]; let ColFields = ["PredSense"];
let KeyCol = ["true"]; let KeyCol = ["true"];
let ValueCols = [["false"]]; let ValueCols = [["false"]];
@ -89,7 +104,7 @@ def getFalsePredOpcode : InstrMapping {
// //
def getTruePredOpcode : InstrMapping { def getTruePredOpcode : InstrMapping {
let FilterClass = "PredRel"; let FilterClass = "PredRel";
let RowFields = ["BaseOpcode", "PNewValue", "isNVStore", "isBrTaken"]; let RowFields = ["BaseOpcode", "PNewValue", "isNVStore", "isBrTaken", "isNT"];
let ColFields = ["PredSense"]; let ColFields = ["PredSense"];
let KeyCol = ["false"]; let KeyCol = ["false"];
let ValueCols = [["true"]]; let ValueCols = [["true"]];
@ -125,7 +140,7 @@ def getPredOldOpcode : InstrMapping {
// //
def getNewValueOpcode : InstrMapping { def getNewValueOpcode : InstrMapping {
let FilterClass = "NewValueRel"; let FilterClass = "NewValueRel";
let RowFields = ["BaseOpcode", "PredSense", "PNewValue", "addrMode"]; let RowFields = ["BaseOpcode", "PredSense", "PNewValue", "addrMode", "isNT"];
let ColFields = ["NValueST"]; let ColFields = ["NValueST"];
let KeyCol = ["false"]; let KeyCol = ["false"];
let ValueCols = [["true"]]; let ValueCols = [["true"]];
@ -137,7 +152,7 @@ def getNewValueOpcode : InstrMapping {
// //
def getNonNVStore : InstrMapping { def getNonNVStore : InstrMapping {
let FilterClass = "NewValueRel"; let FilterClass = "NewValueRel";
let RowFields = ["BaseOpcode", "PredSense", "PNewValue", "addrMode"]; let RowFields = ["BaseOpcode", "PredSense", "PNewValue", "addrMode", "isNT"];
let ColFields = ["NValueST"]; let ColFields = ["NValueST"];
let KeyCol = ["true"]; let KeyCol = ["true"];
let ValueCols = [["false"]]; let ValueCols = [["false"]];

1019
lib/Target/Hexagon/HexagonInstrEnc.td Normal file
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File diff suppressed because it is too large Load Diff

45
lib/Target/Hexagon/HexagonInstrFormats.td
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@ -34,6 +34,8 @@ class SubTarget<bits<6> value> {
def HasAnySubT : SubTarget<0x3f>; // 111111 def HasAnySubT : SubTarget<0x3f>; // 111111
def HasV5SubT : SubTarget<0x3e>; // 111110 def HasV5SubT : SubTarget<0x3e>; // 111110
def HasV55SubT : SubTarget<0x3c>; // 111100
def HasV60SubT : SubTarget<0x38>; // 111000
// Addressing modes for load/store instructions // Addressing modes for load/store instructions
class AddrModeType<bits<3> value> { class AddrModeType<bits<3> value> {
@ -57,6 +59,8 @@ def ByteAccess : MemAccessSize<1>;// Byte access instruction (memb).
def HalfWordAccess : MemAccessSize<2>;// Half word access instruction (memh). def HalfWordAccess : MemAccessSize<2>;// Half word access instruction (memh).
def WordAccess : MemAccessSize<3>;// Word access instruction (memw). def WordAccess : MemAccessSize<3>;// Word access instruction (memw).
def DoubleWordAccess : MemAccessSize<4>;// Double word access instruction (memd) def DoubleWordAccess : MemAccessSize<4>;// Double word access instruction (memd)
def Vector64Access : MemAccessSize<7>;// Vector access instruction (memv)
def Vector128Access : MemAccessSize<8>;// Vector access instruction (memv)
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
@ -167,7 +171,17 @@ class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern,
bits<1> isFP = 0; bits<1> isFP = 0;
let TSFlags {48} = isFP; // Floating-point. let TSFlags {48} = isFP; // Floating-point.
bits<1> hasNewValue2 = 0;
let TSFlags{50} = hasNewValue2; // Second New-value producer insn.
bits<3> opNewValue2 = 0;
let TSFlags{53-51} = opNewValue2; // Second New-value produced operand.
bits<1> isAccumulator = 0;
let TSFlags{54} = isAccumulator;
// Fields used for relation models. // Fields used for relation models.
bit isNonTemporal = 0;
string isNT = ""; // set to "true" for non-temporal vector stores.
string BaseOpcode = ""; string BaseOpcode = "";
string CextOpcode = ""; string CextOpcode = "";
string PredSense = ""; string PredSense = "";
@ -182,6 +196,7 @@ class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern,
""); "");
let PNewValue = !if(isPredicatedNew, "new", ""); let PNewValue = !if(isPredicatedNew, "new", "");
let NValueST = !if(isNVStore, "true", "false"); let NValueST = !if(isNVStore, "true", "false");
let isNT = !if(isNonTemporal, "true", "false");
// *** Must match MCTargetDesc/HexagonBaseInfo.h *** // *** Must match MCTargetDesc/HexagonBaseInfo.h ***
} }
@ -217,6 +232,11 @@ class LD0Inst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
string cstr = "", InstrItinClass itin=LD_tc_ld_SLOT0> string cstr = "", InstrItinClass itin=LD_tc_ld_SLOT0>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeLD>, OpcodeHexagon; : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeLD>, OpcodeHexagon;
let mayLoad = 1 in
class LD1Inst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
string cstr = "", InstrItinClass itin=LD_tc_ld_SLOT0>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeLD>;
// ST Instruction Class in V2/V3 can take SLOT0 only. // ST Instruction Class in V2/V3 can take SLOT0 only.
// ST Instruction Class in V4 can take SLOT0 & SLOT1. // ST Instruction Class in V4 can take SLOT0 & SLOT1.
// Definition of the instruction class CHANGED from V2/V3 to V4. // Definition of the instruction class CHANGED from V2/V3 to V4.
@ -234,6 +254,12 @@ class ST0Inst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
string cstr = "", InstrItinClass itin = ST_tc_ld_SLOT0> string cstr = "", InstrItinClass itin = ST_tc_ld_SLOT0>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeST>, OpcodeHexagon; : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeST>, OpcodeHexagon;
// Same as ST0Inst but doesn't derive from OpcodeHexagon.
let mayStore = 1 in
class ST1Inst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
string cstr = "", InstrItinClass itin = ST_tc_st_SLOT0>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeST>;
// ST Instruction Class in V2/V3 can take SLOT0 only. // ST Instruction Class in V2/V3 can take SLOT0 only.
// ST Instruction Class in V4 can take SLOT0 & SLOT1. // ST Instruction Class in V4 can take SLOT0 & SLOT1.
// Definition of the instruction class CHANGED from V2/V3 to V4. // Definition of the instruction class CHANGED from V2/V3 to V4.
@ -277,6 +303,11 @@ class MInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeXTYPE>, : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeXTYPE>,
OpcodeHexagon; OpcodeHexagon;
// Same as above but doesn't derive from OpcodeHexagon
class MInst2<dag outs, dag ins, string asmstr, list<dag> pattern = [],
string cstr = "", InstrItinClass itin = M_tc_3x_SLOT23>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeXTYPE>;
// M Instruction Class in V2/V3. // M Instruction Class in V2/V3.
// XTYPE Instruction Class in V4. // XTYPE Instruction Class in V4.
// Definition of the instruction class NOT CHANGED. // Definition of the instruction class NOT CHANGED.
@ -294,6 +325,10 @@ class SInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeXTYPE>, : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeXTYPE>,
OpcodeHexagon; OpcodeHexagon;
class SInst2<dag outs, dag ins, string asmstr, list<dag> pattern = [],
string cstr = "", InstrItinClass itin = S_2op_tc_1_SLOT23>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeXTYPE>;
// S Instruction Class in V2/V3. // S Instruction Class in V2/V3.
// XTYPE Instruction Class in V4. // XTYPE Instruction Class in V4.
// Definition of the instruction class NOT CHANGED. // Definition of the instruction class NOT CHANGED.
@ -402,3 +437,13 @@ include "HexagonInstrFormatsV4.td"
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// V4 Instruction Format Definitions + // V4 Instruction Format Definitions +
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
// V60 Instruction Format Definitions +
//===----------------------------------------------------------------------===//
include "HexagonInstrFormatsV60.td"
//===----------------------------------------------------------------------===//
// V60 Instruction Format Definitions +
//===----------------------------------------------------------------------===//

238
lib/Target/Hexagon/HexagonInstrFormatsV60.td Normal file
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@ -0,0 +1,238 @@
//==- HexagonInstrFormatsV60.td - Hexagon Instruction Formats -*- tablegen -==//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file describes the Hexagon V60 instruction classes in TableGen format.
//
//===----------------------------------------------------------------------===//
//----------------------------------------------------------------------------//
// Hexagon Intruction Flags +
//
// *** Must match BaseInfo.h ***
//----------------------------------------------------------------------------//
def TypeCVI_VA : IType<13>;
def TypeCVI_VA_DV : IType<14>;
def TypeCVI_VX : IType<15>;
def TypeCVI_VX_DV : IType<16>;
def TypeCVI_VP : IType<17>;
def TypeCVI_VP_VS : IType<18>;
def TypeCVI_VS : IType<19>;
def TypeCVI_VINLANESAT : IType<20>;
def TypeCVI_VM_LD : IType<21>;
def TypeCVI_VM_TMP_LD : IType<22>;
def TypeCVI_VM_CUR_LD : IType<23>;
def TypeCVI_VM_VP_LDU : IType<24>;
def TypeCVI_VM_ST : IType<25>;
def TypeCVI_VM_NEW_ST : IType<26>;
def TypeCVI_VM_STU : IType<27>;
def TypeCVI_HIST : IType<28>;
//----------------------------------------------------------------------------//
// Intruction Classes Definitions +
//----------------------------------------------------------------------------//
let validSubTargets = HasV60SubT in
{
class CVI_VA_Resource<dag outs, dag ins, string asmstr,
list<dag> pattern = [], string cstr = "",
InstrItinClass itin = PSEUDO>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VA>,
OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
class CVI_VA_DV_Resource<dag outs, dag ins, string asmstr,
list<dag> pattern = [], string cstr = "",
InstrItinClass itin = PSEUDO>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VA_DV>,
OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
class CVI_VX_Resource_long<dag outs, dag ins, string asmstr,
list<dag> pattern = [], string cstr = "",
InstrItinClass itin = PSEUDO>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VX>,
OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
class CVI_VX_Resource_late<dag outs, dag ins, string asmstr,
list<dag> pattern = [], string cstr = "",
InstrItinClass itin = PSEUDO>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VX>,
Requires<[HasV60T, UseHVX]>;
class CVI_VX_Resource<dag outs, dag ins, string asmstr,
list<dag> pattern = [], string cstr = "",
InstrItinClass itin = PSEUDO>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VX>,
OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
class CVI_VX_DV_Resource<dag outs, dag ins, string asmstr,
list<dag> pattern = [], string cstr = "",
InstrItinClass itin = PSEUDO>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VX_DV>,
OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
class CVI_VX_DV_Slot2_Resource<dag outs, dag ins, string asmstr,
list<dag> pattern = [], string cstr = "",
InstrItinClass itin = PSEUDO>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VX_DV>,
OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
class CVI_VX_DV_Resource_long<dag outs, dag ins, string asmstr,
list<dag> pattern = [], string cstr = "",
InstrItinClass itin = PSEUDO>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VX_DV>,
OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
class CVI_VP_Resource_long<dag outs, dag ins, string asmstr,
list<dag> pattern = [], string cstr = "",
InstrItinClass itin = PSEUDO>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VP>,
OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
class CVI_VP_VS_Resource_early<dag outs, dag ins, string asmstr,
list<dag> pattern = [], string cstr = "",
InstrItinClass itin = PSEUDO>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VP_VS>,
OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
class CVI_VP_VS_Resource_long<dag outs, dag ins, string asmstr,
list<dag> pattern = [], string cstr = "",
InstrItinClass itin = PSEUDO>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VP_VS>,
OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
class CVI_VP_VS_Resource_long_early<dag outs, dag ins, string asmstr,
list<dag> pattern = [], string cstr = "",
InstrItinClass itin = PSEUDO>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VP_VS>,
OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
class CVI_VS_Resource<dag outs, dag ins, string asmstr,
list<dag> pattern = [], string cstr = "",
InstrItinClass itin = PSEUDO>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VS>,
OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
class CVI_VINLANESAT_Resource<dag outs, dag ins, string asmstr,
list<dag> pattern = [], string cstr = "",
InstrItinClass itin = PSEUDO>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VINLANESAT>,
OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
class CVI_VS_Resource_long<dag outs, dag ins, string asmstr,
list<dag> pattern = [], string cstr = "",
InstrItinClass itin = PSEUDO>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VS>,
OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
class CVI_VM_LD_Resource<dag outs, dag ins, string asmstr,
list<dag> pattern = [], string cstr = "",
InstrItinClass itin = PSEUDO>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VM_LD>,
OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
class CVI_VM_LD_Resource_long<dag outs, dag ins, string asmstr,
list<dag> pattern = [], string cstr = "",
InstrItinClass itin = PSEUDO>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VM_LD>,
OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
class CVI_VM_TMP_LD_Resource<dag outs, dag ins, string asmstr,
list<dag> pattern = [], string cstr = "",
InstrItinClass itin = PSEUDO>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VM_TMP_LD>,
OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
class CVI_VM_TMP_LD_Resource_long<dag outs, dag ins, string asmstr,
list<dag> pattern = [], string cstr = "",
InstrItinClass itin = PSEUDO>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VM_TMP_LD>,
OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
class CVI_VM_CUR_LD_Resource<dag outs, dag ins, string asmstr,
list<dag> pattern = [], string cstr = "",
InstrItinClass itin = PSEUDO>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VM_CUR_LD>,
OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
class CVI_VM_VP_LDU_Resource<dag outs, dag ins, string asmstr,
list<dag> pattern = [], string cstr = "",
InstrItinClass itin = PSEUDO>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VM_VP_LDU>,
OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
class CVI_VM_VP_LDU_Resource_long<dag outs, dag ins, string asmstr,
list<dag> pattern = [], string cstr = "",
InstrItinClass itin = PSEUDO>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VM_VP_LDU>,
OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
class CVI_VM_ST_Resource<dag outs, dag ins, string asmstr,
list<dag> pattern = [], string cstr = "",
InstrItinClass itin = PSEUDO>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VM_ST>,
OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
class CVI_VM_ST_Resource_long<dag outs, dag ins, string asmstr,
list<dag> pattern = [], string cstr = "",
InstrItinClass itin = PSEUDO>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VM_ST>,
OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
class CVI_VM_NEW_ST_Resource<dag outs, dag ins, string asmstr,
list<dag> pattern = [], string cstr = "",
InstrItinClass itin = PSEUDO>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VM_NEW_ST>,
OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
class CVI_VM_NEW_ST_Resource_long<dag outs, dag ins, string asmstr,
list<dag> pattern = [], string cstr = "",
InstrItinClass itin = PSEUDO>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VM_NEW_ST>,
OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
class CVI_VM_STU_Resource<dag outs, dag ins, string asmstr,
list<dag> pattern = [], string cstr = "",
InstrItinClass itin = PSEUDO>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VM_STU>,
OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
class CVI_VM_STU_Resource_long<dag outs, dag ins, string asmstr,
list<dag> pattern = [], string cstr = "",
InstrItinClass itin = PSEUDO>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VM_STU>,
OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
class CVI_HIST_Resource<dag outs, dag ins, string asmstr,
list<dag> pattern = [], string cstr = "",
InstrItinClass itin = PSEUDO>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_HIST>,
OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
}
let validSubTargets = HasV60SubT in
{
class CVI_VA_Resource1<dag outs, dag ins, string asmstr,
list<dag> pattern = [], string cstr = "",
InstrItinClass itin = PSEUDO>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VA>,
Requires<[HasV60T, UseHVX]>;
class CVI_VX_DV_Resource1<dag outs, dag ins, string asmstr,
list<dag> pattern = [], string cstr = "",
InstrItinClass itin = PSEUDO>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VX_DV>,
Requires<[HasV60T, UseHVX]>;
class CVI_HIST_Resource1<dag outs, dag ins, string asmstr,
list<dag> pattern = [], string cstr = "",
InstrItinClass itin = PSEUDO>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_HIST>,
Requires<[HasV60T, UseHVX]>;
}

12
lib/Target/Hexagon/HexagonInstrInfo.td
View File

@ -13,7 +13,7 @@
include "HexagonInstrFormats.td" include "HexagonInstrFormats.td"
include "HexagonOperands.td" include "HexagonOperands.td"
include "HexagonInstrEnc.td"
// Pattern fragment that combines the value type and the register class // Pattern fragment that combines the value type and the register class
// into a single parameter. // into a single parameter.
// The pat frags in the definitions below need to have a named register, // The pat frags in the definitions below need to have a named register,
@ -5783,6 +5783,16 @@ include "HexagonInstrInfoV5.td"
// V5 Instructions - // V5 Instructions -
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
// V60 Instructions +
//===----------------------------------------------------------------------===//
include "HexagonInstrInfoV60.td"
//===----------------------------------------------------------------------===//
// V60 Instructions -
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// ALU32/64/Vector + // ALU32/64/Vector +
//===----------------------------------------------------------------------===/// //===----------------------------------------------------------------------===///

2211
lib/Target/Hexagon/HexagonInstrInfoV60.td Normal file
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File diff suppressed because it is too large Load Diff

52
lib/Target/Hexagon/HexagonOperands.td
View File

@ -11,6 +11,8 @@ def s4_0ImmOperand : AsmOperandClass { let Name = "s4_0Imm"; }
def s4_1ImmOperand : AsmOperandClass { let Name = "s4_1Imm"; } def s4_1ImmOperand : AsmOperandClass { let Name = "s4_1Imm"; }
def s4_2ImmOperand : AsmOperandClass { let Name = "s4_2Imm"; } def s4_2ImmOperand : AsmOperandClass { let Name = "s4_2Imm"; }
def s4_3ImmOperand : AsmOperandClass { let Name = "s4_3Imm"; } def s4_3ImmOperand : AsmOperandClass { let Name = "s4_3Imm"; }
def s4_6ImmOperand : AsmOperandClass { let Name = "s4_6Imm"; }
def s3_6ImmOperand : AsmOperandClass { let Name = "s3_6Imm"; }
// Immediate operands. // Immediate operands.
@ -58,6 +60,19 @@ let PrintMethod = "printImmOperand" in {
def m6Imm : Operand<i32>; def m6Imm : Operand<i32>;
} }
let OperandType = "OPERAND_IMMEDIATE" in {
def s4_6Imm : Operand<i32> { let ParserMatchClass = s4_6ImmOperand;
let PrintMethod = "prints4_6ImmOperand";
let DecoderMethod = "s4_6ImmDecoder";}
def s4_7Imm : Operand<i32> { let PrintMethod = "prints4_7ImmOperand";
let DecoderMethod = "s4_6ImmDecoder";}
def s3_6Imm : Operand<i32> { let ParserMatchClass = s3_6ImmOperand;
let PrintMethod = "prints3_6ImmOperand";
let DecoderMethod = "s3_6ImmDecoder";}
def s3_7Imm : Operand<i32> { let PrintMethod = "prints3_7ImmOperand";
let DecoderMethod = "s3_6ImmDecoder";}
}
let PrintMethod = "printNOneImmOperand" in let PrintMethod = "printNOneImmOperand" in
def nOneImm : Operand<i32>; def nOneImm : Operand<i32>;
@ -502,6 +517,43 @@ def u9ExtPred : PatLeaf<(i32 imm), [{
}]>; }]>;
def s4_7ImmPred : PatLeaf<(i32 imm), [{
int64_t v = (int64_t)N->getSExtValue();
if (HST->hasV60TOps())
// Return true if the immediate can fit in a 10-bit sign extended field and
// is 128-byte aligned.
return isShiftedInt<4,7>(v);
return false;
}]>;
def s3_7ImmPred : PatLeaf<(i32 imm), [{
int64_t v = (int64_t)N->getSExtValue();
if (HST->hasV60TOps())
// Return true if the immediate can fit in a 9-bit sign extended field and
// is 128-byte aligned.
return isShiftedInt<3,7>(v);
return false;
}]>;
def s4_6ImmPred : PatLeaf<(i32 imm), [{
int64_t v = (int64_t)N->getSExtValue();
if (HST->hasV60TOps())
// Return true if the immediate can fit in a 10-bit sign extended field and
// is 64-byte aligned.
return isShiftedInt<4,6>(v);
return false;
}]>;
def s3_6ImmPred : PatLeaf<(i32 imm), [{
int64_t v = (int64_t)N->getSExtValue();
if (HST->hasV60TOps())
// Return true if the immediate can fit in a 9-bit sign extended field and
// is 64-byte aligned.
return isShiftedInt<3,6>(v);
return false;
}]>;
// This complex pattern exists only to create a machine instruction operand // This complex pattern exists only to create a machine instruction operand
// of type "frame index". There doesn't seem to be a way to do that directly // of type "frame index". There doesn't seem to be a way to do that directly
// in the patterns. // in the patterns.

4
lib/Target/Hexagon/HexagonRegisterInfo.cpp
View File

@ -66,6 +66,8 @@ HexagonRegisterInfo::getCallerSavedRegs(const MachineFunction *MF) const {
switch (HST.getHexagonArchVersion()) { switch (HST.getHexagonArchVersion()) {
case HexagonSubtarget::V4: case HexagonSubtarget::V4:
case HexagonSubtarget::V5: case HexagonSubtarget::V5:
case HexagonSubtarget::V55:
case HexagonSubtarget::V60:
return CallerSavedRegsV4; return CallerSavedRegsV4;
} }
llvm_unreachable( llvm_unreachable(
@ -84,6 +86,8 @@ HexagonRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
switch (MF->getSubtarget<HexagonSubtarget>().getHexagonArchVersion()) { switch (MF->getSubtarget<HexagonSubtarget>().getHexagonArchVersion()) {
case HexagonSubtarget::V4: case HexagonSubtarget::V4:
case HexagonSubtarget::V5: case HexagonSubtarget::V5:
case HexagonSubtarget::V55:
case HexagonSubtarget::V60:
return CalleeSavedRegsV3; return CalleeSavedRegsV3;
} }
llvm_unreachable("Callee saved registers requested for unknown architecture " llvm_unreachable("Callee saved registers requested for unknown architecture "

59
lib/Target/Hexagon/HexagonRegisterInfo.td
View File

@ -53,6 +53,12 @@ let Namespace = "Hexagon" in {
let Num = num; let Num = num;
} }
// Rq - vector predicate registers
class Rq<bits<3> num, string n> : Register<n, []> {
let HWEncoding{2-0} = num;
}
// Rc - control registers // Rc - control registers
class Rc<bits<5> num, string n, class Rc<bits<5> num, string n,
list<string> alt = [], list<Register> alias = []> : list<string> alt = [], list<Register> alias = []> :
@ -158,6 +164,36 @@ let Namespace = "Hexagon" in {
def UPC : Rcc<14, "c15:14", [UPCL, UPCH]>, DwarfRegNum<[80]>; def UPC : Rcc<14, "c15:14", [UPCL, UPCH]>, DwarfRegNum<[80]>;
} }
foreach i = 0-31 in {
def V#i : Ri<i, "v"#i>, DwarfRegNum<[!add(i, 99)]>;
}
// Aliases of the V* registers used to hold double vec values.
let SubRegIndices = [subreg_loreg, subreg_hireg], CoveredBySubRegs = 1 in {
def W0 : Rd< 0, "v1:0", [V0, V1]>, DwarfRegNum<[99]>;
def W1 : Rd< 2, "v3:2", [V2, V3]>, DwarfRegNum<[101]>;
def W2 : Rd< 4, "v5:4", [V4, V5]>, DwarfRegNum<[103]>;
def W3 : Rd< 6, "v7:6", [V6, V7]>, DwarfRegNum<[105]>;
def W4 : Rd< 8, "v9:8", [V8, V9]>, DwarfRegNum<[107]>;
def W5 : Rd<10, "v11:10", [V10, V11]>, DwarfRegNum<[109]>;
def W6 : Rd<12, "v13:12", [V12, V13]>, DwarfRegNum<[111]>;
def W7 : Rd<14, "v15:14", [V14, V15]>, DwarfRegNum<[113]>;
def W8 : Rd<16, "v17:16", [V16, V17]>, DwarfRegNum<[115]>;
def W9 : Rd<18, "v19:18", [V18, V19]>, DwarfRegNum<[117]>;
def W10 : Rd<20, "v21:20", [V20, V21]>, DwarfRegNum<[119]>;
def W11 : Rd<22, "v23:22", [V22, V23]>, DwarfRegNum<[121]>;
def W12 : Rd<24, "v25:24", [V24, V25]>, DwarfRegNum<[123]>;
def W13 : Rd<26, "v27:26", [V26, V27]>, DwarfRegNum<[125]>;
def W14 : Rd<28, "v29:28", [V28, V29]>, DwarfRegNum<[127]>;
def W15 : Rd<30, "v31:30", [V30, V31]>, DwarfRegNum<[129]>;
}
// Vector Predicate registers.
def Q0 : Rq<0, "q0">, DwarfRegNum<[131]>;
def Q1 : Rq<1, "q1">, DwarfRegNum<[132]>;
def Q2 : Rq<2, "q2">, DwarfRegNum<[133]>;
def Q3 : Rq<3, "q3">, DwarfRegNum<[134]>;
// Register classes. // Register classes.
// //
// FIXME: the register order should be defined in terms of the preferred // FIXME: the register order should be defined in terms of the preferred
@ -169,10 +205,33 @@ def IntRegs : RegisterClass<"Hexagon", [i32, f32, v4i8, v2i16], 32,
R10, R11, R29, R30, R31)> { R10, R11, R29, R30, R31)> {
} }
// Registers are listed in reverse order for allocation preference reasons.
def IntRegsLow8 : RegisterClass<"Hexagon", [i32], 32,
(add R7, R6, R5, R4, R3, R2, R1, R0)> ;
def DoubleRegs : RegisterClass<"Hexagon", [i64, f64, v8i8, v4i16, v2i32], 64, def DoubleRegs : RegisterClass<"Hexagon", [i64, f64, v8i8, v4i16, v2i32], 64,
(add (sequence "D%u", 0, 4), (add (sequence "D%u", 0, 4),
(sequence "D%u", 6, 13), D5, D14, D15)>; (sequence "D%u", 6, 13), D5, D14, D15)>;
def VectorRegs : RegisterClass<"Hexagon", [v64i8, v32i16, v16i32, v8i64], 512,
(add (sequence "V%u", 0, 31))>;
def VecDblRegs : RegisterClass<"Hexagon", [v16i64], 1024,
(add (sequence "W%u", 0, 15))>;
def VectorRegs128B : RegisterClass<"Hexagon",
[v16i64], 1024,
(add (sequence "V%u", 0, 31))>;
def VecDblRegs128B : RegisterClass<"Hexagon",
[v16i64], 2048,
(add (sequence "W%u", 0, 15))>;
def VecPredRegs : RegisterClass<"Hexagon", [v16i32], 512,
(add (sequence "Q%u", 0, 3))>;
def VecPredRegs128B : RegisterClass<"Hexagon", [v16i64], 1024,
(add (sequence "Q%u", 0, 3))>;
def PredRegs : RegisterClass<"Hexagon", def PredRegs : RegisterClass<"Hexagon",
[i1, v2i1, v4i1, v8i1, v4i8, v2i16, i32], 32, [i1, v2i1, v4i1, v8i1, v4i8, v2i16, i32], 32,

4
lib/Target/Hexagon/HexagonSchedule.td
View File

@ -13,6 +13,10 @@
include "HexagonScheduleV4.td" include "HexagonScheduleV4.td"
// V55 Machine Info +
include "HexagonScheduleV55.td"
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// V4 Machine Info - // V4 Machine Info -
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//

3
lib/Target/Hexagon/HexagonScheduleV4.td
View File

@ -39,6 +39,7 @@ def PSEUDOM : InstrItinClass;
// ALU64/M/S Instruction classes of V2 are collectively knownn as XTYPE in V4. // ALU64/M/S Instruction classes of V2 are collectively knownn as XTYPE in V4.
def DUPLEX : InstrItinClass; def DUPLEX : InstrItinClass;
def PREFIX : InstrItinClass; def PREFIX : InstrItinClass;
def COMPOUND_CJ_ARCHDEPSLOT : InstrItinClass;
def COMPOUND : InstrItinClass; def COMPOUND : InstrItinClass;
def ALU32_2op_tc_1_SLOT0123 : InstrItinClass; def ALU32_2op_tc_1_SLOT0123 : InstrItinClass;
@ -58,6 +59,7 @@ def CR_tc_2early_SLOT3 : InstrItinClass;
def CR_tc_3x_SLOT23 : InstrItinClass; def CR_tc_3x_SLOT23 : InstrItinClass;
def CR_tc_3x_SLOT3 : InstrItinClass; def CR_tc_3x_SLOT3 : InstrItinClass;
def J_tc_2early_SLOT23 : InstrItinClass; def J_tc_2early_SLOT23 : InstrItinClass;
def J_tc_2early_CJUMP_UCJUMP_ARCHDEPSLOT : InstrItinClass;
def J_tc_2early_SLOT2 : InstrItinClass; def J_tc_2early_SLOT2 : InstrItinClass;
def LD_tc_ld_SLOT01 : InstrItinClass; def LD_tc_ld_SLOT01 : InstrItinClass;
def LD_tc_ld_SLOT0 : InstrItinClass; def LD_tc_ld_SLOT0 : InstrItinClass;
@ -91,6 +93,7 @@ def V4LDST_tc_st_SLOT0 : InstrItinClass;
def V4LDST_tc_st_SLOT01 : InstrItinClass; def V4LDST_tc_st_SLOT01 : InstrItinClass;
def J_tc_2early_SLOT0123 : InstrItinClass; def J_tc_2early_SLOT0123 : InstrItinClass;
def EXTENDER_tc_1_SLOT0123 : InstrItinClass; def EXTENDER_tc_1_SLOT0123 : InstrItinClass;
def S_3op_tc_3stall_SLOT23 : InstrItinClass;
def HexagonItinerariesV4 : def HexagonItinerariesV4 :

170
lib/Target/Hexagon/HexagonScheduleV55.td Normal file
View File

@ -0,0 +1,170 @@
//=-HexagonScheduleV4.td - HexagonV4 Scheduling Definitions --*- tablegen -*-=//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
// There are four SLOTS (four parallel pipelines) in Hexagon V4 machine.
// This file describes that machine information.
//
// |===========|==================================================|
// | PIPELINE | Instruction Classes |
// |===========|==================================================|
// | SLOT0 | LD ST ALU32 MEMOP NV SYSTEM |
// |-----------|--------------------------------------------------|
// | SLOT1 | LD ST ALU32 |
// |-----------|--------------------------------------------------|
// | SLOT2 | XTYPE ALU32 J JR |
// |-----------|--------------------------------------------------|
// | SLOT3 | XTYPE ALU32 J CR |
// |===========|==================================================|
def CJ_tc_1_SLOT23 : InstrItinClass;
def CJ_tc_2early_SLOT23 : InstrItinClass;
def COPROC_VMEM_vtc_long_SLOT01 : InstrItinClass;
def COPROC_VX_vtc_long_SLOT23 : InstrItinClass;
def COPROC_VX_vtc_SLOT23 : InstrItinClass;
def J_tc_3stall_SLOT2 : InstrItinClass;
def MAPPING_tc_1_SLOT0123 : InstrItinClass;
def M_tc_3stall_SLOT23 : InstrItinClass;
def SUBINSN_tc_1_SLOT01 : InstrItinClass;
def SUBINSN_tc_2early_SLOT0 : InstrItinClass;
def SUBINSN_tc_2early_SLOT01 : InstrItinClass;
def SUBINSN_tc_3stall_SLOT0 : InstrItinClass;
def SUBINSN_tc_ld_SLOT0 : InstrItinClass;
def SUBINSN_tc_ld_SLOT01 : InstrItinClass;
def SUBINSN_tc_st_SLOT01 : InstrItinClass;
def HexagonItinerariesV55 :
ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP], [], [
// ALU32
InstrItinData<ALU32_2op_tc_1_SLOT0123 ,
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
InstrItinData<ALU32_2op_tc_2early_SLOT0123,
[InstrStage<2, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
InstrItinData<ALU32_3op_tc_1_SLOT0123 ,
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
InstrItinData<ALU32_3op_tc_2_SLOT0123 ,
[InstrStage<2, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
InstrItinData<ALU32_3op_tc_2early_SLOT0123,
[InstrStage<2, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
InstrItinData<ALU32_ADDI_tc_1_SLOT0123 ,
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
// ALU64
InstrItinData<ALU64_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
InstrItinData<ALU64_tc_2_SLOT23 , [InstrStage<2, [SLOT2, SLOT3]>]>,
InstrItinData<ALU64_tc_2early_SLOT23, [InstrStage<2, [SLOT2, SLOT3]>]>,
InstrItinData<ALU64_tc_3x_SLOT23 , [InstrStage<3, [SLOT2, SLOT3]>]>,
// CR -> System
InstrItinData<CR_tc_2_SLOT3 , [InstrStage<2, [SLOT3]>]>,
InstrItinData<CR_tc_2early_SLOT3 , [InstrStage<2, [SLOT3]>]>,
InstrItinData<CR_tc_3x_SLOT3 , [InstrStage<3, [SLOT3]>]>,
// Jump (conditional/unconditional/return etc)
InstrItinData<CR_tc_2early_SLOT23, [InstrStage<2, [SLOT2, SLOT3]>]>,
InstrItinData<CR_tc_3x_SLOT23 , [InstrStage<3, [SLOT2, SLOT3]>]>,
InstrItinData<CJ_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
InstrItinData<CJ_tc_2early_SLOT23, [InstrStage<2, [SLOT2, SLOT3]>]>,
InstrItinData<J_tc_2early_SLOT23 , [InstrStage<2, [SLOT2, SLOT3]>]>,
InstrItinData<J_tc_2early_CJUMP_UCJUMP_ARCHDEPSLOT , [InstrStage<1, [SLOT2, SLOT3]>]>,
// JR
InstrItinData<J_tc_2early_SLOT2 , [InstrStage<2, [SLOT2]>]>,
InstrItinData<J_tc_3stall_SLOT2 , [InstrStage<3, [SLOT2]>]>,
// Extender
InstrItinData<EXTENDER_tc_1_SLOT0123,
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
// Load
InstrItinData<LD_tc_ld_SLOT01 , [InstrStage<3, [SLOT0, SLOT1]>]>,
InstrItinData<LD_tc_3or4stall_SLOT0, [InstrStage<3, [SLOT0]>]>,
InstrItinData<LD_tc_ld_SLOT0 , [InstrStage<3, [SLOT0]>]>,
// M
InstrItinData<M_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
InstrItinData<M_tc_2_SLOT23 , [InstrStage<2, [SLOT2, SLOT3]>]>,
InstrItinData<M_tc_3_SLOT23 , [InstrStage<3, [SLOT2, SLOT3]>]>,
InstrItinData<M_tc_3x_SLOT23 , [InstrStage<3, [SLOT2, SLOT3]>]>,
InstrItinData<M_tc_3or4x_SLOT23 , [InstrStage<3, [SLOT2, SLOT3]>]>,
InstrItinData<M_tc_3stall_SLOT23, [InstrStage<3, [SLOT2, SLOT3]>]>,
// Store
InstrItinData<ST_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>,
InstrItinData<ST_tc_3stall_SLOT0, [InstrStage<3, [SLOT0]>]>,
InstrItinData<ST_tc_ld_SLOT0 , [InstrStage<3, [SLOT0]>]>,
InstrItinData<ST_tc_st_SLOT0 , [InstrStage<1, [SLOT0]>]>,
// Subinsn
InstrItinData<SUBINSN_tc_2early_SLOT0, [InstrStage<2, [SLOT0]>]>,
InstrItinData<SUBINSN_tc_3stall_SLOT0, [InstrStage<3, [SLOT0]>]>,
InstrItinData<SUBINSN_tc_ld_SLOT0 , [InstrStage<3, [SLOT0]>]>,
InstrItinData<SUBINSN_tc_1_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>,
InstrItinData<SUBINSN_tc_2early_SLOT01,
[InstrStage<2, [SLOT0, SLOT1]>]>,
InstrItinData<SUBINSN_tc_ld_SLOT01 , [InstrStage<3, [SLOT0, SLOT1]>]>,
InstrItinData<SUBINSN_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>,
// S
InstrItinData<S_2op_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
InstrItinData<S_2op_tc_2_SLOT23 , [InstrStage<2, [SLOT2, SLOT3]>]>,
InstrItinData<S_2op_tc_2early_SLOT23, [InstrStage<2, [SLOT2, SLOT3]>]>,
InstrItinData<S_2op_tc_3or4x_SLOT23 , [InstrStage<3, [SLOT2, SLOT3]>]>,
InstrItinData<S_3op_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
InstrItinData<S_3op_tc_2_SLOT23 , [InstrStage<2, [SLOT2, SLOT3]>]>,
InstrItinData<S_3op_tc_2early_SLOT23, [InstrStage<2, [SLOT2, SLOT3]>]>,
InstrItinData<S_3op_tc_3_SLOT23 , [InstrStage<3, [SLOT2, SLOT3]>]>,
InstrItinData<S_3op_tc_3stall_SLOT23, [InstrStage<3, [SLOT2, SLOT3]>]>,
InstrItinData<S_3op_tc_3x_SLOT23 , [InstrStage<3, [SLOT2, SLOT3]>]>,
// New Value Compare Jump
InstrItinData<NCJ_tc_3or4stall_SLOT0, [InstrStage<3, [SLOT0]>]>,
// Mem ops
InstrItinData<V2LDST_tc_st_SLOT0 , [InstrStage<1, [SLOT0]>]>,
InstrItinData<V2LDST_tc_ld_SLOT01 , [InstrStage<2, [SLOT0, SLOT1]>]>,
InstrItinData<V2LDST_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>,
InstrItinData<V4LDST_tc_st_SLOT0 , [InstrStage<1, [SLOT0]>]>,
InstrItinData<V4LDST_tc_ld_SLOT01 , [InstrStage<3, [SLOT0, SLOT1]>]>,
InstrItinData<V4LDST_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>,
// Endloop
InstrItinData<J_tc_2early_SLOT0123, [InstrStage<2, [SLOT_ENDLOOP]>]>,
// Vector
InstrItinData<COPROC_VMEM_vtc_long_SLOT01,
[InstrStage<3, [SLOT0, SLOT1]>]>,
InstrItinData<COPROC_VX_vtc_long_SLOT23 ,
[InstrStage<3, [SLOT2, SLOT3]>]>,
InstrItinData<COPROC_VX_vtc_SLOT23 ,
[InstrStage<3, [SLOT2, SLOT3]>]>,
InstrItinData<MAPPING_tc_1_SLOT0123 ,
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
// Misc
InstrItinData<COMPOUND_CJ_ARCHDEPSLOT , [InstrStage<1, [SLOT2, SLOT3]>]>,
InstrItinData<COMPOUND , [InstrStage<1, [SLOT2, SLOT3]>]>,
InstrItinData<DUPLEX , [InstrStage<1, [SLOT0]>]>,
InstrItinData<PREFIX , [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
InstrItinData<PSEUDO , [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
InstrItinData<PSEUDOM, [InstrStage<1, [SLOT2, SLOT3], 0>,
InstrStage<1, [SLOT2, SLOT3]>]>
]>;
def HexagonModelV55 : SchedMachineModel {
// Max issue per cycle == bundle width.
let IssueWidth = 4;
let Itineraries = HexagonItinerariesV55;
let LoadLatency = 1;
}
//===----------------------------------------------------------------------===//
// Hexagon V4 Resource Definitions -
//===----------------------------------------------------------------------===//

301
lib/Target/Hexagon/HexagonScheduleV60.td Normal file
View File

@ -0,0 +1,301 @@
//=-HexagonScheduleV60.td - HexagonV60 Scheduling Definitions *- tablegen -*-=//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
// CVI pipes from the "Hexagon Multimedia Co-Processor Extensions Arch Spec".
def CVI_ST : FuncUnit;
def CVI_XLANE : FuncUnit;
def CVI_SHIFT : FuncUnit;
def CVI_MPY0 : FuncUnit;
def CVI_MPY1 : FuncUnit;
def CVI_LD : FuncUnit;
// Combined functional units.
def CVI_XLSHF : FuncUnit;
def CVI_MPY01 : FuncUnit;
def CVI_ALL : FuncUnit;
// Note: When adding additional vector scheduling classes, add the
// corresponding methods to the class HexagonInstrInfo.
def CVI_VA : InstrItinClass;
def CVI_VA_DV : InstrItinClass;
def CVI_VX_LONG : InstrItinClass;
def CVI_VX_LATE : InstrItinClass;
def CVI_VX : InstrItinClass;
def CVI_VX_DV_LONG : InstrItinClass;
def CVI_VX_DV : InstrItinClass;
def CVI_VX_DV_SLOT2 : InstrItinClass;
def CVI_VP : InstrItinClass;
def CVI_VP_LONG : InstrItinClass;
def CVI_VP_VS_EARLY : InstrItinClass;
def CVI_VP_VS_LONG_EARLY : InstrItinClass;
def CVI_VP_VS_LONG : InstrItinClass;
def CVI_VP_VS : InstrItinClass;
def CVI_VP_DV : InstrItinClass;
def CVI_VS : InstrItinClass;
def CVI_VINLANESAT : InstrItinClass;
def CVI_VM_LD : InstrItinClass;
def CVI_VM_TMP_LD : InstrItinClass;
def CVI_VM_CUR_LD : InstrItinClass;
def CVI_VM_VP_LDU : InstrItinClass;
def CVI_VM_ST : InstrItinClass;
def CVI_VM_NEW_ST : InstrItinClass;
def CVI_VM_STU : InstrItinClass;
def CVI_HIST : InstrItinClass;
def CVI_VA_EXT : InstrItinClass;
// There are four SLOTS (four parallel pipelines) in Hexagon V60 machine.
// This file describes that machine information.
//
// |===========|==================================================|
// | PIPELINE | Instruction Classes |
// |===========|==================================================|
// | SLOT0 | LD ST ALU32 MEMOP NV SYSTEM |
// |-----------|--------------------------------------------------|
// | SLOT1 | LD ST ALU32 |
// |-----------|--------------------------------------------------|
// | SLOT2 | XTYPE ALU32 J JR |
// |-----------|--------------------------------------------------|
// | SLOT3 | XTYPE ALU32 J CR |
// |===========|==================================================|
//
//
// In addition to using the above SLOTS, there are also six vector pipelines
// in the CVI co-processor in the Hexagon V60 machine.
//
// |=========| |=========| |=========| |=========| |=========| |=========|
// SLOT | CVI_LD | |CVI_MPY3 | |CVI_MPY2 | |CVI_SHIFT| |CVI_XLANE| | CVI_ST |
// ==== |=========| |=========| |=========| |=========| |=========| |=========|
// S0-3 | | | CVI_VA | | CVI_VA | | CVI_VA | | CVI_VA | | |
// S2-3 | | | CVI_VX | | CVI_VX | | | | | | |
// S0-3 | | | | | | | | | CVI_VP | | |
// S0-3 | | | | | | | CVI_VS | | | | |
// S0-1 |(CVI_LD) | | CVI_LD | | CVI_LD | | CVI_LD | | CVI_LD | | |
// S0-1 |(C*TMP_LD) | | | | | | | | | |
// S01 |(C*_LDU) | | | | | | | | C*_LDU | | |
// S0 | | | CVI_ST | | CVI_ST | | CVI_ST | | CVI_ST | |(CVI_ST) |
// S0 | | | | | | | | | | |(C*TMP_ST)
// S01 | | | | | | | | | VSTU | |(C*_STU) |
// |=========| |=========| |=========| |=========| |=========| |=========|
// |=====================| |=====================|
// | CVI_MPY2 & CVI_MPY3 | |CVI_XLANE & CVI_SHIFT|
// |=====================| |=====================|
// S0-3 | CVI_VA_DV | | CVI_VA_DV |
// S0-3 | | | CVI_VP_DV |
// S2-3 | CVI_VX_DV | | |
// |=====================| |=====================|
// |=====================================================================|
// S0-3 | CVI_HIST Histogram |
// S0123| CVI_VA_EXT Extract |
// |=====================================================================|
def HexagonItinerariesV60 :
ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP,
CVI_ST, CVI_XLANE, CVI_SHIFT, CVI_MPY0, CVI_MPY1,
CVI_LD, CVI_XLSHF, CVI_MPY01, CVI_ALL], [], [
// ALU32
InstrItinData<ALU32_2op_tc_1_SLOT0123 ,
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
InstrItinData<ALU32_2op_tc_2early_SLOT0123,
[InstrStage<2, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
InstrItinData<ALU32_3op_tc_1_SLOT0123 ,
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
InstrItinData<ALU32_3op_tc_2_SLOT0123 ,
[InstrStage<2, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
InstrItinData<ALU32_3op_tc_2early_SLOT0123,
[InstrStage<2, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
InstrItinData<ALU32_ADDI_tc_1_SLOT0123 ,
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
// ALU64
InstrItinData<ALU64_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
InstrItinData<ALU64_tc_2_SLOT23 , [InstrStage<2, [SLOT2, SLOT3]>]>,
InstrItinData<ALU64_tc_2early_SLOT23, [InstrStage<2, [SLOT2, SLOT3]>]>,
InstrItinData<ALU64_tc_3x_SLOT23 , [InstrStage<3, [SLOT2, SLOT3]>]>,
// CR -> System
InstrItinData<CR_tc_2_SLOT3 , [InstrStage<2, [SLOT3]>]>,
InstrItinData<CR_tc_2early_SLOT3 , [InstrStage<2, [SLOT3]>]>,
InstrItinData<CR_tc_3x_SLOT3 , [InstrStage<3, [SLOT3]>]>,
// Jump (conditional/unconditional/return etc)
InstrItinData<CR_tc_2early_SLOT23, [InstrStage<2, [SLOT2, SLOT3]>]>,
InstrItinData<CR_tc_3x_SLOT23 , [InstrStage<3, [SLOT2, SLOT3]>]>,
InstrItinData<CJ_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
InstrItinData<CJ_tc_2early_SLOT23, [InstrStage<2, [SLOT2, SLOT3]>]>,
InstrItinData<J_tc_2early_SLOT23 , [InstrStage<2, [SLOT2, SLOT3]>]>,
InstrItinData<J_tc_2early_CJUMP_UCJUMP_ARCHDEPSLOT , [InstrStage<1, [SLOT2, SLOT3]>]>,
// JR
InstrItinData<J_tc_2early_SLOT2 , [InstrStage<2, [SLOT2]>]>,
InstrItinData<J_tc_3stall_SLOT2 , [InstrStage<3, [SLOT2]>]>,
// Extender
InstrItinData<EXTENDER_tc_1_SLOT0123, [InstrStage<1,
[SLOT0, SLOT1, SLOT2, SLOT3]>]>,
// Load
InstrItinData<LD_tc_ld_SLOT01 , [InstrStage<3, [SLOT0, SLOT1]>]>,
InstrItinData<LD_tc_3or4stall_SLOT0, [InstrStage<4, [SLOT0]>]>,
InstrItinData<LD_tc_ld_SLOT0 , [InstrStage<3, [SLOT0]>]>,
// M
InstrItinData<M_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
InstrItinData<M_tc_2_SLOT23 , [InstrStage<2, [SLOT2, SLOT3]>]>,
InstrItinData<M_tc_3_SLOT23 , [InstrStage<3, [SLOT2, SLOT3]>]>,
InstrItinData<M_tc_3x_SLOT23 , [InstrStage<3, [SLOT2, SLOT3]>]>,
InstrItinData<M_tc_3or4x_SLOT23 , [InstrStage<4, [SLOT2, SLOT3]>]>,
InstrItinData<M_tc_3stall_SLOT23, [InstrStage<3, [SLOT2, SLOT3]>]>,
// Store
InstrItinData<ST_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>,
InstrItinData<ST_tc_3stall_SLOT0, [InstrStage<3, [SLOT0]>]>,
InstrItinData<ST_tc_ld_SLOT0 , [InstrStage<3, [SLOT0]>]>,
InstrItinData<ST_tc_st_SLOT0 , [InstrStage<1, [SLOT0]>]>,
// Subinsn
InstrItinData<SUBINSN_tc_2early_SLOT0, [InstrStage<2, [SLOT0]>]>,
InstrItinData<SUBINSN_tc_3stall_SLOT0, [InstrStage<3, [SLOT0]>]>,
InstrItinData<SUBINSN_tc_ld_SLOT0 , [InstrStage<3, [SLOT0]>]>,
InstrItinData<SUBINSN_tc_1_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>,
InstrItinData<SUBINSN_tc_2early_SLOT01,
[InstrStage<2, [SLOT0, SLOT1]>]>,
InstrItinData<SUBINSN_tc_ld_SLOT01 , [InstrStage<3, [SLOT0, SLOT1]>]>,
InstrItinData<SUBINSN_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>,
// S
InstrItinData<S_2op_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
InstrItinData<S_2op_tc_2_SLOT23 , [InstrStage<2, [SLOT2, SLOT3]>]>,
InstrItinData<S_2op_tc_2early_SLOT23, [InstrStage<2, [SLOT2, SLOT3]>]>,
// The S_2op_tc_3x_SLOT23 slots are 4 cycles on v60.
InstrItinData<S_2op_tc_3or4x_SLOT23 , [InstrStage<4, [SLOT2, SLOT3]>]>,
InstrItinData<S_3op_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
InstrItinData<S_3op_tc_2_SLOT23 , [InstrStage<2, [SLOT2, SLOT3]>]>,
InstrItinData<S_3op_tc_2early_SLOT23, [InstrStage<2, [SLOT2, SLOT3]>]>,
InstrItinData<S_3op_tc_3_SLOT23 , [InstrStage<3, [SLOT2, SLOT3]>]>,
InstrItinData<S_3op_tc_3stall_SLOT23, [InstrStage<3, [SLOT2, SLOT3]>]>,
InstrItinData<S_3op_tc_3x_SLOT23 , [InstrStage<3, [SLOT2, SLOT3]>]>,
// New Value Compare Jump
InstrItinData<NCJ_tc_3or4stall_SLOT0, [InstrStage<4, [SLOT0]>]>,
// Mem ops
InstrItinData<V2LDST_tc_st_SLOT0 , [InstrStage<1, [SLOT0]>]>,
InstrItinData<V2LDST_tc_ld_SLOT01 , [InstrStage<2, [SLOT0, SLOT1]>]>,
InstrItinData<V2LDST_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>,
InstrItinData<V4LDST_tc_st_SLOT0 , [InstrStage<1, [SLOT0]>]>,
InstrItinData<V4LDST_tc_ld_SLOT01 , [InstrStage<3, [SLOT0, SLOT1]>]>,
InstrItinData<V4LDST_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>,
// Endloop
InstrItinData<J_tc_2early_SLOT0123, [InstrStage<2, [SLOT_ENDLOOP]>]>,
// Vector
InstrItinData<COPROC_VMEM_vtc_long_SLOT01,
[InstrStage<3, [SLOT0, SLOT1]>]>,
InstrItinData<COPROC_VX_vtc_long_SLOT23 ,
[InstrStage<3, [SLOT2, SLOT3]>]>,
InstrItinData<COPROC_VX_vtc_SLOT23 ,
[InstrStage<3, [SLOT2, SLOT3]>]>,
InstrItinData<MAPPING_tc_1_SLOT0123 ,
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
// Duplex and Compound
InstrItinData<DUPLEX , [InstrStage<1, [SLOT0]>]>,
InstrItinData<COMPOUND_CJ_ARCHDEPSLOT , [InstrStage<1, [SLOT2, SLOT3]>]>,
InstrItinData<COMPOUND , [InstrStage<1, [SLOT2, SLOT3]>]>,
// Misc
InstrItinData<PREFIX , [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
InstrItinData<PSEUDO , [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
InstrItinData<PSEUDOM , [InstrStage<1, [SLOT2, SLOT3], 0>,
InstrStage<1, [SLOT2, SLOT3]>]>,
// Latest CVI spec definitions.
InstrItinData<CVI_VA,[InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
InstrStage<1, [CVI_XLANE,CVI_SHIFT,
CVI_MPY0, CVI_MPY1]>]>,
InstrItinData<CVI_VA_DV,
[InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
InstrStage<1, [CVI_XLSHF, CVI_MPY01]>]>,
InstrItinData<CVI_VX_LONG, [InstrStage<1, [SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_MPY0, CVI_MPY1]>]>,
InstrItinData<CVI_VX_LATE, [InstrStage<1, [SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_MPY0, CVI_MPY1]>]>,
InstrItinData<CVI_VX,[InstrStage<1, [SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_MPY0, CVI_MPY1]>]>,
InstrItinData<CVI_VX_DV_LONG,
[InstrStage<1, [SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_MPY01]>]>,
InstrItinData<CVI_VX_DV,
[InstrStage<1, [SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_MPY01]>]>,
InstrItinData<CVI_VX_DV_SLOT2,
[InstrStage<1, [SLOT2], 0>,
InstrStage<1, [CVI_MPY01]>]>,
InstrItinData<CVI_VP, [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
InstrStage<1, [CVI_XLANE]>]>,
InstrItinData<CVI_VP_LONG, [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
InstrStage<1, [CVI_XLANE]>]>,
InstrItinData<CVI_VP_VS_EARLY,
[InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
InstrStage<1, [CVI_XLSHF]>]>,
InstrItinData<CVI_VP_VS_LONG,
[InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
InstrStage<1, [CVI_XLSHF]>]>,
InstrItinData<CVI_VP_VS,
[InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
InstrStage<1, [CVI_XLSHF]>]>,
InstrItinData<CVI_VP_VS_LONG_EARLY,
[InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
InstrStage<1, [CVI_XLSHF]>]>,
InstrItinData<CVI_VP_DV , [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
InstrStage<1, [CVI_XLSHF]>]>,
InstrItinData<CVI_VS,
[InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
InstrStage<1, [CVI_SHIFT]>]>,
InstrItinData<CVI_VINLANESAT,
[InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
InstrStage<1, [CVI_SHIFT]>]>,
InstrItinData<CVI_VM_LD , [InstrStage<1, [SLOT0, SLOT1], 0>,
InstrStage<1, [CVI_LD], 0>,
InstrStage<1, [CVI_XLANE, CVI_SHIFT,
CVI_MPY0, CVI_MPY1]>]>,
InstrItinData<CVI_VM_TMP_LD,[InstrStage<1,[SLOT0, SLOT1], 0>,
InstrStage<1, [CVI_LD]>]>,
InstrItinData<CVI_VM_CUR_LD,[InstrStage<1,[SLOT0, SLOT1], 0>,
InstrStage<1, [CVI_LD], 0>,
InstrStage<1, [CVI_XLANE, CVI_SHIFT,
CVI_MPY0, CVI_MPY1]>]>,
InstrItinData<CVI_VM_VP_LDU,[InstrStage<1,[SLOT0], 0>,
InstrStage<1, [SLOT1], 0>,
InstrStage<1, [CVI_LD], 0>,
InstrStage<1, [CVI_XLANE]>]>,
InstrItinData<CVI_VM_ST , [InstrStage<1, [SLOT0], 0>,
InstrStage<1, [CVI_ST], 0>,
InstrStage<1, [CVI_XLANE, CVI_SHIFT,
CVI_MPY0, CVI_MPY1]>]>,
InstrItinData<CVI_VM_NEW_ST,[InstrStage<1,[SLOT0], 0>,
InstrStage<1, [CVI_ST]>]>,
InstrItinData<CVI_VM_STU , [InstrStage<1, [SLOT0], 0>,
InstrStage<1, [SLOT1], 0>,
InstrStage<1, [CVI_ST], 0>,
InstrStage<1, [CVI_XLANE]>]>,
InstrItinData<CVI_HIST , [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
InstrStage<1, [CVI_ALL]>]>
]>;
def HexagonModelV60 : SchedMachineModel {
// Max issue per cycle == bundle width.
let IssueWidth = 4;
let Itineraries = HexagonItinerariesV60;
let LoadLatency = 1;
}
//===----------------------------------------------------------------------===//
// Hexagon V60 Resource Definitions -
//===----------------------------------------------------------------------===//

8
lib/Target/Hexagon/HexagonSubtarget.h
View File

@ -34,12 +34,12 @@ namespace llvm {
class HexagonSubtarget : public HexagonGenSubtargetInfo { class HexagonSubtarget : public HexagonGenSubtargetInfo {
virtual void anchor(); virtual void anchor();
bool UseMemOps; bool UseMemOps, UseHVXOps, UseHVXDblOps;
bool ModeIEEERndNear; bool ModeIEEERndNear;
public: public:
enum HexagonArchEnum { enum HexagonArchEnum {
V4, V5 V4, V5, V55, V60
}; };
HexagonArchEnum HexagonArchVersion; HexagonArchEnum HexagonArchVersion;
@ -84,7 +84,11 @@ public:
bool useMemOps() const { return UseMemOps; } bool useMemOps() const { return UseMemOps; }
bool hasV5TOps() const { return getHexagonArchVersion() >= V5; } bool hasV5TOps() const { return getHexagonArchVersion() >= V5; }
bool hasV5TOpsOnly() const { return getHexagonArchVersion() == V5; } bool hasV5TOpsOnly() const { return getHexagonArchVersion() == V5; }
bool hasV60TOps() const { return getHexagonArchVersion() >= V60; }
bool hasV60TOpsOnly() const { return getHexagonArchVersion() == V60; }
bool modeIEEERndNear() const { return ModeIEEERndNear; } bool modeIEEERndNear() const { return ModeIEEERndNear; }
bool useHVXDblOps() const { return UseHVXDblOps; }
bool useHVXSglOps() const { return UseHVXOps && !UseHVXDblOps; }
bool enableMachineScheduler() const override; bool enableMachineScheduler() const override;
// Always use the TargetLowering default scheduler. // Always use the TargetLowering default scheduler.
// FIXME: This will use the vliw scheduler which is probably just hurting // FIXME: This will use the vliw scheduler which is probably just hurting

28
lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.cpp
View File

@ -178,6 +178,34 @@ void HexagonInstPrinter::printNOneImmOperand(const MCInst *MI, unsigned OpNo,
O << -1; O << -1;
} }
void HexagonInstPrinter::prints3_6ImmOperand(MCInst const *MI, unsigned OpNo,
raw_ostream &O) const {
int64_t Imm = MI->getOperand(OpNo).getImm();
assert(((Imm & 0x3f) == 0) && "Lower 6 bits must be ZERO.");
O << formatImm(Imm/64);
}
void HexagonInstPrinter::prints3_7ImmOperand(MCInst const *MI, unsigned OpNo,
raw_ostream &O) const {
int64_t Imm = MI->getOperand(OpNo).getImm();
assert(((Imm & 0x7f) == 0) && "Lower 7 bits must be ZERO.");
O << formatImm(Imm/128);
}
void HexagonInstPrinter::prints4_6ImmOperand(MCInst const *MI, unsigned OpNo,
raw_ostream &O) const {
int64_t Imm = MI->getOperand(OpNo).getImm();
assert(((Imm & 0x3f) == 0) && "Lower 6 bits must be ZERO.");
O << formatImm(Imm/64);
}
void HexagonInstPrinter::prints4_7ImmOperand(MCInst const *MI, unsigned OpNo,
raw_ostream &O) const {
int64_t Imm = MI->getOperand(OpNo).getImm();
assert(((Imm & 0x7f) == 0) && "Lower 7 bits must be ZERO.");
O << formatImm(Imm/128);
}
void HexagonInstPrinter::printMEMriOperand(const MCInst *MI, unsigned OpNo, void HexagonInstPrinter::printMEMriOperand(const MCInst *MI, unsigned OpNo,
raw_ostream &O) const { raw_ostream &O) const {
const MCOperand& MO0 = MI->getOperand(OpNo); const MCOperand& MO0 = MI->getOperand(OpNo);

8
lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.h
View File

@ -48,6 +48,14 @@ namespace llvm {
const; const;
void printNOneImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) void printNOneImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O)
const; const;
void prints3_6ImmOperand(MCInst const *MI, unsigned OpNo,
raw_ostream &O) const;
void prints3_7ImmOperand(MCInst const *MI, unsigned OpNo,
raw_ostream &O) const;
void prints4_6ImmOperand(MCInst const *MI, unsigned OpNo,
raw_ostream &O) const;
void prints4_7ImmOperand(MCInst const *MI, unsigned OpNo,
raw_ostream &O) const;
void printMEMriOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) void printMEMriOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O)
const; const;
void printFrameIndexOperand(const MCInst *MI, unsigned OpNo, void printFrameIndexOperand(const MCInst *MI, unsigned OpNo,

3
test/CodeGen/Generic/MachineBranchProb.ll
View File

@ -1,8 +1,7 @@
; RUN: llc < %s -print-machineinstrs=expand-isel-pseudos -o /dev/null 2>&1 | FileCheck %s ; RUN: llc < %s -print-machineinstrs=expand-isel-pseudos -o /dev/null 2>&1 | FileCheck %s
; ARM & AArch64 run an extra SimplifyCFG which disrupts this test. ; ARM & AArch64 run an extra SimplifyCFG which disrupts this test.
; Hexagon crashes (PR23377) ; XFAIL: arm,aarch64
; XFAIL: arm,aarch64,hexagon
; Make sure we have the correct weight attached to each successor. ; Make sure we have the correct weight attached to each successor.
define i32 @test2(i32 %x) nounwind uwtable readnone ssp { define i32 @test2(i32 %x) nounwind uwtable readnone ssp {