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AMDGPU: Handle 32-bit address wraparounds for SMRD opcodes
Summary: This fixes GPU hangs with OpenGL bindless handle arithmetic. Reviewers: arsenm, nhaehnle Subscribers: kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D51203 llvm-svn: 340959
This commit is contained in:
Marek Olsak
parent
c3b4726b4b
commit
fa68af9f80
@ -1408,7 +1408,11 @@ bool AMDGPUDAGToDAGISel::SelectSMRD(SDValue Addr, SDValue &SBase,
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SDValue &Offset, bool &Imm) const {
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SDLoc SL(Addr);
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if (CurDAG->isBaseWithConstantOffset(Addr)) {
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// A 32-bit (address + offset) should not cause unsigned 32-bit integer
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// wraparound, because s_load instructions perform the addition in 64 bits.
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if ((Addr.getValueType() != MVT::i32 ||
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Addr->getFlags().hasNoUnsignedWrap()) &&
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CurDAG->isBaseWithConstantOffset(Addr)) {
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SDValue N0 = Addr.getOperand(0);
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SDValue N1 = Addr.getOperand(1);
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@ -12,7 +12,7 @@
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; VIGFX9-DAG: s_load_dword s{{[0-9]}}, s[0:1], 0x0
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; VIGFX9-DAG: s_load_dword s{{[0-9]}}, s[2:3], 0x8
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define amdgpu_vs float @load_i32(i32 addrspace(6)* inreg %p0, i32 addrspace(6)* inreg %p1) #0 {
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%gep1 = getelementptr i32, i32 addrspace(6)* %p1, i64 2
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%gep1 = getelementptr inbounds i32, i32 addrspace(6)* %p1, i32 2
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%r0 = load i32, i32 addrspace(6)* %p0
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%r1 = load i32, i32 addrspace(6)* %gep1
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%r = add i32 %r0, %r1
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@ -29,7 +29,7 @@ define amdgpu_vs float @load_i32(i32 addrspace(6)* inreg %p0, i32 addrspace(6)*
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; VIGFX9-DAG: s_load_dwordx2 s[{{.*}}], s[0:1], 0x0
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; VIGFX9-DAG: s_load_dwordx2 s[{{.*}}], s[2:3], 0x10
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define amdgpu_vs <2 x float> @load_v2i32(<2 x i32> addrspace(6)* inreg %p0, <2 x i32> addrspace(6)* inreg %p1) #0 {
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%gep1 = getelementptr <2 x i32>, <2 x i32> addrspace(6)* %p1, i64 2
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%gep1 = getelementptr inbounds <2 x i32>, <2 x i32> addrspace(6)* %p1, i32 2
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%r0 = load <2 x i32>, <2 x i32> addrspace(6)* %p0
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%r1 = load <2 x i32>, <2 x i32> addrspace(6)* %gep1
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%r = add <2 x i32> %r0, %r1
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@ -46,7 +46,7 @@ define amdgpu_vs <2 x float> @load_v2i32(<2 x i32> addrspace(6)* inreg %p0, <2 x
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; VIGFX9-DAG: s_load_dwordx4 s[{{.*}}], s[0:1], 0x0
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; VIGFX9-DAG: s_load_dwordx4 s[{{.*}}], s[2:3], 0x20
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define amdgpu_vs <4 x float> @load_v4i32(<4 x i32> addrspace(6)* inreg %p0, <4 x i32> addrspace(6)* inreg %p1) #0 {
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%gep1 = getelementptr <4 x i32>, <4 x i32> addrspace(6)* %p1, i64 2
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%gep1 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(6)* %p1, i32 2
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%r0 = load <4 x i32>, <4 x i32> addrspace(6)* %p0
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%r1 = load <4 x i32>, <4 x i32> addrspace(6)* %gep1
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%r = add <4 x i32> %r0, %r1
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@ -63,7 +63,7 @@ define amdgpu_vs <4 x float> @load_v4i32(<4 x i32> addrspace(6)* inreg %p0, <4 x
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; VIGFX9-DAG: s_load_dwordx8 s[{{.*}}], s[0:1], 0x0
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; VIGFX9-DAG: s_load_dwordx8 s[{{.*}}], s[2:3], 0x40
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define amdgpu_vs <8 x float> @load_v8i32(<8 x i32> addrspace(6)* inreg %p0, <8 x i32> addrspace(6)* inreg %p1) #0 {
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%gep1 = getelementptr <8 x i32>, <8 x i32> addrspace(6)* %p1, i64 2
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%gep1 = getelementptr inbounds <8 x i32>, <8 x i32> addrspace(6)* %p1, i32 2
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%r0 = load <8 x i32>, <8 x i32> addrspace(6)* %p0
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%r1 = load <8 x i32>, <8 x i32> addrspace(6)* %gep1
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%r = add <8 x i32> %r0, %r1
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@ -80,7 +80,7 @@ define amdgpu_vs <8 x float> @load_v8i32(<8 x i32> addrspace(6)* inreg %p0, <8 x
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; VIGFX9-DAG: s_load_dwordx16 s[{{.*}}], s[0:1], 0x0
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; VIGFX9-DAG: s_load_dwordx16 s[{{.*}}], s[2:3], 0x80
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define amdgpu_vs <16 x float> @load_v16i32(<16 x i32> addrspace(6)* inreg %p0, <16 x i32> addrspace(6)* inreg %p1) #0 {
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%gep1 = getelementptr <16 x i32>, <16 x i32> addrspace(6)* %p1, i64 2
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%gep1 = getelementptr inbounds <16 x i32>, <16 x i32> addrspace(6)* %p1, i32 2
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%r0 = load <16 x i32>, <16 x i32> addrspace(6)* %p0
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%r1 = load <16 x i32>, <16 x i32> addrspace(6)* %gep1
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%r = add <16 x i32> %r0, %r1
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@ -97,7 +97,7 @@ define amdgpu_vs <16 x float> @load_v16i32(<16 x i32> addrspace(6)* inreg %p0, <
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; VIGFX9-DAG: s_load_dword s{{[0-9]}}, s[0:1], 0x0
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; VIGFX9-DAG: s_load_dword s{{[0-9]}}, s[2:3], 0x8
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define amdgpu_vs float @load_float(float addrspace(6)* inreg %p0, float addrspace(6)* inreg %p1) #0 {
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%gep1 = getelementptr float, float addrspace(6)* %p1, i64 2
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%gep1 = getelementptr inbounds float, float addrspace(6)* %p1, i32 2
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%r0 = load float, float addrspace(6)* %p0
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%r1 = load float, float addrspace(6)* %gep1
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%r = fadd float %r0, %r1
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@ -113,7 +113,7 @@ define amdgpu_vs float @load_float(float addrspace(6)* inreg %p0, float addrspac
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; VIGFX9-DAG: s_load_dwordx2 s[{{.*}}], s[0:1], 0x0
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; VIGFX9-DAG: s_load_dwordx2 s[{{.*}}], s[2:3], 0x10
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define amdgpu_vs <2 x float> @load_v2float(<2 x float> addrspace(6)* inreg %p0, <2 x float> addrspace(6)* inreg %p1) #0 {
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%gep1 = getelementptr <2 x float>, <2 x float> addrspace(6)* %p1, i64 2
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%gep1 = getelementptr inbounds <2 x float>, <2 x float> addrspace(6)* %p1, i32 2
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%r0 = load <2 x float>, <2 x float> addrspace(6)* %p0
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%r1 = load <2 x float>, <2 x float> addrspace(6)* %gep1
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%r = fadd <2 x float> %r0, %r1
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@ -129,7 +129,7 @@ define amdgpu_vs <2 x float> @load_v2float(<2 x float> addrspace(6)* inreg %p0,
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; VIGFX9-DAG: s_load_dwordx4 s[{{.*}}], s[0:1], 0x0
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; VIGFX9-DAG: s_load_dwordx4 s[{{.*}}], s[2:3], 0x20
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define amdgpu_vs <4 x float> @load_v4float(<4 x float> addrspace(6)* inreg %p0, <4 x float> addrspace(6)* inreg %p1) #0 {
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%gep1 = getelementptr <4 x float>, <4 x float> addrspace(6)* %p1, i64 2
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%gep1 = getelementptr inbounds <4 x float>, <4 x float> addrspace(6)* %p1, i32 2
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%r0 = load <4 x float>, <4 x float> addrspace(6)* %p0
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%r1 = load <4 x float>, <4 x float> addrspace(6)* %gep1
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%r = fadd <4 x float> %r0, %r1
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@ -145,7 +145,7 @@ define amdgpu_vs <4 x float> @load_v4float(<4 x float> addrspace(6)* inreg %p0,
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; VIGFX9-DAG: s_load_dwordx8 s[{{.*}}], s[0:1], 0x0
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; VIGFX9-DAG: s_load_dwordx8 s[{{.*}}], s[2:3], 0x40
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define amdgpu_vs <8 x float> @load_v8float(<8 x float> addrspace(6)* inreg %p0, <8 x float> addrspace(6)* inreg %p1) #0 {
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%gep1 = getelementptr <8 x float>, <8 x float> addrspace(6)* %p1, i64 2
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%gep1 = getelementptr inbounds <8 x float>, <8 x float> addrspace(6)* %p1, i32 2
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%r0 = load <8 x float>, <8 x float> addrspace(6)* %p0
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%r1 = load <8 x float>, <8 x float> addrspace(6)* %gep1
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%r = fadd <8 x float> %r0, %r1
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@ -161,7 +161,7 @@ define amdgpu_vs <8 x float> @load_v8float(<8 x float> addrspace(6)* inreg %p0,
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; VIGFX9-DAG: s_load_dwordx16 s[{{.*}}], s[0:1], 0x0
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; VIGFX9-DAG: s_load_dwordx16 s[{{.*}}], s[2:3], 0x80
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define amdgpu_vs <16 x float> @load_v16float(<16 x float> addrspace(6)* inreg %p0, <16 x float> addrspace(6)* inreg %p1) #0 {
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%gep1 = getelementptr <16 x float>, <16 x float> addrspace(6)* %p1, i64 2
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%gep1 = getelementptr inbounds <16 x float>, <16 x float> addrspace(6)* %p1, i32 2
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%r0 = load <16 x float>, <16 x float> addrspace(6)* %p0
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%r1 = load <16 x float>, <16 x float> addrspace(6)* %gep1
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%r = fadd <16 x float> %r0, %r1
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@ -212,12 +212,12 @@ main_body:
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%22 = call nsz float @llvm.amdgcn.interp.mov(i32 2, i32 0, i32 0, i32 %5) #8
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%23 = bitcast float %22 to i32
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%24 = shl i32 %23, 1
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%25 = getelementptr [0 x <8 x i32>], [0 x <8 x i32>] addrspace(6)* %1, i32 0, i32 %24, !amdgpu.uniform !0
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%25 = getelementptr inbounds [0 x <8 x i32>], [0 x <8 x i32>] addrspace(6)* %1, i32 0, i32 %24, !amdgpu.uniform !0
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%26 = load <8 x i32>, <8 x i32> addrspace(6)* %25, align 32, !invariant.load !0
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%27 = shl i32 %23, 2
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%28 = or i32 %27, 3
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%29 = bitcast [0 x <8 x i32>] addrspace(6)* %1 to [0 x <4 x i32>] addrspace(6)*
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%30 = getelementptr [0 x <4 x i32>], [0 x <4 x i32>] addrspace(6)* %29, i32 0, i32 %28, !amdgpu.uniform !0
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%30 = getelementptr inbounds [0 x <4 x i32>], [0 x <4 x i32>] addrspace(6)* %29, i32 0, i32 %28, !amdgpu.uniform !0
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%31 = load <4 x i32>, <4 x i32> addrspace(6)* %30, align 16, !invariant.load !0
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%32 = call nsz <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float 0.0, <8 x i32> %26, <4 x i32> %31, i1 0, i32 0, i32 0) #8
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%33 = extractelement <4 x float> %32, i32 0
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@ -246,12 +246,12 @@ main_body:
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%22 = call nsz float @llvm.amdgcn.interp.mov(i32 2, i32 0, i32 0, i32 %5) #8
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%23 = bitcast float %22 to i32
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%24 = shl i32 %23, 1
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%25 = getelementptr [0 x <8 x i32>], [0 x <8 x i32>] addrspace(6)* %1, i32 0, i32 %24
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%25 = getelementptr inbounds [0 x <8 x i32>], [0 x <8 x i32>] addrspace(6)* %1, i32 0, i32 %24
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%26 = load <8 x i32>, <8 x i32> addrspace(6)* %25, align 32, !invariant.load !0
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%27 = shl i32 %23, 2
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%28 = or i32 %27, 3
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%29 = bitcast [0 x <8 x i32>] addrspace(6)* %1 to [0 x <4 x i32>] addrspace(6)*
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%30 = getelementptr [0 x <4 x i32>], [0 x <4 x i32>] addrspace(6)* %29, i32 0, i32 %28
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%30 = getelementptr inbounds [0 x <4 x i32>], [0 x <4 x i32>] addrspace(6)* %29, i32 0, i32 %28
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%31 = load <4 x i32>, <4 x i32> addrspace(6)* %30, align 16, !invariant.load !0
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%32 = call nsz <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float 0.0, <8 x i32> %26, <4 x i32> %31, i1 0, i32 0, i32 0) #8
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%33 = extractelement <4 x float> %32, i32 0
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@ -268,6 +268,17 @@ main_body:
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ret <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %43
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}
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; GCN-LABEL: {{^}}load_addr_no_fold:
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; GCN-DAG: s_add_i32 s0, s0, 4
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; GCN-DAG: s_mov_b32 s1, 0
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; GCN: s_load_dword s{{[0-9]}}, s[0:1], 0x0
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define amdgpu_vs float @load_addr_no_fold(i32 addrspace(6)* inreg noalias %p0) #0 {
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%gep1 = getelementptr i32, i32 addrspace(6)* %p0, i32 1
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%r1 = load i32, i32 addrspace(6)* %gep1
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%r2 = bitcast i32 %r1 to float
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ret float %r2
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}
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; Function Attrs: nounwind readnone speculatable
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declare float @llvm.amdgcn.interp.mov(i32, i32, i32, i32) #6
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