From faa6fb3cc493c5c7639c844402a46f917ac9fc67 Mon Sep 17 00:00:00 2001 From: Momchil Velikov Date: Fri, 7 Feb 2020 11:38:46 +0000 Subject: [PATCH] [AArch64] Predictably disassemble system registers with the same encoding The registers TRCEXTINSELR and TRCEXTINSELR0 are distinct registers, defined by separate extension specifications (ETM and ETE, respectively), yet they use the same encoding in MSR/MRS. When performing a system register lookup by encoding, we would essentially return a random one, depending on the number, relative position in the TableGen file, whether the TableGen records for system registers are named or not, and, if they are named, depending on record (not register!) name as well. This patch works around the issue by explictly checking for the TRCEXTINSELR/TRCEXTINSELR0 encoding and always returning TRCEXTINSELR. Differential Revision: https://reviews.llvm.org/D74074 --- .../AArch64/MCTargetDesc/AArch64InstPrinter.cpp | 12 ++++++++++++ test/MC/AArch64/ete-sysregs.s | 8 ++++---- test/MC/AArch64/trace-regs.s | 4 ++-- test/MC/Disassembler/AArch64/ete.txt | 2 +- test/MC/Disassembler/AArch64/trace-regs.txt | 2 +- 5 files changed, 20 insertions(+), 8 deletions(-) diff --git a/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp b/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp index 469892213ef..f0a2dd76710 100644 --- a/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp +++ b/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp @@ -1411,6 +1411,12 @@ void AArch64InstPrinter::printMRSSystemRegister(const MCInst *MI, unsigned OpNo, return; } + // Horrible hack for two different registers having the same encoding. + if (Val == AArch64SysReg::TRCEXTINSELR) { + O << "TRCEXTINSELR"; + return; + } + const AArch64SysReg::SysReg *Reg = AArch64SysReg::lookupSysRegByEncoding(Val); if (Reg && Reg->Readable && Reg->haveFeatures(STI.getFeatureBits())) O << Reg->Name; @@ -1431,6 +1437,12 @@ void AArch64InstPrinter::printMSRSystemRegister(const MCInst *MI, unsigned OpNo, return; } + // Horrible hack for two different registers having the same encoding. + if (Val == AArch64SysReg::TRCEXTINSELR) { + O << "TRCEXTINSELR"; + return; + } + const AArch64SysReg::SysReg *Reg = AArch64SysReg::lookupSysRegByEncoding(Val); if (Reg && Reg->Writeable && Reg->haveFeatures(STI.getFeatureBits())) O << Reg->Name; diff --git a/test/MC/AArch64/ete-sysregs.s b/test/MC/AArch64/ete-sysregs.s index 5d0d293f2d5..fb5e42a9c60 100644 --- a/test/MC/AArch64/ete-sysregs.s +++ b/test/MC/AArch64/ete-sysregs.s @@ -11,8 +11,8 @@ mrs x0, TRCEXTINSELR2 mrs x0, TRCEXTINSELR3 // CHECK: mrs x0, TRCRSR // encoding: [0x00,0x0a,0x31,0xd5] -// CHECK: mrs x0, TRCEXTINSELR0 // encoding: [0x80,0x08,0x31,0xd5] -// CHECK: mrs x0, TRCEXTINSELR0 // encoding: [0x80,0x08,0x31,0xd5] +// CHECK: mrs x0, TRCEXTINSELR // encoding: [0x80,0x08,0x31,0xd5] +// CHECK: mrs x0, TRCEXTINSELR // encoding: [0x80,0x08,0x31,0xd5] // CHECK: mrs x0, TRCEXTINSELR1 // encoding: [0x80,0x09,0x31,0xd5] // CHECK: mrs x0, TRCEXTINSELR2 // encoding: [0x80,0x0a,0x31,0xd5] // CHECK: mrs x0, TRCEXTINSELR3 // encoding: [0x80,0x0b,0x31,0xd5] @@ -26,8 +26,8 @@ msr TRCEXTINSELR2, x0 msr TRCEXTINSELR3, x0 // CHECK: msr TRCRSR, x0 // encoding: [0x00,0x0a,0x11,0xd5] -// CHECK: msr TRCEXTINSELR0, x0 // encoding: [0x80,0x08,0x11,0xd5] -// CHECK: msr TRCEXTINSELR0, x0 // encoding: [0x80,0x08,0x11,0xd5] +// CHECK: msr TRCEXTINSELR, x0 // encoding: [0x80,0x08,0x11,0xd5] +// CHECK: msr TRCEXTINSELR, x0 // encoding: [0x80,0x08,0x11,0xd5] // CHECK: msr TRCEXTINSELR1, x0 // encoding: [0x80,0x09,0x11,0xd5] // CHECK: msr TRCEXTINSELR2, x0 // encoding: [0x80,0x0a,0x11,0xd5] // CHECK: msr TRCEXTINSELR3, x0 // encoding: [0x80,0x0b,0x11,0xd5] diff --git a/test/MC/AArch64/trace-regs.s b/test/MC/AArch64/trace-regs.s index 25738ddd649..5b29ebbdb38 100644 --- a/test/MC/AArch64/trace-regs.s +++ b/test/MC/AArch64/trace-regs.s @@ -269,7 +269,7 @@ // CHECK: mrs x26, {{trcseqevr2|TRCSEQEVR2}} // encoding: [0x9a,0x02,0x31,0xd5] // CHECK: mrs x14, {{trcseqrstevr|TRCSEQRSTEVR}} // encoding: [0x8e,0x06,0x31,0xd5] // CHECK: mrs x4, {{trcseqstr|TRCSEQSTR}} // encoding: [0x84,0x07,0x31,0xd5] -// CHECK: mrs x17, {{trcextinselr|TRCEXTINSELR0}} // encoding: [0x91,0x08,0x31,0xd5] +// CHECK: mrs x17, {{trcextinselr|TRCEXTINSELR}} // encoding: [0x91,0x08,0x31,0xd5] // CHECK: mrs x21, {{trccntrldvr0|TRCCNTRLDVR0}} // encoding: [0xb5,0x00,0x31,0xd5] // CHECK: mrs x10, {{trccntrldvr1|TRCCNTRLDVR1}} // encoding: [0xaa,0x01,0x31,0xd5] // CHECK: mrs x20, {{trccntrldvr2|TRCCNTRLDVR2}} // encoding: [0xb4,0x02,0x31,0xd5] @@ -618,7 +618,7 @@ // CHECK: msr {{trcseqevr2|TRCSEQEVR2}}, x16 // encoding: [0x90,0x02,0x11,0xd5] // CHECK: msr {{trcseqrstevr|TRCSEQRSTEVR}}, x16 // encoding: [0x90,0x06,0x11,0xd5] // CHECK: msr {{trcseqstr|TRCSEQSTR}}, x25 // encoding: [0x99,0x07,0x11,0xd5] -// CHECK: msr {{trcextinselr|TRCEXTINSELR0}}, x29 // encoding: [0x9d,0x08,0x11,0xd5] +// CHECK: msr {{trcextinselr|TRCEXTINSELR}}, x29 // encoding: [0x9d,0x08,0x11,0xd5] // CHECK: msr {{trccntrldvr0|TRCCNTRLDVR0}}, x20 // encoding: [0xb4,0x00,0x11,0xd5] // CHECK: msr {{trccntrldvr1|TRCCNTRLDVR1}}, x20 // encoding: [0xb4,0x01,0x11,0xd5] // CHECK: msr {{trccntrldvr2|TRCCNTRLDVR2}}, x22 // encoding: [0xb6,0x02,0x11,0xd5] diff --git a/test/MC/Disassembler/AArch64/ete.txt b/test/MC/Disassembler/AArch64/ete.txt index f9a43d5195a..69c75609bfe 100644 --- a/test/MC/Disassembler/AArch64/ete.txt +++ b/test/MC/Disassembler/AArch64/ete.txt @@ -24,7 +24,7 @@ # CHECK: msr TRCRSR, x0 [0x80,0x08,0x11,0xd5] -# CHECK: msr TRCEXTINSELR0, x0 +# CHECK: msr TRCEXTINSELR, x0 [0x80,0x09,0x11,0xd5] # CHECK: msr TRCEXTINSELR1, x0 diff --git a/test/MC/Disassembler/AArch64/trace-regs.txt b/test/MC/Disassembler/AArch64/trace-regs.txt index bcaad740581..43171e3d2f6 100644 --- a/test/MC/Disassembler/AArch64/trace-regs.txt +++ b/test/MC/Disassembler/AArch64/trace-regs.txt @@ -456,7 +456,7 @@ 0x99 0x7 0x11 0xd5 # CHECK: msr {{trcseqstr|TRCSEQSTR}}, x25 0x9d 0x8 0x11 0xd5 -# CHECK: msr {{trcextinselr|TRCEXTINSELR0}}, x29 +# CHECK: msr {{trcextinselr|TRCEXTINSELR}}, x29 0xb4 0x0 0x11 0xd5 # CHECK: msr {{trccntrldvr0|TRCCNTRLDVR0}}, x20 0xb4 0x1 0x11 0xd5