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[AArch64] Reverting FP16 vcvth_n_s64_f16 to fix

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llvm-svn: 335737
This commit is contained in:
Luke Geeson 2018-06-27 14:34:40 +00:00
parent 65794251d1
commit fade465f79
2 changed files with 0 additions and 22 deletions
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2
lib/Target/AArch64/AArch64InstrInfo.td
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@ -4979,8 +4979,6 @@ def : Pat<(f16 (int_aarch64_neon_vcvtfxs2fp (i32 (sext_inreg FPR32:$Rn, i16)), v
(SCVTFh (EXTRACT_SUBREG FPR32:$Rn, hsub), vecshiftR16:$imm)>;
def : Pat<(f16 (int_aarch64_neon_vcvtfxs2fp (i32 FPR32:$Rn), vecshiftR16:$imm)),
(SCVTFh (EXTRACT_SUBREG FPR32:$Rn, hsub), vecshiftR16:$imm)>;
def : Pat<(f16 (int_aarch64_neon_vcvtfxs2fp (i64 FPR64:$Rn), vecshiftR16:$imm)),
(SCVTFh (EXTRACT_SUBREG FPR64:$Rn, hsub), vecshiftR16:$imm)>;
def : Pat<(f16 (int_aarch64_neon_vcvtfxu2fp
(and FPR32:$Rn, (i32 65535)),
vecshiftR16:$imm)),

20
test/CodeGen/AArch64/fp16_intrinsic_scalar_2op.ll
View File

@ -176,26 +176,6 @@ entry:
ret half %vcvth_n_f16_s32
}
define dso_local half @test_vcvth_n_f16_s64_1(i64 %a) {
; CHECK-LABEL: test_vcvth_n_f16_s64_1:
; CHECK: fmov d0, x0
; CHECK-NEXT: scvtf h0, h0, #1
; CHECK-NEXT: ret
entry:
%vcvth_n_f16_s64 = tail call half @llvm.aarch64.neon.vcvtfxs2fp.f16.i64(i64 %a, i32 1)
ret half %vcvth_n_f16_s64
}
define dso_local half @test_vcvth_n_f16_s64_16(i64 %a) {
; CHECK-LABEL: test_vcvth_n_f16_s64_16:
; CHECK: fmov d0, x0
; CHECK-NEXT: scvtf h0, h0, #16
; CHECK-NEXT: ret
entry:
%vcvth_n_f16_s64 = tail call half @llvm.aarch64.neon.vcvtfxs2fp.f16.i64(i64 %a, i32 16)
ret half %vcvth_n_f16_s64
}
define dso_local i16 @test_vcvth_n_s16_f16_1(half %a) {
; CHECK-LABEL: test_vcvth_n_s16_f16_1:
; CHECK: fcvtzs h0, h0, #1