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[VE] Fix types of multiclass template arguments in TableGen files
There were not properly checked before `[TableGen] Improve handling of template arguments`.
This commit is contained in:
Fangrui Song
parent
566ea91075
commit
faf0152f73
@ -793,7 +793,7 @@ multiclass PFCHm<string opcStr, bits<8>opc> {
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let Constraints = "$dest = $sd", DisableEncoding = "$sd",
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mayStore=1, mayLoad = 1, hasSideEffects = 0 in
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multiclass RRCAStgm<string opcStr, bits<8>opc, RegisterClass RC, ValueType Ty,
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Operand immOp, Operand MEM, Operand ADDR,
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Operand immOp, Operand MEM, ComplexPattern ADDR,
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SDPatternOperator OpNode = null_frag> {
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def r : RRM<opc, (outs RC:$dest), (ins MEM:$addr, RC:$sy, RC:$sd),
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!strconcat(opcStr, " $dest, $addr, $sy"),
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@ -1719,10 +1719,10 @@ def : Pat<(i64 (anyext i32:$sy)),
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// extload, sextload and zextload stuff
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multiclass EXT64m<SDPatternOperator from,
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SDPatternOperator torri,
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SDPatternOperator torii,
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SDPatternOperator tozri,
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SDPatternOperator tozii> {
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RM torri,
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RM torii,
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RM tozri,
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RM tozii> {
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def : Pat<(i64 (from ADDRrri:$addr)),
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(INSERT_SUBREG (i64 (IMPLICIT_DEF)), (torri MEMrri:$addr),
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sub_i32)>;
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@ -1748,10 +1748,10 @@ defm : EXT64m<extloadi32, LDLSXrri, LDLSXrii, LDLSXzri, LDLSXzii>;
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// anyextload
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multiclass EXT32m<SDPatternOperator from,
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SDPatternOperator torri,
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SDPatternOperator torii,
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SDPatternOperator tozri,
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SDPatternOperator tozii> {
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RM torri,
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RM torii,
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RM tozri,
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RM tozii> {
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def : Pat<(from ADDRrri:$addr), (torri MEMrri:$addr)>;
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def : Pat<(from ADDRrii:$addr), (torii MEMrii:$addr)>;
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def : Pat<(from ADDRzri:$addr), (tozri MEMzri:$addr)>;
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@ -1762,10 +1762,10 @@ defm : EXT32m<extloadi16, LD2BZXrri, LD2BZXrii, LD2BZXzri, LD2BZXzii>;
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// truncstore
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multiclass TRUNC64m<SDPatternOperator from,
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SDPatternOperator torri,
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SDPatternOperator torii,
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SDPatternOperator tozri,
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SDPatternOperator tozii> {
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RM torri,
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RM torii,
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RM tozri,
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RM tozii> {
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def : Pat<(from i64:$src, ADDRrri:$addr),
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(torri MEMrri:$addr, (EXTRACT_SUBREG $src, sub_i32))>;
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def : Pat<(from i64:$src, ADDRrii:$addr),
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@ -1781,8 +1781,8 @@ defm : TRUNC64m<truncstorei32, STLrri, STLrii, STLzri, ST1Bzii>;
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// Atomic loads
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multiclass ATMLDm<SDPatternOperator from,
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SDPatternOperator torri, SDPatternOperator torii,
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SDPatternOperator tozri, SDPatternOperator tozii> {
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RM torri, RM torii,
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RM tozri, RM tozii> {
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def : Pat<(from ADDRrri:$addr), (torri MEMrri:$addr)>;
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def : Pat<(from ADDRrii:$addr), (torii MEMrii:$addr)>;
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def : Pat<(from ADDRzri:$addr), (tozri MEMzri:$addr)>;
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@ -1794,9 +1794,9 @@ defm : ATMLDm<atomic_load_32, LDLZXrri, LDLZXrii, LDLZXzri, LDLZXzii>;
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defm : ATMLDm<atomic_load_64, LDrri, LDrii, LDzri, LDzii>;
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// Optimized atomic loads with sext
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multiclass SXATMLDm<SDPatternOperator from, Operand TY,
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SDPatternOperator torri, SDPatternOperator torii,
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SDPatternOperator tozri, SDPatternOperator tozii> {
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multiclass SXATMLDm<SDPatternOperator from, ValueType TY,
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RM torri, RM torii,
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RM tozri, RM tozii> {
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def : Pat<(i64 (sext_inreg (i64 (anyext (from ADDRrri:$addr))), TY)),
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(i2l (torri MEMrri:$addr))>;
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def : Pat<(i64 (sext_inreg (i64 (anyext (from ADDRrii:$addr))), TY)),
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@ -1807,8 +1807,8 @@ multiclass SXATMLDm<SDPatternOperator from, Operand TY,
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(i2l (tozii MEMzii:$addr))>;
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}
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multiclass SXATMLD32m<SDPatternOperator from,
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SDPatternOperator torri, SDPatternOperator torii,
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SDPatternOperator tozri, SDPatternOperator tozii> {
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RM torri, RM torii,
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RM tozri, RM tozii> {
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def : Pat<(i64 (sext (from ADDRrri:$addr))),
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(i2l (torri MEMrri:$addr))>;
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def : Pat<(i64 (sext (from ADDRrii:$addr))),
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@ -1824,9 +1824,9 @@ defm : SXATMLDm<atomic_load_16, i16, LD2BSXrri, LD2BSXrii, LD2BSXzri,
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defm : SXATMLD32m<atomic_load_32, LDLSXrri, LDLSXrii, LDLSXzri, LDLSXzii>;
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// Optimized atomic loads with zext
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multiclass ZXATMLDm<SDPatternOperator from, Operand VAL,
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SDPatternOperator torri, SDPatternOperator torii,
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SDPatternOperator tozri, SDPatternOperator tozii> {
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multiclass ZXATMLDm<SDPatternOperator from, int VAL,
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RM torri, RM torii,
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RM tozri, RM tozii> {
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def : Pat<(i64 (and (anyext (from ADDRrri:$addr)), VAL)),
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(i2l (torri MEMrri:$addr))>;
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def : Pat<(i64 (and (anyext (from ADDRrii:$addr)), VAL)),
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@ -1836,9 +1836,9 @@ multiclass ZXATMLDm<SDPatternOperator from, Operand VAL,
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def : Pat<(i64 (and (anyext (from ADDRzii:$addr)), VAL)),
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(i2l (tozii MEMzii:$addr))>;
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}
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multiclass ZXATMLD32m<SDPatternOperator from, Operand VAL,
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SDPatternOperator torri, SDPatternOperator torii,
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SDPatternOperator tozri, SDPatternOperator tozii> {
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multiclass ZXATMLD32m<SDPatternOperator from, int VAL,
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RM torri, RM torii,
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RM tozri, RM tozii> {
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def : Pat<(i64 (zext (from ADDRrri:$addr))),
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(i2l (torri MEMrri:$addr))>;
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def : Pat<(i64 (zext (from ADDRrii:$addr))),
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@ -1857,8 +1857,8 @@ defm : ZXATMLD32m<atomic_load_32, 0xFFFFFFFF, LDLZXrri, LDLZXrii, LDLZXzri,
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// Atomic stores
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multiclass ATMSTm<SDPatternOperator from, ValueType ty,
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SDPatternOperator torri, SDPatternOperator torii,
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SDPatternOperator tozri, SDPatternOperator tozii> {
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RM torri, RM torii,
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RM tozri, RM tozii> {
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def : Pat<(from ADDRrri:$addr, ty:$src), (torri MEMrri:$addr, $src)>;
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def : Pat<(from ADDRrii:$addr, ty:$src), (torii MEMrii:$addr, $src)>;
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def : Pat<(from ADDRzri:$addr, ty:$src), (tozri MEMzri:$addr, $src)>;
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@ -1872,10 +1872,10 @@ defm : ATMSTm<atomic_store_64, i64, STrri, STrii, STzri, STzii>;
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// Optimized atomic stores with truncate
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multiclass TRATMSTm<SDPatternOperator from,
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ValueType ty,
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SDPatternOperator torri,
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SDPatternOperator torii,
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SDPatternOperator tozri,
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SDPatternOperator tozii> {
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RM torri,
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RM torii,
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RM tozri,
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RM tozii> {
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def : Pat<(from ADDRrri:$addr, (i32 (trunc i64:$src))),
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(torri MEMrri:$addr, (EXTRACT_SUBREG $src, sub_i32))>;
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def : Pat<(from ADDRrii:$addr, (i32 (trunc i64:$src))),
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@ -1929,10 +1929,10 @@ def : Pat<(br bb:$addr), (BRCFLa bb:$addr)>;
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// brcc
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// integer brcc
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multiclass BRCCIm<ValueType ty, SDPatternOperator BrOpNode1,
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SDPatternOperator BrOpNode2,
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SDPatternOperator CmpOpNode1,
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SDPatternOperator CmpOpNode2> {
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multiclass BRCCIm<ValueType ty, CF BrOpNode1,
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CF BrOpNode2,
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RR CmpOpNode1,
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RR CmpOpNode2> {
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def : Pat<(brcc CCSIOp:$cond, ty:$l, simm7:$r, bb:$addr),
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(BrOpNode2 (icond2ccSwap $cond), (LO7 $r), $l, bb:$addr)>;
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def : Pat<(brcc CCSIOp:$cond, ty:$l, ty:$r, bb:$addr),
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@ -1947,8 +1947,7 @@ defm : BRCCIm<i32, BRCFWrr, BRCFWir, CMPUWrr, CMPUWir>;
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defm : BRCCIm<i64, BRCFLrr, BRCFLir, CMPULrr, CMPULir>;
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// floating point brcc
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multiclass BRCCFm<ValueType ty, SDPatternOperator BrOpNode1,
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SDPatternOperator BrOpNode2> {
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multiclass BRCCFm<ValueType ty, CF BrOpNode1, CF BrOpNode2> {
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def : Pat<(brcc cond:$cond, ty:$l, simm7fp:$r, bb:$addr),
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(BrOpNode2 (fcond2ccSwap $cond), (LO7FP $r), $l, bb:$addr)>;
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def : Pat<(brcc cond:$cond, ty:$l, ty:$r, bb:$addr),
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@ -16,7 +16,7 @@
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//===----------------------------------------------------------------------===//
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multiclass vbrd_elem32<ValueType v32, ValueType s32, SDPatternOperator ImmOp,
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SDNodeXForm ImmCast, SDNodeXForm SuperRegCast> {
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SDNodeXForm ImmCast, OutPatFrag SuperRegCast> {
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// VBRDil
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def : Pat<(v32 (vec_broadcast (s32 ImmOp:$sy), i32:$vl)),
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(VBRDil (ImmCast $sy), i32:$vl)>;
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@ -38,8 +38,8 @@ multiclass vbrd_elem64<ValueType v64, ValueType s64,
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}
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multiclass extract_insert_elem32<ValueType v32, ValueType s32,
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SDNodeXForm SubRegCast,
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SDNodeXForm SuperRegCast> {
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OutPatFrag SubRegCast,
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OutPatFrag SuperRegCast> {
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// LVSvi
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def: Pat<(s32 (extractelt v32:$vec, uimm7:$idx)),
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(SubRegCast (LVSvi v32:$vec, (ULO7 $idx)))>;
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@ -73,7 +73,7 @@ multiclass extract_insert_elem64<ValueType v64, ValueType s64> {
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multiclass patterns_elem32<ValueType v32, ValueType s32,
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SDPatternOperator ImmOp, SDNodeXForm ImmCast,
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SDNodeXForm SubRegCast, SDNodeXForm SuperRegCast> {
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OutPatFrag SubRegCast, OutPatFrag SuperRegCast> {
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defm : vbrd_elem32<v32, s32, ImmOp, ImmCast, SuperRegCast>;
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defm : extract_insert_elem32<v32, s32, SubRegCast, SuperRegCast>;
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}
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