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AMDGPU: WQM cleanups
- Add new TTI instruction checks - Don't use const for blocks that are mutated. - Checking isBranch and isTerminator should be redundant llvm-svn: 275252
This commit is contained in:
Matt Arsenault
parent
e9d18bfc80
commit
fafe4e3cc6
@ -350,6 +350,14 @@ public:
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return get(Opcode).TSFlags & SIInstrFlags::DPP;
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}
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static bool isScalarUnit(const MachineInstr &MI) {
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return MI.getDesc().TSFlags & (SIInstrFlags::SALU | SIInstrFlags::SMRD);
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}
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static bool usesVM_CNT(const MachineInstr &MI) {
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return MI.getDesc().TSFlags & SIInstrFlags::VM_CNT;
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}
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bool isVGPRCopy(const MachineInstr &MI) const {
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assert(MI.isCopy());
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unsigned Dest = MI.getOperand(0).getReg();
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@ -53,13 +53,10 @@
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#include "AMDGPUSubtarget.h"
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#include "SIInstrInfo.h"
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#include "SIMachineFunctionInfo.h"
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#include "llvm/CodeGen/MachineDominanceFrontier.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/IR/Constants.h"
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using namespace llvm;
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@ -84,12 +81,12 @@ struct BlockInfo {
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};
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struct WorkItem {
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const MachineBasicBlock *MBB = nullptr;
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const MachineInstr *MI = nullptr;
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MachineBasicBlock *MBB = nullptr;
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MachineInstr *MI = nullptr;
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WorkItem() {}
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WorkItem(const MachineBasicBlock *MBB) : MBB(MBB) {}
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WorkItem(const MachineInstr *MI) : MI(MI) {}
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WorkItem(MachineBasicBlock *MBB) : MBB(MBB) {}
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WorkItem(MachineInstr *MI) : MI(MI) {}
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};
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class SIWholeQuadMode : public MachineFunctionPass {
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@ -99,13 +96,13 @@ private:
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MachineRegisterInfo *MRI;
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DenseMap<const MachineInstr *, InstrInfo> Instructions;
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DenseMap<const MachineBasicBlock *, BlockInfo> Blocks;
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DenseMap<MachineBasicBlock *, BlockInfo> Blocks;
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SmallVector<const MachineInstr *, 2> ExecExports;
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SmallVector<MachineInstr *, 1> LiveMaskQueries;
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char scanInstructions(MachineFunction &MF, std::vector<WorkItem>& Worklist);
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void propagateInstruction(const MachineInstr &MI, std::vector<WorkItem>& Worklist);
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void propagateBlock(const MachineBasicBlock &MBB, std::vector<WorkItem>& Worklist);
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char scanInstructions(MachineFunction &MF, std::vector<WorkItem> &Worklist);
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void propagateInstruction(MachineInstr &MI, std::vector<WorkItem> &Worklist);
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void propagateBlock(MachineBasicBlock &MBB, std::vector<WorkItem> &Worklist);
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char analyzeFunction(MachineFunction &MF);
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void toExact(MachineBasicBlock &MBB, MachineBasicBlock::iterator Before,
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@ -138,10 +135,8 @@ public:
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char SIWholeQuadMode::ID = 0;
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INITIALIZE_PASS_BEGIN(SIWholeQuadMode, DEBUG_TYPE,
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"SI Whole Quad Mode", false, false)
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INITIALIZE_PASS_END(SIWholeQuadMode, DEBUG_TYPE,
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"SI Whole Quad Mode", false, false)
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INITIALIZE_PASS(SIWholeQuadMode, DEBUG_TYPE,
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"SI Whole Quad Mode", false, false)
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char &llvm::SIWholeQuadModeID = SIWholeQuadMode::ID;
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@ -166,8 +161,7 @@ char SIWholeQuadMode::scanInstructions(MachineFunction &MF,
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if (TII->isWQM(Opcode) || TII->isDS(Opcode)) {
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Flags = StateWQM;
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} else if (TII->get(Opcode).mayStore() &&
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(MI.getDesc().TSFlags & SIInstrFlags::VM_CNT)) {
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} else if (MI.mayStore() && TII->usesVM_CNT(MI)) {
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Flags = StateExact;
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} else {
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// Handle export instructions with the exec mask valid flag set
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@ -214,16 +208,15 @@ char SIWholeQuadMode::scanInstructions(MachineFunction &MF,
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return GlobalFlags;
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}
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void SIWholeQuadMode::propagateInstruction(const MachineInstr &MI,
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void SIWholeQuadMode::propagateInstruction(MachineInstr &MI,
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std::vector<WorkItem>& Worklist) {
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const MachineBasicBlock &MBB = *MI.getParent();
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MachineBasicBlock *MBB = MI.getParent();
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InstrInfo II = Instructions[&MI]; // take a copy to prevent dangling references
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BlockInfo &BI = Blocks[&MBB];
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BlockInfo &BI = Blocks[MBB];
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// Control flow-type instructions that are followed by WQM computations
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// must themselves be in WQM.
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if ((II.OutNeeds & StateWQM) && !(II.Needs & StateWQM) &&
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(MI.isBranch() || MI.isTerminator())) {
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if ((II.OutNeeds & StateWQM) && !(II.Needs & StateWQM) && MI.isTerminator()) {
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Instructions[&MI].Needs = StateWQM;
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II.Needs = StateWQM;
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}
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@ -232,11 +225,11 @@ void SIWholeQuadMode::propagateInstruction(const MachineInstr &MI,
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BI.Needs |= II.Needs;
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if ((BI.InNeeds | II.Needs) != BI.InNeeds) {
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BI.InNeeds |= II.Needs;
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Worklist.push_back(&MBB);
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Worklist.push_back(MBB);
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}
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// Propagate backwards within block
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if (const MachineInstr *PrevMI = MI.getPrevNode()) {
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if (MachineInstr *PrevMI = MI.getPrevNode()) {
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char InNeeds = II.Needs | II.OutNeeds;
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if (!PrevMI->isPHI()) {
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InstrInfo &PrevII = Instructions[PrevMI];
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@ -267,9 +260,8 @@ void SIWholeQuadMode::propagateInstruction(const MachineInstr &MI,
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if (!TargetRegisterInfo::isVirtualRegister(Use.getReg()))
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continue;
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for (const MachineOperand &Def : MRI->def_operands(Use.getReg())) {
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const MachineInstr *DefMI = Def.getParent();
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InstrInfo &DefII = Instructions[DefMI];
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for (MachineInstr &DefMI : MRI->def_instructions(Use.getReg())) {
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InstrInfo &DefII = Instructions[&DefMI];
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// Obviously skip if DefMI is already flagged as NeedWQM.
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//
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@ -281,18 +273,18 @@ void SIWholeQuadMode::propagateInstruction(const MachineInstr &MI,
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continue;
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DefII.Needs = StateWQM;
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Worklist.push_back(DefMI);
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Worklist.push_back(&DefMI);
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}
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}
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}
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void SIWholeQuadMode::propagateBlock(const MachineBasicBlock &MBB,
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void SIWholeQuadMode::propagateBlock(MachineBasicBlock &MBB,
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std::vector<WorkItem>& Worklist) {
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BlockInfo BI = Blocks[&MBB]; // take a copy to prevent dangling references
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BlockInfo BI = Blocks[&MBB]; // Make a copy to prevent dangling references.
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// Propagate through instructions
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if (!MBB.empty()) {
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const MachineInstr *LastMI = &*MBB.rbegin();
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MachineInstr *LastMI = &*MBB.rbegin();
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InstrInfo &LastII = Instructions[LastMI];
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if ((LastII.OutNeeds | BI.OutNeeds) != LastII.OutNeeds) {
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LastII.OutNeeds |= BI.OutNeeds;
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@ -301,7 +293,7 @@ void SIWholeQuadMode::propagateBlock(const MachineBasicBlock &MBB,
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}
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// Predecessor blocks must provide for our WQM/Exact needs.
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for (const MachineBasicBlock *Pred : MBB.predecessors()) {
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for (MachineBasicBlock *Pred : MBB.predecessors()) {
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BlockInfo &PredBI = Blocks[Pred];
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if ((PredBI.OutNeeds | BI.InNeeds) == PredBI.OutNeeds)
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continue;
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@ -311,9 +303,8 @@ void SIWholeQuadMode::propagateBlock(const MachineBasicBlock &MBB,
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Worklist.push_back(Pred);
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}
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// All successors must be prepared to accept the same set of WQM/Exact
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// data.
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for (const MachineBasicBlock *Succ : MBB.successors()) {
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// All successors must be prepared to accept the same set of WQM/Exact data.
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for (MachineBasicBlock *Succ : MBB.successors()) {
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BlockInfo &SuccBI = Blocks[Succ];
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if ((SuccBI.InNeeds | BI.OutNeeds) == SuccBI.InNeeds)
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continue;
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@ -394,8 +385,7 @@ void SIWholeQuadMode::processBlock(MachineBasicBlock &MBB, unsigned LiveMaskReg,
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++II;
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// Skip instructions that are not affected by EXEC
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if (MI.getDesc().TSFlags & (SIInstrFlags::SALU | SIInstrFlags::SMRD) &&
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!MI.isBranch() && !MI.isTerminator())
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if (TII->isScalarUnit(MI) && !MI.isTerminator())
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continue;
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// Generic instructions such as COPY will either disappear by register
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@ -421,7 +411,7 @@ void SIWholeQuadMode::processBlock(MachineBasicBlock &MBB, unsigned LiveMaskReg,
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// Make sure to switch to Exact mode before the end of the block when
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// Exact and only Exact is needed further downstream.
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if (OutNeeds == StateExact && (MI.isBranch() || MI.isTerminator())) {
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if (OutNeeds == StateExact && MI.isTerminator()) {
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assert(Needs == 0);
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Needs = StateExact;
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}
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@ -456,7 +446,7 @@ void SIWholeQuadMode::processBlock(MachineBasicBlock &MBB, unsigned LiveMaskReg,
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void SIWholeQuadMode::lowerLiveMaskQueries(unsigned LiveMaskReg) {
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for (MachineInstr *MI : LiveMaskQueries) {
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DebugLoc DL = MI->getDebugLoc();
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const DebugLoc &DL = MI->getDebugLoc();
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unsigned Dest = MI->getOperand(0).getReg();
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BuildMI(*MI->getParent(), MI, DL, TII->get(AMDGPU::COPY), Dest)
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.addReg(LiveMaskReg);
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@ -512,9 +502,8 @@ bool SIWholeQuadMode::runOnMachineFunction(MachineFunction &MF) {
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lowerLiveMaskQueries(LiveMaskReg);
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// Handle the general case
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for (const auto &BII : Blocks)
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processBlock(const_cast<MachineBasicBlock &>(*BII.first), LiveMaskReg,
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BII.first == &*MF.begin());
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for (auto BII : Blocks)
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processBlock(*BII.first, LiveMaskReg, BII.first == &*MF.begin());
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return true;
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}
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