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[AArch64][GlobalISel] Change store value type from p0 -> s64 to import patterns
Similar to the G_PTR_ADD + G_LOAD twiddling we do in `preISelLower`. The imported patterns expect scalars only, so they can't handle things like ``` G_STORE %ptr1, %ptr2 ``` To get around this, use s64 instead. (This probably makes a good portion of the manual selection code for G_STORE dead.) This is a 0.2% geomean code size improvement on CTMark at -Os. (Best is consumer-typeset @ -0.7%) Differential Revision: https://reviews.llvm.org/D95908
This commit is contained in:
Jessica Paquette
parent
1c6798fa1f
commit
fb07198b1d
@ -1915,8 +1915,22 @@ bool AArch64InstructionSelector::preISelLower(MachineInstr &I) {
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}
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return true;
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}
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case TargetOpcode::G_STORE:
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return contractCrossBankCopyIntoStore(I, MRI);
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case TargetOpcode::G_STORE: {
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bool Changed = contractCrossBankCopyIntoStore(I, MRI);
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MachineOperand &SrcOp = I.getOperand(0);
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if (MRI.getType(SrcOp.getReg()).isPointer()) {
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// Allow matching with imported patterns for stores of pointers. Unlike
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// G_LOAD/G_PTR_ADD, we may not have selected all users. So, emit a copy
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// and constrain.
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MachineIRBuilder MIB(I);
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auto Copy = MIB.buildCopy(LLT::scalar(64), SrcOp);
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Register NewSrc = Copy.getReg(0);
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SrcOp.setReg(NewSrc);
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RBI.constrainGenericRegister(NewSrc, AArch64::GPR64RegClass, MRI);
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Changed = true;
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}
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return Changed;
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}
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case TargetOpcode::G_PTR_ADD:
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return convertPtrAddToAdd(I, MRI);
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case TargetOpcode::G_LOAD: {
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@ -246,8 +246,9 @@ body: |
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liveins: $x0
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; CHECK-LABEL: name: store_fi_s64_gpr
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; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
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; CHECK: STRXui [[COPY]], %stack.0.ptr0, 0 :: (store 8)
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; CHECK: [[COPY:%[0-9]+]]:gpr64all = COPY $x0
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; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY [[COPY]]
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; CHECK: STRXui [[COPY1]], %stack.0.ptr0, 0 :: (store 8)
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%0(p0) = COPY $x0
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%1(p0) = G_FRAME_INDEX %stack.0.ptr0
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G_STORE %0, %1 :: (store 8)
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@ -613,9 +614,10 @@ body: |
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liveins: $x0
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; CHECK-LABEL: name: store_adrp_add_low
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; CHECK: liveins: $x0
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; CHECK: %copy:gpr64 = COPY $x0
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; CHECK: %copy:gpr64all = COPY $x0
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; CHECK: %adrp:gpr64common = ADRP target-flags(aarch64-page) @x
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; CHECK: STRXui %copy, %adrp, target-flags(aarch64-pageoff, aarch64-nc) @x :: (store 8 into @x)
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; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %copy
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; CHECK: STRXui [[COPY]], %adrp, target-flags(aarch64-pageoff, aarch64-nc) @x :: (store 8 into @x)
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%copy:gpr(p0) = COPY $x0
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%adrp:gpr64(p0) = ADRP target-flags(aarch64-page) @x
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%add_low:gpr(p0) = G_ADD_LOW %adrp(p0), target-flags(aarch64-pageoff, aarch64-nc) @x
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@ -59,8 +59,9 @@ body: |
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; CHECK-LABEL: name: check_sext_not_lost
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; CHECK: liveins: $x0
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; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
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; CHECK: STRXui [[COPY]], %stack.0.ptr.addr, 0 :: (store 8 into %ir.ptr.addr)
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; CHECK: [[COPY:%[0-9]+]]:gpr64all = COPY $x0
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; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY [[COPY]]
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; CHECK: STRXui [[COPY1]], %stack.0.ptr.addr, 0 :: (store 8 into %ir.ptr.addr)
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; CHECK: [[LDRXui:%[0-9]+]]:gpr64common = LDRXui %stack.0.ptr.addr, 0 :: (dereferenceable load 8 from %ir.ptr.addr)
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; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) @x
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; CHECK: [[LDRWui:%[0-9]+]]:gpr32common = LDRWui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) @x :: (dereferenceable load 4 from @x)
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@ -3,12 +3,14 @@
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--- |
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define void @strxrox(i64* %addr) { ret void }
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define void @strxrox_p0(i64* %addr) { ret void }
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define void @strdrox(i64* %addr) { ret void }
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define void @strwrox(i64* %addr) { ret void }
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define void @strsrox(i64* %addr) { ret void }
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define void @strhrox(i64* %addr) { ret void }
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define void @strqrox(i64* %addr) { ret void }
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define void @shl(i64* %addr) { ret void }
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define void @shl_p0(i64* %addr) { ret void }
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...
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---
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@ -34,6 +36,29 @@ body: |
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G_STORE %3, %ptr :: (store 8 into %ir.addr)
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...
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---
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name: strxrox_p0
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $x0, $x1, $x2
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; CHECK-LABEL: name: strxrox_p0
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; CHECK: liveins: $x0, $x1, $x2
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; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
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; CHECK: [[COPY2:%[0-9]+]]:gpr64all = COPY $x2
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; CHECK: [[COPY3:%[0-9]+]]:gpr64 = COPY [[COPY2]]
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; CHECK: STRXroX [[COPY3]], [[COPY]], [[COPY1]], 0, 0 :: (store 8 into %ir.addr)
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%0:gpr(p0) = COPY $x0
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%1:gpr(s64) = COPY $x1
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%ptr:gpr(p0) = G_PTR_ADD %0, %1
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%3:gpr(p0) = COPY $x2
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G_STORE %3, %ptr :: (store 8 into %ir.addr)
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...
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---
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name: strdrox
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alignment: 4
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legalized: true
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@ -166,3 +191,28 @@ body: |
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%ptr:gpr(p0) = G_PTR_ADD %3, %2
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%4:gpr(s64) = COPY $x2
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G_STORE %4, %ptr :: (store 8 into %ir.addr)
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...
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---
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name: shl_p0
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $x0, $x1, $x2
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; CHECK-LABEL: name: shl_p0
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; CHECK: liveins: $x0, $x1, $x2
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; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
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; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x1
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; CHECK: [[COPY2:%[0-9]+]]:gpr64all = COPY $x2
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; CHECK: [[COPY3:%[0-9]+]]:gpr64 = COPY [[COPY2]]
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; CHECK: STRXroX [[COPY3]], [[COPY1]], [[COPY]], 0, 1 :: (store 8 into %ir.addr)
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%0:gpr(s64) = COPY $x0
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%1:gpr(s64) = G_CONSTANT i64 3
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%2:gpr(s64) = G_SHL %0, %1(s64)
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%3:gpr(p0) = COPY $x1
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%ptr:gpr(p0) = G_PTR_ADD %3, %2
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%4:gpr(p0) = COPY $x2
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G_STORE %4, %ptr :: (store 8 into %ir.addr)
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@ -50,3 +50,29 @@ body: |
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%dst:gpr(s64) = COPY $x2
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G_STORE %dst, %ptr :: (store 8)
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...
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---
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name: strxrow_p0
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $x0, $x1, $x2
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; CHECK-LABEL: name: strxrow_p0
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; CHECK: liveins: $x0, $x1, $x2
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; CHECK: %base:gpr64sp = COPY $x0
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; CHECK: %foo:gpr32 = COPY $w1
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; CHECK: %dst:gpr64all = COPY $x2
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; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %dst
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; CHECK: STRXroW [[COPY]], %base, %foo, 1, 1 :: (store 8)
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%base:gpr(p0) = COPY $x0
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%foo:gpr(s32) = COPY $w1
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%ext:gpr(s64) = G_SEXT %foo(s32)
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%c:gpr(s64) = G_CONSTANT i64 3
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%offset:gpr(s64) = G_SHL %ext, %c
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%ptr:gpr(p0) = G_PTR_ADD %base, %offset(s64)
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%dst:gpr(p0) = COPY $x2
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G_STORE %dst, %ptr :: (store 8)
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...
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