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[ARM] Extra test for gep immediate costs. NFC
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David Green
parent
93f53bac4a
commit
fb194b2e47
134
test/CodeGen/ARM/gep-imm.ll
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134
test/CodeGen/ARM/gep-imm.ll
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@ -0,0 +1,134 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=thumbv6m-none-eabi < %s | FileCheck %s --check-prefix=CHECKV6M
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; RUN: llc -mtriple=thumbv7m-none-eabi < %s | FileCheck %s --check-prefix=CHECKV7M
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; RUN: llc -mtriple=thumbv7a-none-eabi < %s | FileCheck %s --check-prefix=CHECKV7A
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define void @small(i32 %a, i32 %b, i32 *%c, i32* %d) {
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; CHECKV6M-LABEL: small:
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; CHECKV6M: @ %bb.0: @ %entry
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; CHECKV6M-NEXT: str r1, [r3, #120]
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; CHECKV6M-NEXT: str r0, [r3, #80]
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; CHECKV6M-NEXT: str r0, [r2, #80]
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; CHECKV6M-NEXT: bx lr
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;
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; CHECKV7M-LABEL: small:
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; CHECKV7M: @ %bb.0: @ %entry
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; CHECKV7M-NEXT: str r1, [r3, #120]
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; CHECKV7M-NEXT: str r0, [r3, #80]
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; CHECKV7M-NEXT: str r0, [r2, #80]
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; CHECKV7M-NEXT: bx lr
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;
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; CHECKV7A-LABEL: small:
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; CHECKV7A: @ %bb.0: @ %entry
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; CHECKV7A-NEXT: str r1, [r3, #120]
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; CHECKV7A-NEXT: str r0, [r3, #80]
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; CHECKV7A-NEXT: str r0, [r2, #80]
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; CHECKV7A-NEXT: bx lr
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entry:
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%arrayidx = getelementptr inbounds i32, i32* %d, i32 20
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store i32 %a, i32* %arrayidx, align 4
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%arrayidx1 = getelementptr inbounds i32, i32* %d, i32 30
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store i32 %b, i32* %arrayidx1, align 4
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%arrayidx2 = getelementptr inbounds i32, i32* %c, i32 20
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store i32 %a, i32* %arrayidx2, align 4
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ret void
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}
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define void @large(i32 %a, i32 %b, i32 *%c, i32* %d) {
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; CHECKV6M-LABEL: large:
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; CHECKV6M: @ %bb.0: @ %entry
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; CHECKV6M-NEXT: .save {r4, r5, r7, lr}
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; CHECKV6M-NEXT: push {r4, r5, r7, lr}
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; CHECKV6M-NEXT: movs r4, #125
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; CHECKV6M-NEXT: lsls r4, r4, #4
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; CHECKV6M-NEXT: lsls r4, r4, #2
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; CHECKV6M-NEXT: str r0, [r3, r4]
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; CHECKV6M-NEXT: ldr r5, .LCPI1_0
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; CHECKV6M-NEXT: str r1, [r3, r5]
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; CHECKV6M-NEXT: str r0, [r2, r4]
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; CHECKV6M-NEXT: pop {r4, r5, r7, pc}
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; CHECKV6M-NEXT: .p2align 2
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; CHECKV6M-NEXT: @ %bb.1:
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; CHECKV6M-NEXT: .LCPI1_0:
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; CHECKV6M-NEXT: .long 12000 @ 0x2ee0
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;
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; CHECKV7M-LABEL: large:
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; CHECKV7M: @ %bb.0: @ %entry
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; CHECKV7M-NEXT: mov.w r12, #8000
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; CHECKV7M-NEXT: str.w r0, [r3, r12]
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; CHECKV7M-NEXT: add.w r3, r3, #8000
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; CHECKV7M-NEXT: str.w r1, [r3, #4000]
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; CHECKV7M-NEXT: str.w r0, [r2, r12]
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; CHECKV7M-NEXT: bx lr
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;
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; CHECKV7A-LABEL: large:
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; CHECKV7A: @ %bb.0: @ %entry
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; CHECKV7A-NEXT: mov.w r12, #8000
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; CHECKV7A-NEXT: str.w r0, [r3, r12]
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; CHECKV7A-NEXT: add.w r3, r3, #8000
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; CHECKV7A-NEXT: str.w r1, [r3, #4000]
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; CHECKV7A-NEXT: str.w r0, [r2, r12]
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; CHECKV7A-NEXT: bx lr
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entry:
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%arrayidx = getelementptr inbounds i32, i32* %d, i32 2000
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store i32 %a, i32* %arrayidx, align 4
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%arrayidx1 = getelementptr inbounds i32, i32* %d, i32 3000
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store i32 %b, i32* %arrayidx1, align 4
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%arrayidx2 = getelementptr inbounds i32, i32* %c, i32 2000
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store i32 %a, i32* %arrayidx2, align 4
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ret void
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}
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define void @huge(i32 %a, i32 %b, i32 *%c, i32* %d) {
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; CHECKV6M-LABEL: huge:
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; CHECKV6M: @ %bb.0: @ %entry
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; CHECKV6M-NEXT: .save {r4, r5, r7, lr}
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; CHECKV6M-NEXT: push {r4, r5, r7, lr}
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; CHECKV6M-NEXT: ldr r4, .LCPI2_0
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; CHECKV6M-NEXT: lsls r4, r4, #2
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; CHECKV6M-NEXT: str r0, [r3, r4]
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; CHECKV6M-NEXT: ldr r5, .LCPI2_1
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; CHECKV6M-NEXT: str r1, [r3, r5]
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; CHECKV6M-NEXT: str r0, [r2, r4]
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; CHECKV6M-NEXT: pop {r4, r5, r7, pc}
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; CHECKV6M-NEXT: .p2align 2
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; CHECKV6M-NEXT: @ %bb.1:
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; CHECKV6M-NEXT: .LCPI2_0:
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; CHECKV6M-NEXT: .long 200000 @ 0x30d40
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; CHECKV6M-NEXT: .LCPI2_1:
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; CHECKV6M-NEXT: .long 1200000 @ 0x124f80
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;
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; CHECKV7M-LABEL: huge:
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; CHECKV7M: @ %bb.0: @ %entry
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; CHECKV7M-NEXT: .save {r7, lr}
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; CHECKV7M-NEXT: push {r7, lr}
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; CHECKV7M-NEXT: movw r12, #3392
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; CHECKV7M-NEXT: movw lr, #20352
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; CHECKV7M-NEXT: movt r12, #3
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; CHECKV7M-NEXT: movt lr, #18
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; CHECKV7M-NEXT: str.w r0, [r3, r12, lsl #2]
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; CHECKV7M-NEXT: str.w r1, [r3, lr]
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; CHECKV7M-NEXT: str.w r0, [r2, r12, lsl #2]
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; CHECKV7M-NEXT: pop {r7, pc}
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;
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; CHECKV7A-LABEL: huge:
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; CHECKV7A: @ %bb.0: @ %entry
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; CHECKV7A-NEXT: .save {r7, lr}
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; CHECKV7A-NEXT: push {r7, lr}
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; CHECKV7A-NEXT: movw r12, #3392
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; CHECKV7A-NEXT: movw lr, #20352
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; CHECKV7A-NEXT: movt r12, #3
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; CHECKV7A-NEXT: movt lr, #18
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; CHECKV7A-NEXT: str.w r0, [r3, r12, lsl #2]
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; CHECKV7A-NEXT: str.w r1, [r3, lr]
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; CHECKV7A-NEXT: str.w r0, [r2, r12, lsl #2]
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; CHECKV7A-NEXT: pop {r7, pc}
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entry:
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%arrayidx = getelementptr inbounds i32, i32* %d, i32 200000
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store i32 %a, i32* %arrayidx, align 4
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%arrayidx1 = getelementptr inbounds i32, i32* %d, i32 300000
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store i32 %b, i32* %arrayidx1, align 4
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%arrayidx2 = getelementptr inbounds i32, i32* %c, i32 200000
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store i32 %a, i32* %arrayidx2, align 4
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ret void
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}
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