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AMDGPU: Remove hasPostISelHook from most instructions

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Since this is only needed for VOP3 and a few other special
case instructions, stop setting it on everything.

llvm-svn: 248657
This commit is contained in:
Matt Arsenault 2015-09-26 05:06:48 +00:00
parent 16b445f6b4
commit fb1ff93ba4
2 changed files with 19 additions and 12 deletions
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8
lib/Target/AMDGPU/SIInstrFormats.td
View File

@ -69,9 +69,6 @@ class InstSI <dag outs, dag ins, string asm, list<dag> pattern> :
let TSFlags{20} = WQM;
let TSFlags{21} = VGPRSpill;
// Most instructions require adjustments after selection to satisfy
// operand requirements.
let hasPostISelHook = 1;
let SchedRW = [Write32Bit];
}
@ -137,6 +134,11 @@ class VOP3Common <dag outs, dag ins, string asm, list<dag> pattern> :
let isCodeGenOnly = 0;
int Size = 8;
// Because SGPRs may be allowed if there are multiple operands, we
// need a post-isel hook to insert copies in order to avoid
// violating constant bus requirements.
let hasPostISelHook = 1;
}
} // End Uses = [EXEC]

23
lib/Target/AMDGPU/SIInstrInfo.td
View File

@ -2061,12 +2061,14 @@ multiclass DS_1A1D_RET <bits<8> op, string opName, RegisterClass rc,
dag ins = (ins VGPR_32:$addr, rc:$data0, ds_offset:$offset, gds:$gds),
string asm = opName#" $vdst, $addr, $data0"#"$offset$gds"> {
def "" : DS_Pseudo <opName, outs, ins, []>,
AtomicNoRet<noRetOp, 1>;
let hasPostISelHook = 1 in {
def "" : DS_Pseudo <opName, outs, ins, []>,
AtomicNoRet<noRetOp, 1>;
let data1 = 0 in {
def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
let data1 = 0 in {
def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
}
}
}
@ -2075,11 +2077,13 @@ multiclass DS_1A2D_RET_m <bits<8> op, string opName, RegisterClass rc,
dag outs = (outs rc:$vdst),
string asm = opName#" $vdst, $addr, $data0, $data1"#"$offset"#"$gds"> {
def "" : DS_Pseudo <opName, outs, ins, []>,
AtomicNoRet<noRetOp, 1>;
let hasPostISelHook = 1 in {
def "" : DS_Pseudo <opName, outs, ins, []>,
AtomicNoRet<noRetOp, 1>;
def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
}
}
multiclass DS_1A2D_RET <bits<8> op, string asm, RegisterClass rc,
@ -2561,6 +2565,7 @@ multiclass FLAT_ATOMIC <bits<7> op, string name, RegisterClass vdst_rc,
name#" $vdst, $addr, $data glc"#"$slc"#"$tfe", []>,
AtomicNoRet <NAME, 1> {
let glc = 1;
let hasPostISelHook = 1;
}
}
}