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[Hexagon] Minimize number of repeated constant extenders
Each constant extender requires an extra instruction, which adds to the code size and also reduces the number of available slots in an instruction packet. In most cases, the value of a repeated constant extender could be loaded into a register, and the instructions using the extender could be replaced with their counterparts that use that register instead. This patch adds a pass that tries to reduce the number of constant extenders, including extenders which differ only in an immediate offset known at compile time, e.g. @global and @global+12. llvm-svn: 315735
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@ -20,6 +20,7 @@ add_llvm_target(HexagonCodeGen
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HexagonBranchRelaxation.cpp
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HexagonCFGOptimizer.cpp
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HexagonCommonGEP.cpp
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HexagonConstExtenders.cpp
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HexagonConstPropagation.cpp
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HexagonCopyToCombine.cpp
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HexagonEarlyIfConv.cpp
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1854
lib/Target/Hexagon/HexagonConstExtenders.cpp
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1854
lib/Target/Hexagon/HexagonConstExtenders.cpp
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File diff suppressed because it is too large
Load Diff
@ -28,6 +28,9 @@
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using namespace llvm;
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static cl::opt<bool> EnableCExtOpt("hexagon-cext", cl::Hidden, cl::ZeroOrMore,
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cl::init(true), cl::desc("Enable Hexagon constant-extender optimization"));
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static cl::opt<bool> EnableRDFOpt("rdf-opt", cl::Hidden, cl::ZeroOrMore,
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cl::init(true), cl::desc("Enable RDF-based optimizations"));
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@ -119,6 +122,7 @@ SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler",
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namespace llvm {
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extern char &HexagonExpandCondsetsID;
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void initializeHexagonConstExtendersPass(PassRegistry&);
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void initializeHexagonEarlyIfConversionPass(PassRegistry&);
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void initializeHexagonExpandCondsetsPass(PassRegistry&);
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void initializeHexagonGenMuxPass(PassRegistry&);
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@ -135,6 +139,7 @@ namespace llvm {
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FunctionPass *createHexagonCallFrameInformation();
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FunctionPass *createHexagonCFGOptimizer();
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FunctionPass *createHexagonCommonGEP();
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FunctionPass *createHexagonConstExtenders();
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FunctionPass *createHexagonConstPropagationPass();
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FunctionPass *createHexagonCopyToCombine();
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FunctionPass *createHexagonEarlyIfConversion();
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@ -176,6 +181,7 @@ extern "C" void LLVMInitializeHexagonTarget() {
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RegisterTargetMachine<HexagonTargetMachine> X(getTheHexagonTarget());
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PassRegistry &PR = *PassRegistry::getPassRegistry();
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initializeHexagonConstExtendersPass(PR);
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initializeHexagonEarlyIfConversionPass(PR);
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initializeHexagonGenMuxPass(PR);
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initializeHexagonLoopIdiomRecognizePass(PR);
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@ -340,6 +346,8 @@ bool HexagonPassConfig::addInstSelector() {
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void HexagonPassConfig::addPreRegAlloc() {
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if (getOptLevel() != CodeGenOpt::None) {
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if (EnableCExtOpt)
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addPass(createHexagonConstExtenders());
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if (EnableExpandCondsets)
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insertPass(&RegisterCoalescerID, &HexagonExpandCondsetsID);
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if (!DisableStoreWidening)
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75
test/CodeGen/Hexagon/cext-opt-basic.mir
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75
test/CodeGen/Hexagon/cext-opt-basic.mir
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@ -0,0 +1,75 @@
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# RUN: llc -march=hexagon -run-pass hexagon-cext-opt -hexagon-cext-threshold=3 %s -o - | FileCheck %s
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--- |
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define void @test0() { ret void }
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define void @test1() { ret void }
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define void @test2() { ret void }
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@global_address = global [1024 x i32] zeroinitializer, align 8
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...
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# CHECK-LABEL: name: test0
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# CHECK: [[B:%[0-9]+]] = A2_tfrsi @global_address
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# CHECK: L2_loadri_io [[B]], 0
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# CHECK: L2_loadri_io [[B]], 4
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# CHECK: L2_loadri_io [[B]], 8
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---
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name: test0
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registers:
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- { id: 0, class: intregs }
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- { id: 1, class: intregs }
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- { id: 2, class: intregs }
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body: |
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bb.0:
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%0 = PS_loadriabs @global_address
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%1 = PS_loadriabs @global_address+4
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%2 = PS_loadriabs @global_address+8
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...
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# CHECK-LABEL: name: test1
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# CHECK: [[C:%[0-9]+]] = COPY %r0
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# CHECK: [[B:%[0-9]+]] = A2_addi [[C]], @global_address
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# CHECK: L2_loadri_io [[B]], 0
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# CHECK: L2_loadri_io [[B]], 4
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# CHECK: L2_loadri_io [[B]], 8
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---
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name: test1
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registers:
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- { id: 0, class: intregs }
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- { id: 1, class: intregs }
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- { id: 2, class: intregs }
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- { id: 3, class: intregs }
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body: |
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bb.0:
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liveins: %r0
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%0 = COPY %r0
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%1 = L4_loadri_ur %0, 0, @global_address
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%2 = L4_loadri_ur %0, 0, @global_address+4
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%3 = L4_loadri_ur %0, 0, @global_address+8
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...
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# CHECK-LABEL: name: test2
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# CHECK: [[C:%[0-9]+]] = COPY %r0
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# CHECK: [[B:%[0-9]+]] = A2_tfrsi @global_address + 4
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# CHECK: [[T0:%[0-9]+]] = A2_addi [[B]], -4
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# CHECK: %r0 = COPY [[T0]]
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# CHECK: [[T1:%[0-9]+]] = A2_addi [[B]], -2
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# CHECK: %r1 = COPY [[T1]]
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# CHECK: L4_loadri_rr [[B]], [[C]], 0
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---
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name: test2
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registers:
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- { id: 0, class: intregs }
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- { id: 1, class: intregs }
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- { id: 2, class: intregs }
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- { id: 3, class: intregs }
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body: |
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bb.0:
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liveins: %r0
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%0 = COPY %r0
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%1 = A2_tfrsi @global_address
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%r0 = COPY %1
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%2 = A2_tfrsi @global_address+2
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%r1 = COPY %2
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%3 = L4_loadri_ur %0, 0, @global_address+4
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...
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@ -1,4 +1,4 @@
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; RUN: llc -march=hexagon < %s | FileCheck %s
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; RUN: llc -march=hexagon -hexagon-cext=0 < %s | FileCheck %s
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@i65_l = external global i65
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@i65_s = external global i65
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