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R600: Emit config values in register / value pairs

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Reviewed-by: Vincent Lejeune <vljn@ovi.com>
Tested-By: Aaron Watry <awatry@gmail.com>
llvm-svn: 181228
This commit is contained in:
Tom Stellard 2013-05-06 17:50:51 +00:00
parent c179ac43fa
commit fb8e73f3af
3 changed files with 58 additions and 5 deletions
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32
lib/Target/R600/AMDGPUAsmPrinter.cpp
View File

@ -22,6 +22,7 @@
#include "SIDefines.h"
#include "SIMachineFunctionInfo.h"
#include "SIRegisterInfo.h"
#include "R600Defines.h"
#include "R600MachineFunctionInfo.h"
#include "R600RegisterInfo.h"
#include "llvm/MC/MCContext.h"
@ -78,6 +79,7 @@ void AMDGPUAsmPrinter::EmitProgramInfoR600(MachineFunction &MF) {
const R600RegisterInfo * RI =
static_cast<const R600RegisterInfo*>(TM.getRegisterInfo());
R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
const AMDGPUSubtarget &STM = TM.getSubtarget<AMDGPUSubtarget>();
for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end();
BB != BB_E; ++BB) {
@ -101,9 +103,33 @@ void AMDGPUAsmPrinter::EmitProgramInfoR600(MachineFunction &MF) {
}
}
}
OutStreamer.EmitIntValue(MaxGPR + 1, 4);
OutStreamer.EmitIntValue(MFI->StackSize, 4);
OutStreamer.EmitIntValue(killPixel, 4);
unsigned RsrcReg;
if (STM.device()->getGeneration() >= AMDGPUDeviceInfo::HD5XXX) {
// Evergreen / Northern Islands
switch (MFI->ShaderType) {
default: // Fall through
case ShaderType::COMPUTE: RsrcReg = R_0288D4_SQ_PGM_RESOURCES_LS; break;
case ShaderType::GEOMETRY: RsrcReg = R_028878_SQ_PGM_RESOURCES_GS; break;
case ShaderType::PIXEL: RsrcReg = R_028844_SQ_PGM_RESOURCES_PS; break;
case ShaderType::VERTEX: RsrcReg = R_028860_SQ_PGM_RESOURCES_VS; break;
}
} else {
// R600 / R700
switch (MFI->ShaderType) {
default: // Fall through
case ShaderType::GEOMETRY: // Fall through
case ShaderType::COMPUTE: // Fall through
case ShaderType::VERTEX: RsrcReg = R_028868_SQ_PGM_RESOURCES_VS; break;
case ShaderType::PIXEL: RsrcReg = R_028850_SQ_PGM_RESOURCES_PS; break;
}
}
OutStreamer.EmitIntValue(RsrcReg, 4);
OutStreamer.EmitIntValue(S_NUM_GPRS(MaxGPR + 1) |
S_STACK_SIZE(MFI->StackSize), 4);
OutStreamer.EmitIntValue(R_02880C_DB_SHADER_CONTROL, 4);
OutStreamer.EmitIntValue(S_02880C_KILL_ENABLE(killPixel), 4);
}
void AMDGPUAsmPrinter::EmitProgramInfoSI(MachineFunction &MF) {

26
lib/Target/R600/R600Defines.h
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@ -97,4 +97,30 @@ namespace R600Operands {
}
//===----------------------------------------------------------------------===//
// Config register definitions
//===----------------------------------------------------------------------===//
#define R_02880C_DB_SHADER_CONTROL 0x02880C
#define S_02880C_KILL_ENABLE(x) (((x) & 0x1) << 6)
// These fields are the same for all shader types and families.
#define S_NUM_GPRS(x) (((x) & 0xFF) << 0)
#define S_STACK_SIZE(x) (((x) & 0xFF) << 8)
//===----------------------------------------------------------------------===//
// R600, R700 Registers
//===----------------------------------------------------------------------===//
#define R_028850_SQ_PGM_RESOURCES_PS 0x028850
#define R_028868_SQ_PGM_RESOURCES_VS 0x028868
//===----------------------------------------------------------------------===//
// Evergreen, Northern Islands Registers
//===----------------------------------------------------------------------===//
#define R_028844_SQ_PGM_RESOURCES_PS 0x028844
#define R_028860_SQ_PGM_RESOURCES_VS 0x028860
#define R_028878_SQ_PGM_RESOURCES_GS 0x028878
#define R_0288D4_SQ_PGM_RESOURCES_LS 0x0288d4
#endif // R600DEFINES_H_

5
test/CodeGen/R600/elf.r600.ll
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@ -5,8 +5,9 @@
; ELF-CHECK: Name: .AMDGPU.config
; CONFIG-CHECK: .section .AMDGPU.config
; CONFIG-CHECK-NEXT: .long 2
; CONFIG-CHECK-NEXT: .long 1
; CONFIG-CHECK-NEXT: .long 166100
; CONFIG-CHECK-NEXT: .long 258
; CONFIG-CHECK-NEXT: .long 165900
; CONFIG-CHECK-NEXT: .long 0
define void @test(float addrspace(1)* %out, i32 %p) {
%i = add i32 %p, 2