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[X86] Add a DAG combine for turning *_extend_vector_inreg+load into an appropriate extload if the load isn't volatile.
Remove the corresponding isel patterns that did the same thing without checking for volatile. This fixes another variation of PR42079 llvm-svn: 364977
This commit is contained in:
Craig Topper
parent
b7970f9e15
commit
fba19d76da
@ -1876,6 +1876,7 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
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setTargetDAGCombine(ISD::SIGN_EXTEND);
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setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
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setTargetDAGCombine(ISD::ANY_EXTEND_VECTOR_INREG);
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setTargetDAGCombine(ISD::SIGN_EXTEND_VECTOR_INREG);
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setTargetDAGCombine(ISD::ZERO_EXTEND_VECTOR_INREG);
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setTargetDAGCombine(ISD::SINT_TO_FP);
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setTargetDAGCombine(ISD::UINT_TO_FP);
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@ -43914,16 +43915,35 @@ static SDValue combinePMULDQ(SDNode *N, SelectionDAG &DAG,
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}
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static SDValue combineExtInVec(SDNode *N, SelectionDAG &DAG,
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TargetLowering::DAGCombinerInfo &DCI,
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const X86Subtarget &Subtarget) {
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EVT VT = N->getValueType(0);
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SDValue In = N->getOperand(0);
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// Try to merge vector loads and extend_inreg to an extload.
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if (!DCI.isBeforeLegalizeOps() && ISD::isNormalLoad(In.getNode()) &&
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In.hasOneUse()) {
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auto *Ld = cast<LoadSDNode>(In);
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if (!Ld->isVolatile()) {
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MVT SVT = In.getSimpleValueType().getVectorElementType();
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ISD::LoadExtType Ext = N->getOpcode() == ISD::SIGN_EXTEND_VECTOR_INREG ? ISD::SEXTLOAD : ISD::ZEXTLOAD;
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EVT MemVT = EVT::getVectorVT(*DAG.getContext(), SVT,
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VT.getVectorNumElements());
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SDValue Load =
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DAG.getExtLoad(Ext, SDLoc(N), VT, Ld->getChain(), Ld->getBasePtr(),
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Ld->getPointerInfo(), MemVT, Ld->getAlignment(),
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Ld->getMemOperand()->getFlags());
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DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
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return Load;
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}
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}
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// Disabling for widening legalization for now. We can enable if we find a
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// case that needs it. Otherwise it can be deleted when we switch to
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// widening legalization.
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if (ExperimentalVectorWideningLegalization)
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return SDValue();
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EVT VT = N->getValueType(0);
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SDValue In = N->getOperand(0);
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// Combine (ext_invec (ext_invec X)) -> (ext_invec X)
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const TargetLowering &TLI = DAG.getTargetLoweringInfo();
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if (In.getOpcode() == N->getOpcode() &&
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@ -43932,7 +43952,7 @@ static SDValue combineExtInVec(SDNode *N, SelectionDAG &DAG,
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// Attempt to combine as a shuffle.
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// TODO: SSE41 support
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if (Subtarget.hasAVX()) {
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if (Subtarget.hasAVX() && N->getOpcode() != ISD::SIGN_EXTEND_VECTOR_INREG) {
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SDValue Op(N, 0);
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if (TLI.isTypeLegal(VT) && TLI.isTypeLegal(In.getValueType()))
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if (SDValue Res = combineX86ShufflesRecursively(Op, DAG, Subtarget))
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@ -44010,7 +44030,9 @@ SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
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case ISD::SIGN_EXTEND: return combineSext(N, DAG, DCI, Subtarget);
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case ISD::SIGN_EXTEND_INREG: return combineSignExtendInReg(N, DAG, Subtarget);
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case ISD::ANY_EXTEND_VECTOR_INREG:
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case ISD::ZERO_EXTEND_VECTOR_INREG: return combineExtInVec(N, DAG, Subtarget);
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case ISD::SIGN_EXTEND_VECTOR_INREG:
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case ISD::ZERO_EXTEND_VECTOR_INREG: return combineExtInVec(N, DAG, DCI,
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Subtarget);
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case ISD::SETCC: return combineSetCC(N, DAG, Subtarget);
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case X86ISD::SETCC: return combineX86SetCC(N, DAG, Subtarget);
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case X86ISD::BRCOND: return combineBrCond(N, DAG, Subtarget);
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@ -9632,21 +9632,15 @@ multiclass AVX512_pmovx_patterns<string OpcPrefix, SDNode ExtOp,
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(!cast<I>(OpcPrefix#BWZ128rm) addr:$src)>;
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def : Pat<(v8i16 (InVecOp (v16i8 (vzload_v2i64 addr:$src)))),
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(!cast<I>(OpcPrefix#BWZ128rm) addr:$src)>;
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def : Pat<(v8i16 (InVecOp (loadv16i8 addr:$src))),
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(!cast<I>(OpcPrefix#BWZ128rm) addr:$src)>;
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}
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let Predicates = [HasVLX] in {
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def : Pat<(v4i32 (InVecOp (bc_v16i8 (v4i32 (scalar_to_vector (loadi32 addr:$src)))))),
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(!cast<I>(OpcPrefix#BDZ128rm) addr:$src)>;
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def : Pat<(v4i32 (InVecOp (v16i8 (vzload_v4i32 addr:$src)))),
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(!cast<I>(OpcPrefix#BDZ128rm) addr:$src)>;
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def : Pat<(v4i32 (InVecOp (loadv16i8 addr:$src))),
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(!cast<I>(OpcPrefix#BDZ128rm) addr:$src)>;
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def : Pat<(v2i64 (InVecOp (bc_v16i8 (v4i32 (scalar_to_vector (extloadi32i16 addr:$src)))))),
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(!cast<I>(OpcPrefix#BQZ128rm) addr:$src)>;
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def : Pat<(v2i64 (InVecOp (loadv16i8 addr:$src))),
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(!cast<I>(OpcPrefix#BQZ128rm) addr:$src)>;
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def : Pat<(v4i32 (InVecOp (bc_v8i16 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
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(!cast<I>(OpcPrefix#WDZ128rm) addr:$src)>;
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@ -9654,15 +9648,11 @@ multiclass AVX512_pmovx_patterns<string OpcPrefix, SDNode ExtOp,
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(!cast<I>(OpcPrefix#WDZ128rm) addr:$src)>;
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def : Pat<(v4i32 (InVecOp (v8i16 (vzload_v2i64 addr:$src)))),
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(!cast<I>(OpcPrefix#WDZ128rm) addr:$src)>;
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def : Pat<(v4i32 (InVecOp (loadv8i16 addr:$src))),
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(!cast<I>(OpcPrefix#WDZ128rm) addr:$src)>;
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def : Pat<(v2i64 (InVecOp (bc_v8i16 (v4i32 (scalar_to_vector (loadi32 addr:$src)))))),
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(!cast<I>(OpcPrefix#WQZ128rm) addr:$src)>;
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def : Pat<(v2i64 (InVecOp (v8i16 (vzload_v4i32 addr:$src)))),
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(!cast<I>(OpcPrefix#WQZ128rm) addr:$src)>;
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def : Pat<(v2i64 (InVecOp (loadv8i16 addr:$src))),
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(!cast<I>(OpcPrefix#WQZ128rm) addr:$src)>;
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def : Pat<(v2i64 (InVecOp (bc_v4i32 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
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(!cast<I>(OpcPrefix#DQZ128rm) addr:$src)>;
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@ -9670,37 +9660,27 @@ multiclass AVX512_pmovx_patterns<string OpcPrefix, SDNode ExtOp,
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(!cast<I>(OpcPrefix#DQZ128rm) addr:$src)>;
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def : Pat<(v2i64 (InVecOp (v4i32 (vzload_v2i64 addr:$src)))),
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(!cast<I>(OpcPrefix#DQZ128rm) addr:$src)>;
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def : Pat<(v2i64 (InVecOp (loadv4i32 addr:$src))),
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(!cast<I>(OpcPrefix#DQZ128rm) addr:$src)>;
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}
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let Predicates = [HasVLX] in {
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def : Pat<(v8i32 (InVecOp (bc_v16i8 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
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(!cast<I>(OpcPrefix#BDZ256rm) addr:$src)>;
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def : Pat<(v8i32 (InVecOp (v16i8 (vzload_v2i64 addr:$src)))),
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(!cast<I>(OpcPrefix#BDZ256rm) addr:$src)>;
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def : Pat<(v8i32 (InVecOp (loadv16i8 addr:$src))),
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(!cast<I>(OpcPrefix#BDZ256rm) addr:$src)>;
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def : Pat<(v4i64 (InVecOp (bc_v16i8 (v4i32 (scalar_to_vector (loadi32 addr:$src)))))),
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(!cast<I>(OpcPrefix#BQZ256rm) addr:$src)>;
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def : Pat<(v4i64 (InVecOp (v16i8 (vzload_v4i32 addr:$src)))),
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(!cast<I>(OpcPrefix#BQZ256rm) addr:$src)>;
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def : Pat<(v4i64 (InVecOp (loadv16i8 addr:$src))),
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(!cast<I>(OpcPrefix#BQZ256rm) addr:$src)>;
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def : Pat<(v4i64 (InVecOp (bc_v8i16 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
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(!cast<I>(OpcPrefix#WQZ256rm) addr:$src)>;
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def : Pat<(v4i64 (InVecOp (v8i16 (vzload_v2i64 addr:$src)))),
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(!cast<I>(OpcPrefix#WQZ256rm) addr:$src)>;
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def : Pat<(v4i64 (InVecOp (loadv8i16 addr:$src))),
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(!cast<I>(OpcPrefix#WQZ256rm) addr:$src)>;
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}
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// 512-bit patterns
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let Predicates = [HasAVX512] in {
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def : Pat<(v8i64 (InVecOp (bc_v16i8 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
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(!cast<I>(OpcPrefix#BQZrm) addr:$src)>;
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def : Pat<(v8i64 (InVecOp (loadv16i8 addr:$src))),
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(!cast<I>(OpcPrefix#BQZrm) addr:$src)>;
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}
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}
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@ -4947,8 +4947,6 @@ multiclass SS41I_pmovx_avx2_patterns<string OpcPrefix, string ExtTy,
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(!cast<I>(OpcPrefix#BDYrm) addr:$src)>;
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def : Pat<(v8i32 (InVecOp (v16i8 (vzload_v2i64 addr:$src)))),
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(!cast<I>(OpcPrefix#BDYrm) addr:$src)>;
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def : Pat<(v8i32 (InVecOp (loadv16i8 addr:$src))),
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(!cast<I>(OpcPrefix#BDYrm) addr:$src)>;
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def : Pat<(v4i64 (ExtOp (loadv4i32 addr:$src))),
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(!cast<I>(OpcPrefix#DQYrm) addr:$src)>;
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@ -4957,15 +4955,11 @@ multiclass SS41I_pmovx_avx2_patterns<string OpcPrefix, string ExtTy,
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(!cast<I>(OpcPrefix#BQYrm) addr:$src)>;
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def : Pat<(v4i64 (InVecOp (v16i8 (vzload_v2i64 addr:$src)))),
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(!cast<I>(OpcPrefix#BQYrm) addr:$src)>;
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def : Pat<(v4i64 (InVecOp (loadv16i8 addr:$src))),
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(!cast<I>(OpcPrefix#BQYrm) addr:$src)>;
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def : Pat<(v4i64 (InVecOp (bc_v8i16 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
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(!cast<I>(OpcPrefix#WQYrm) addr:$src)>;
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def : Pat<(v4i64 (InVecOp (v8i16 (vzload_v2i64 addr:$src)))),
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(!cast<I>(OpcPrefix#WQYrm) addr:$src)>;
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def : Pat<(v4i64 (InVecOp (loadv8i16 addr:$src))),
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(!cast<I>(OpcPrefix#WQYrm) addr:$src)>;
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}
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}
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