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[SystemZ] Improve handling of Select pseudo-instructions
If we have LOCR instructions, select them directly from SelectionDAG instead of first going through a pseudo instruction and then using the custom inserter to emit the LOCR. Provide Select pseudo-instructions for VR32/VR64 if we have vector instructions, to avoid having to go through the first 16 FPRs unnecessarily. If we do not have LOCFHR, prefer using LOCR followed by a move over a conditional branch. llvm-svn: 331191
This commit is contained in:
Ulrich Weigand
parent
6211a39789
commit
fbbb5881dd
@ -62,6 +62,7 @@ def FeatureLoadStoreOnCond : SystemZFeature<
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"load-store-on-cond", "LoadStoreOnCond",
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"Assume that the load/store-on-condition facility is installed"
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>;
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def FeatureNoLoadStoreOnCond : SystemZMissingFeature<"LoadStoreOnCond">;
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def FeaturePopulationCount : SystemZFeature<
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"population-count", "PopulationCount",
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@ -5954,8 +5954,7 @@ static unsigned forceReg(MachineInstr &MI, MachineOperand &Base,
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// Implement EmitInstrWithCustomInserter for pseudo Select* instruction MI.
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MachineBasicBlock *
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SystemZTargetLowering::emitSelect(MachineInstr &MI,
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MachineBasicBlock *MBB,
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unsigned LOCROpcode) const {
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MachineBasicBlock *MBB) const {
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const SystemZInstrInfo *TII =
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static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
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@ -5966,15 +5965,6 @@ SystemZTargetLowering::emitSelect(MachineInstr &MI,
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unsigned CCMask = MI.getOperand(4).getImm();
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DebugLoc DL = MI.getDebugLoc();
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// Use LOCROpcode if possible.
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if (LOCROpcode && Subtarget.hasLoadStoreOnCond()) {
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BuildMI(*MBB, MI, DL, TII->get(LOCROpcode), DestReg)
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.addReg(FalseReg).addReg(TrueReg)
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.addImm(CCValid).addImm(CCMask);
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MI.eraseFromParent();
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return MBB;
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}
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MachineBasicBlock *StartMBB = MBB;
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MachineBasicBlock *JoinMBB = splitBlockBefore(MI, MBB);
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MachineBasicBlock *FalseMBB = emitBlockAfter(StartMBB);
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@ -6824,18 +6814,15 @@ MachineBasicBlock *SystemZTargetLowering::emitLoadAndTestCmp0(
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MachineBasicBlock *SystemZTargetLowering::EmitInstrWithCustomInserter(
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MachineInstr &MI, MachineBasicBlock *MBB) const {
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switch (MI.getOpcode()) {
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case SystemZ::Select32Mux:
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return emitSelect(MI, MBB,
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Subtarget.hasLoadStoreOnCond2()? SystemZ::LOCRMux : 0);
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case SystemZ::Select32:
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return emitSelect(MI, MBB, SystemZ::LOCR);
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case SystemZ::Select64:
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return emitSelect(MI, MBB, SystemZ::LOCGR);
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case SystemZ::SelectF32:
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case SystemZ::SelectF64:
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case SystemZ::SelectF128:
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case SystemZ::SelectVR32:
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case SystemZ::SelectVR64:
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case SystemZ::SelectVR128:
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return emitSelect(MI, MBB, 0);
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return emitSelect(MI, MBB);
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case SystemZ::CondStore8Mux:
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return emitCondStore(MI, MBB, SystemZ::STCMux, 0, false);
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@ -601,8 +601,7 @@ private:
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MachineBasicBlock *Target) const;
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// Implement EmitInstrWithCustomInserter for individual operation types.
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MachineBasicBlock *emitSelect(MachineInstr &MI, MachineBasicBlock *BB,
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unsigned LOCROpcode) const;
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MachineBasicBlock *emitSelect(MachineInstr &MI, MachineBasicBlock *BB) const;
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MachineBasicBlock *emitCondStore(MachineInstr &MI, MachineBasicBlock *BB,
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unsigned StoreOpcode, unsigned STOCOpcode,
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bool Invert) const;
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@ -15,6 +15,10 @@
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//===----------------------------------------------------------------------===//
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// C's ?: operator for floating-point operands.
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let Predicates = [FeatureVector] in {
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def SelectVR32 : SelectWrapper<f32, VR32>;
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def SelectVR64 : SelectWrapper<f64, VR64>;
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}
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def SelectF32 : SelectWrapper<f32, FP32>;
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def SelectF64 : SelectWrapper<f64, FP64>;
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let Predicates = [FeatureNoVectorEnhancements1] in
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@ -3132,7 +3132,9 @@ class CondBinaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1,
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RegisterOperand cls2>
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: InstRRFc<opcode, (outs cls1:$R1),
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(ins cls1:$R1src, cls2:$R2, cond4:$valid, cond4:$M3),
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mnemonic#"$M3\t$R1, $R2", []> {
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mnemonic#"$M3\t$R1, $R2",
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[(set cls1:$R1, (z_select_ccmask cls2:$R2, cls1:$R1src,
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cond4:$valid, cond4:$M3))]> {
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let Constraints = "$R1 = $R1src";
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let DisableEncoding = "$R1src";
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let CCMaskLast = 1;
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@ -4611,7 +4613,9 @@ class CompareRXYPseudo<SDPatternOperator operator, RegisterOperand cls,
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// register.
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class CondBinaryRRFPseudo<RegisterOperand cls1, RegisterOperand cls2>
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: Pseudo<(outs cls1:$R1),
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(ins cls1:$R1src, cls2:$R2, cond4:$valid, cond4:$M3), []> {
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(ins cls1:$R1src, cls2:$R2, cond4:$valid, cond4:$M3),
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[(set cls1:$R1, (z_select_ccmask cls2:$R2, cls1:$R1src,
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cond4:$valid, cond4:$M3))]> {
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let Constraints = "$R1 = $R1src";
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let DisableEncoding = "$R1src";
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let CCMaskLast = 1;
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@ -325,9 +325,10 @@ let isReturn = 1, isTerminator = 1, hasCtrlDep = 1 in {
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// Select instructions
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//===----------------------------------------------------------------------===//
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def Select32Mux : SelectWrapper<i32, GRX32>, Requires<[FeatureHighWord]>;
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def Select32 : SelectWrapper<i32, GR32>;
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def Select64 : SelectWrapper<i64, GR64>;
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def Select32 : SelectWrapper<i32, GR32>,
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Requires<[FeatureNoLoadStoreOnCond]>;
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def Select64 : SelectWrapper<i64, GR64>,
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Requires<[FeatureNoLoadStoreOnCond]>;
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// We don't define 32-bit Mux stores if we don't have STOCFH, because the
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// low-only STOC should then always be used if possible.
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@ -495,7 +496,7 @@ let Predicates = [FeatureLoadStoreOnCond2], Uses = [CC] in {
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defm LOCHI : CondBinaryRIEPair<"lochi", 0xEC42, GR32, imm32sx16>;
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defm LOCGHI : CondBinaryRIEPair<"locghi", 0xEC46, GR64, imm64sx16>;
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// Move register on condition. Expanded from Select* pseudos and
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// Move register on condition. Matched via DAG pattern and
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// created by early if-conversion.
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let isCommutable = 1 in {
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// Expands to LOCR or LOCFHR or a branch-and-move sequence,
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@ -530,7 +531,7 @@ let Predicates = [FeatureLoadStoreOnCond2], Uses = [CC] in {
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}
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let Predicates = [FeatureLoadStoreOnCond], Uses = [CC] in {
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// Move register on condition. Expanded from Select* pseudos and
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// Move register on condition. Matched via DAG pattern and
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// created by early if-conversion.
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let isCommutable = 1 in {
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defm LOCR : CondBinaryRRFPair<"locr", 0xB9F2, GR32, GR32>;
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@ -290,11 +290,14 @@ define void @f12() {
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}
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; Test selects involving high registers.
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; Note that we prefer to use a LOCR and move the result to a high register.
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define void @f13(i32 %x, i32 %y) {
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; CHECK-LABEL: f13:
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; CHECK: llihl [[REG:%r[0-5]]], 0
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; CHECK: cije %r2, 0
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; CHECK: iihf [[REG]], 2102030405
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; CHECK-DAG: chi %r2, 0
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; CHECK-DAG: iilf [[REG1:%r[0-5]]], 2102030405
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; CHECK-DAG: lhi [[REG2:%r[0-5]]], 0
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; CHECK: locre [[REG1]], [[REG2]]
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; CHECK: risbhg [[REG:%r[0-5]]], [[REG1]], 0, 159, 32
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; CHECK: blah [[REG]]
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; CHECK: br %r14
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%cmp = icmp eq i32 %x, 0
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@ -306,9 +309,10 @@ define void @f13(i32 %x, i32 %y) {
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; Test selects involving low registers.
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define void @f14(i32 %x, i32 %y) {
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; CHECK-LABEL: f14:
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; CHECK: lhi [[REG:%r[0-5]]], 0
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; CHECK: cije %r2, 0
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; CHECK: iilf [[REG]], 2102030405
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; CHECK-DAG: chi %r2, 0
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; CHECK-DAG: iilf [[REG:%r[0-5]]], 2102030405
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; CHECK-DAG: lhi [[REG1:%r[0-5]]], 0
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; CHECK: locre [[REG]], [[REG1]]
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; CHECK: blah [[REG]]
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; CHECK: br %r14
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%cmp = icmp eq i32 %x, 0
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