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https://github.com/RPCS3/llvm-mirror.git
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remove misleading documentation: LLVM has no atomic support yet.
llvm-svn: 42580
This commit is contained in:
Chris Lattner
parent
a31fa80185
commit
fc0f3994a0
@ -191,15 +191,6 @@
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</li>
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<li><a href="#int_debugger">Debugger intrinsics</a></li>
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<li><a href="#int_eh">Exception Handling intrinsics</a></li>
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<li><a href="#int_atomics">Atomic Operations and Synchronization Intrinsics</a>
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<ol>
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<li><a href="#int_lcs">'<tt>llvm.atomic.lcs.*</tt>' Intrinsic</a></li>
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<li><a href="#int_ls">'<tt>llvm.atomic.ls.*</tt>' Intrinsic</a></li>
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<li><a href="#int_las">'<tt>llvm.atomic.las.*</tt>' Intrinsic</a></li>
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<li><a href="#int_lss">'<tt>llvm.atomic.lss.*</tt>' Intrinsic</a></li>
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<li><a href="#int_memory_barrier">'<tt>llvm.memory.barrier</tt>' Intrinsic</a></li>
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</ol>
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</li>
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<li><a href="#int_trampoline">Trampoline Intrinsic</a>
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<ol>
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<li><a href="#int_it">'<tt>llvm.init.trampoline</tt>' Intrinsic</a></li>
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@ -291,7 +282,7 @@ by the verifier pass indicate bugs in transformation passes or input to
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the parser.</p>
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</div>
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<!-- Describe the typesetting conventions here. -->
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<!-- Describe the typesetting conventions here. --> </div>
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<!-- *********************************************************************** -->
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<div class="doc_section"> <a name="identifiers">Identifiers</a> </div>
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@ -4859,298 +4850,6 @@ href="ExceptionHandling.html#format_common_intrinsics">LLVM Exception
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Handling</a> document. </p>
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</div>
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<!-- ======================================================================= -->
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<div class="doc_subsection">
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<a name="int_atomics">Atomic Operations and Synchronization Intrinsics</a>
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</div>
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<div class="doc_text">
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<p>
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These intrinsic functions expand the "universal IR" of LLVM to represent
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hardware constructs for atomic operations and memory synchronization. This
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provides an interface to the hardware, not an interface to the programmer. It
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is aimed at a low enough level to allow any programming models or APIs which
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need atomic behaviors to map cleanly onto it. It is also modeled primarily on
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hardware behavior. Just as hardware provides a "universal IR" for source
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languages, it also provides a starting point for developing a "universal"
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atomic operation and synchronization IR.
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</p>
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<p>
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These do <em>not</em> form an API such as high-level threading libraries,
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software transaction memory systems, atomic primitives, and intrinsic
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functions as found in BSD, GNU libc, atomic_ops, APR, and other system and
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application libraries. The hardware interface provided by LLVM should allow
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a clean implementation of all of these APIs and parallel programming models.
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No one model or paradigm should be selected above others unless the hardware
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itself ubiquitously does so.
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</p>
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</div>
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<!-- _______________________________________________________________________ -->
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<div class="doc_subsubsection">
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<a name="int_lcs">'<tt>llvm.atomic.lcs.*</tt>' Intrinsic</a>
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</div>
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<div class="doc_text">
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<h5>Syntax:</h5>
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<p>
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This is an overloaded intrinsic. You can use <tt>llvm.atomic.lcs</tt> on any
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integer bit width. Not all targets support all bit widths however.</p>
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<pre>
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declare i8 @llvm.atomic.lcs.i8.i8p.i8.i8( i8* <ptr>, i8 <cmp>, i8 <val> )
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declare i16 @llvm.atomic.lcs.i16.i16p.i16.i16( i16* <ptr>, i16 <cmp>, i16 <val> )
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declare i32 @llvm.atomic.lcs.i32.i32p.i32.i32( i32* <ptr>, i32 <cmp>, i32 <val> )
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declare i64 @llvm.atomic.lcs.i64.i64p.i64.i64( i64* <ptr>, i64 <cmp>, i64 <val> )
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</pre>
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<h5>Overview:</h5>
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<p>
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This loads a value in memory and compares it to a given value. If they are
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equal, it stores a new value into the memory.
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</p>
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<h5>Arguments:</h5>
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<p>
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The <tt>llvm.atomic.lcs</tt> intrinsic takes three arguments. The result as
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well as both <tt>cmp</tt> and <tt>val</tt> must be integer values with the
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same bit width. The <tt>ptr</tt> argument must be a pointer to a value of
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this integer type. While any bit width integer may be used, targets may only
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lower representations they support in hardware.
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</p>
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<h5>Semantics:</h5>
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<p>
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This entire intrinsic must be executed atomically. It first loads the value
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in memory pointed to by <tt>ptr</tt> and compares it with the value
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<tt>cmp</tt>. If they are equal, <tt>val</tt> is stored into the memory. The
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loaded value is yielded in all cases. This provides the equivalent of an
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atomic compare-and-swap operation within the SSA framework.
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</p>
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<h5>Examples:</h5>
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<pre>
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%ptr = malloc i32
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store i32 4, %ptr
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%val1 = add i32 4, 4
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%result1 = call i32 @llvm.atomic.lcs( i32* %ptr, i32 4, %val1 )
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<i>; yields {i32}:result1 = 4</i>
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%stored1 = icmp eq i32 %result1, 4 <i>; yields {i1}:stored1 = true</i>
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%memval1 = load i32* %ptr <i>; yields {i32}:memval1 = 8</i>
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%val2 = add i32 1, 1
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%result2 = call i32 @llvm.atomic.lcs( i32* %ptr, i32 5, %val2 )
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<i>; yields {i32}:result2 = 8</i>
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%stored2 = icmp eq i32 %result2, 5 <i>; yields {i1}:stored2 = false</i>
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%memval2 = load i32* %ptr <i>; yields {i32}:memval2 = 8</i>
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</pre>
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</div>
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<!-- _______________________________________________________________________ -->
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<div class="doc_subsubsection">
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<a name="int_ls">'<tt>llvm.atomic.ls.*</tt>' Intrinsic</a>
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</div>
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<div class="doc_text">
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<h5>Syntax:</h5>
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<p>
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This is an overloaded intrinsic. You can use <tt>llvm.atomic.ls</tt> on any
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integer bit width. Not all targets support all bit widths however.</p>
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<pre>
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declare i8 @llvm.atomic.ls.i8.i8p.i8( i8* <ptr>, i8 <val> )
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declare i16 @llvm.atomic.ls.i16.i16p.i16( i16* <ptr>, i16 <val> )
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declare i32 @llvm.atomic.ls.i32.i32p.i32( i32* <ptr>, i32 <val> )
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declare i64 @llvm.atomic.ls.i64.i64p.i64( i64* <ptr>, i64 <val> )
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</pre>
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<h5>Overview:</h5>
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<p>
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This intrinsic loads the value stored in memory at <tt>ptr</tt> and yields
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the value from memory. It then stores the value in <tt>val</tt> in the memory
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at <tt>ptr</tt>.
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</p>
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<h5>Arguments:</h5>
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<p>
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The <tt>llvm.atomic.ls</tt> intrinsic takes two arguments. Both the
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<tt>val</tt> argument and the result must be integers of the same bit width.
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The first argument, <tt>ptr</tt>, must be a pointer to a value of this
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integer type. The targets may only lower integer representations they
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support.
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</p>
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<h5>Semantics:</h5>
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<p>
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This intrinsic loads the value pointed to by <tt>ptr</tt>, yields it, and
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stores <tt>val</tt> back into <tt>ptr</tt> atomically. This provides the
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equivalent of an atomic swap operation within the SSA framework.
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</p>
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<h5>Examples:</h5>
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<pre>
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%ptr = malloc i32
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store i32 4, %ptr
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%val1 = add i32 4, 4
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%result1 = call i32 @llvm.atomic.ls( i32* %ptr, i32 %val1 )
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<i>; yields {i32}:result1 = 4</i>
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%stored1 = icmp eq i32 %result1, 4 <i>; yields {i1}:stored1 = true</i>
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%memval1 = load i32* %ptr <i>; yields {i32}:memval1 = 8</i>
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%val2 = add i32 1, 1
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%result2 = call i32 @llvm.atomic.ls( i32* %ptr, i32 %val2 )
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<i>; yields {i32}:result2 = 8</i>
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%stored2 = icmp eq i32 %result2, 8 <i>; yields {i1}:stored2 = true</i>
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%memval2 = load i32* %ptr <i>; yields {i32}:memval2 = 2</i>
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</pre>
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</div>
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<!-- _______________________________________________________________________ -->
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<div class="doc_subsubsection">
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<a name="int_las">'<tt>llvm.atomic.las.*</tt>' Intrinsic</a>
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</div>
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<div class="doc_text">
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<h5>Syntax:</h5>
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<p>
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This is an overloaded intrinsic. You can use <tt>llvm.atomic.las</tt> on any
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integer bit width. Not all targets support all bit widths however.</p>
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<pre>
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declare i8 @llvm.atomic.las.i8.i8p.i8( i8* <ptr>, i8 <delta> )
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declare i16 @llvm.atomic.las.i16.i16p.i16( i16* <ptr>, i16 <delta> )
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declare i32 @llvm.atomic.las.i32.i32p.i32( i32* <ptr>, i32 <delta> )
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declare i64 @llvm.atomic.las.i64.i64p.i64( i64* <ptr>, i64 <delta> )
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</pre>
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<h5>Overview:</h5>
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<p>
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This intrinsic adds <tt>delta</tt> to the value stored in memory at
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<tt>ptr</tt>. It yields the original value at <tt>ptr</tt>.
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</p>
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<h5>Arguments:</h5>
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<p>
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The intrinsic takes two arguments, the first a pointer to an integer value
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and the second an integer value. The result is also an integer value. These
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integer types can have any bit width, but they must all have the same bit
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width. The targets may only lower integer representations they support.
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</p>
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<h5>Semantics:</h5>
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<p>
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This intrinsic does a series of operations atomically. It first loads the
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value stored at <tt>ptr</tt>. It then adds <tt>delta</tt>, stores the result
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to <tt>ptr</tt>. It yields the original value stored at <tt>ptr</tt>.
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</p>
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<h5>Examples:</h5>
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<pre>
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%ptr = malloc i32
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store i32 4, %ptr
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%result1 = call i32 @llvm.atomic.las( i32* %ptr, i32 4 )
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<i>; yields {i32}:result1 = 4</i>
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%result2 = call i32 @llvm.atomic.las( i32* %ptr, i32 2 )
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<i>; yields {i32}:result2 = 8</i>
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%result3 = call i32 @llvm.atomic.las( i32* %ptr, i32 5 )
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<i>; yields {i32}:result3 = 10</i>
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%memval = load i32* %ptr <i>; yields {i32}:memval1 = 15</i>
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</pre>
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</div>
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<!-- _______________________________________________________________________ -->
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<div class="doc_subsubsection">
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<a name="int_lss">'<tt>llvm.atomic.lss.*</tt>' Intrinsic</a>
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</div>
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<div class="doc_text">
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<h5>Syntax:</h5>
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<p>
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This is an overloaded intrinsic. You can use <tt>llvm.atomic.lss</tt> on any
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integer bit width. Not all targets support all bit widths however.</p>
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<pre>
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declare i8 @llvm.atomic.lss.i8.i8.i8( i8* <ptr>, i8 <delta> )
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declare i16 @llvm.atomic.lss.i16.i16.i16( i16* <ptr>, i16 <delta> )
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declare i32 @llvm.atomic.lss.i32.i32.i32( i32* <ptr>, i32 <delta> )
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declare i64 @llvm.atomic.lss.i64.i64.i64( i64* <ptr>, i64 <delta> )
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</pre>
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<h5>Overview:</h5>
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<p>
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This intrinsic subtracts <tt>delta</tt> from the value stored in memory at
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<tt>ptr</tt>. It yields the original value at <tt>ptr</tt>.
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</p>
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<h5>Arguments:</h5>
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<p>
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The intrinsic takes two arguments, the first a pointer to an integer value
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and the second an integer value. The result is also an integer value. These
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integer types can have any bit width, but they must all have the same bit
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width. The targets may only lower integer representations they support.
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</p>
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<h5>Semantics:</h5>
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<p>
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This intrinsic does a series of operations atomically. It first loads the
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value stored at <tt>ptr</tt>. It then subtracts <tt>delta</tt>,
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stores the result to <tt>ptr</tt>. It yields the original value stored
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at <tt>ptr</tt>.
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</p>
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<h5>Examples:</h5>
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<pre>
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%ptr = malloc i32
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store i32 32, %ptr
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%result1 = call i32 @llvm.atomic.lss( i32* %ptr, i32 4 )
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<i>; yields {i32}:result1 = 32</i>
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%result2 = call i32 @llvm.atomic.lss( i32* %ptr, i32 2 )
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<i>; yields {i32}:result2 = 28</i>
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%result3 = call i32 @llvm.atomic.lss( i32* %ptr, i32 5 )
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<i>; yields {i32}:result3 = 26</i>
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%memval = load i32* %ptr <i>; yields {i32}:memval1 = 21</i>
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</pre>
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</div>
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<!-- _______________________________________________________________________ -->
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<div class="doc_subsubsection">
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<a name="int_memory_barrier">'<tt>llvm.memory.barrier</tt>' Intrinsic</a>
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</div>
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<div class="doc_text">
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<h5>Syntax:</h5>
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<pre>
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declare void @llvm.memory.barrier( i1 <ll>, i1 <ls>, i1 <sl>, i1 <ss> )
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</pre>
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<h5>Overview:</h5>
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<p>
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The <tt>llvm.memory.barrier</tt> intrinsic guarantees ordering between
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specific pairs of memory access types.
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</p>
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<h5>Arguments:</h5>
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<p>
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The <tt>llvm.memory.barrier</tt> intrinsic requires four boolean arguments.
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Each argument enables a specific barrier as listed below.
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</p>
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<ul>
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<li><tt>ll</tt>: load-load barrier</li>
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<li><tt>ls</tt>: load-store barrier</li>
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<li><tt>sl</tt>: store-load barrier</li>
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<li><tt>ss</tt>: store-store barrier</li>
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</ul>
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<h5>Semantics:</h5>
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<p>
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This intrinsic causes the system to enforce some ordering constraints upon
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the loads and stores of the program. This barrier does not indicate
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<em>when</em> any events will occur, it only enforces an <em>order</em> in
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which they occur. For any of the specified pairs of load and store operations
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(f.ex. load-load, or store-load), all of the first operations preceding the
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barrier will complete before any of the second operations succeeding the
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barrier begin. Specifically the semantics for each pairing is as follows:
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</p>
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<ul>
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<li><tt>ll</tt>: All loads before the barrier must complete before any load
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after the barrier begins.</li>
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<li><tt>ls</tt>: All loads before the barrier must complete before any
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store after the barrier begins.</li>
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<li><tt>ss</tt>: All stores before the barrier must complete before any
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store after the barrier begins.</li>
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<li><tt>sl</tt>: All stores before the barrier must complete before any
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load after the barrier begins.</li>
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</ul>
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<p>
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These semantics are applied with a logical "and" behavior when more than one
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is enabled in a single memory barrier intrinsic.
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</p>
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<h5>Example:</h5>
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<pre>
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%ptr = malloc i32
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store i32 4, %ptr
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%result1 = load i32* %ptr <i>; yields {i32}:result1 = 4</i>
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call void @llvm.memory.barrier( i1 false, i1 true, i1 false, i1 false )
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<i>; guarantee the above finishes</i>
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store i32 8, %ptr <i>; before this begins</i>
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</pre>
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</div>
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<!-- ======================================================================= -->
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<div class="doc_subsection">
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<a name="int_trampoline">Trampoline Intrinsic</a>
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