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ptx: add the rest of special registers of ISA version 2.0
llvm-svn: 127397
This commit is contained in:
Che-Liang Chiou
parent
92652a803f
commit
fc6c7ba9d5
@ -12,27 +12,50 @@
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//===----------------------------------------------------------------------===//
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let TargetPrefix = "ptx" in {
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multiclass PTXReadSpecialRegisterIntrinsic {
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// FIXME Since PTX 2.0, special registers are redefined as v4i32 type
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multiclass PTXReadSpecialRegisterIntrinsic_v4i16 {
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def _r64 : Intrinsic<[llvm_i64_ty], [], [IntrNoMem]>;
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def _v4i16 : Intrinsic<[llvm_v4i16_ty], [], [IntrNoMem]>;
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def _x : Intrinsic<[llvm_i16_ty], [], [IntrNoMem]>;
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def _y : Intrinsic<[llvm_i16_ty], [], [IntrNoMem]>;
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def _z : Intrinsic<[llvm_i16_ty], [], [IntrNoMem]>;
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def _w : Intrinsic<[llvm_i16_ty], [], [IntrNoMem]>;
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}
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multiclass PTXReadSpecialSubRegisterIntrinsic {
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def _x : Intrinsic<[llvm_i16_ty], [], [IntrNoMem]>;
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def _y : Intrinsic<[llvm_i16_ty], [], [IntrNoMem]>;
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def _z : Intrinsic<[llvm_i16_ty], [], [IntrNoMem]>;
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def _w : Intrinsic<[llvm_i16_ty], [], [IntrNoMem]>;
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}
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class PTXReadSpecialRegisterIntrinsic_r32
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: Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>;
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class PTXReadSpecialRegisterIntrinsic_r64
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: Intrinsic<[llvm_i64_ty], [], [IntrNoMem]>;
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}
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defm int_ptx_read_tid : PTXReadSpecialRegisterIntrinsic;
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defm int_ptx_read_tid : PTXReadSpecialSubRegisterIntrinsic;
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defm int_ptx_read_ntid : PTXReadSpecialRegisterIntrinsic;
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defm int_ptx_read_ntid : PTXReadSpecialSubRegisterIntrinsic;
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defm int_ptx_read_ctaid : PTXReadSpecialRegisterIntrinsic;
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defm int_ptx_read_ctaid : PTXReadSpecialSubRegisterIntrinsic;
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defm int_ptx_read_nctaid : PTXReadSpecialRegisterIntrinsic;
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defm int_ptx_read_nctaid : PTXReadSpecialSubRegisterIntrinsic;
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defm int_ptx_read_tid : PTXReadSpecialRegisterIntrinsic_v4i16;
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defm int_ptx_read_ntid : PTXReadSpecialRegisterIntrinsic_v4i16;
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def int_ptx_read_laneid : PTXReadSpecialRegisterIntrinsic_r32;
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def int_ptx_read_warpid : PTXReadSpecialRegisterIntrinsic_r32;
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def int_ptx_read_nwarpid : PTXReadSpecialRegisterIntrinsic_r32;
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defm int_ptx_read_ctaid : PTXReadSpecialRegisterIntrinsic_v4i16;
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defm int_ptx_read_nctaid : PTXReadSpecialRegisterIntrinsic_v4i16;
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def int_ptx_read_smid : PTXReadSpecialRegisterIntrinsic_r32;
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def int_ptx_read_nsmid : PTXReadSpecialRegisterIntrinsic_r32;
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def int_ptx_read_gridid : PTXReadSpecialRegisterIntrinsic_r32;
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def int_ptx_read_lanemask_eq : PTXReadSpecialRegisterIntrinsic_r32;
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def int_ptx_read_lanemask_le : PTXReadSpecialRegisterIntrinsic_r32;
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def int_ptx_read_lanemask_lt : PTXReadSpecialRegisterIntrinsic_r32;
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def int_ptx_read_lanemask_ge : PTXReadSpecialRegisterIntrinsic_r32;
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def int_ptx_read_lanemask_gt : PTXReadSpecialRegisterIntrinsic_r32;
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def int_ptx_read_clock : PTXReadSpecialRegisterIntrinsic_r32;
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def int_ptx_read_clock64 : PTXReadSpecialRegisterIntrinsic_r64;
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def int_ptx_read_pm0 : PTXReadSpecialRegisterIntrinsic_r32;
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def int_ptx_read_pm1 : PTXReadSpecialRegisterIntrinsic_r32;
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def int_ptx_read_pm2 : PTXReadSpecialRegisterIntrinsic_r32;
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def int_ptx_read_pm3 : PTXReadSpecialRegisterIntrinsic_r32;
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let TargetPrefix = "ptx" in
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def int_ptx_bar_sync : Intrinsic<[], [llvm_i32_ty], []>;
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@ -13,40 +13,76 @@
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// PTX Special Purpose Register Accessor Intrinsics
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class PTX_READ_SPECIAL_REGISTER<string regname, Intrinsic intop>
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class PTX_READ_SPECIAL_REGISTER_R64<string regname, Intrinsic intop>
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: InstPTX<(outs RRegu64:$d), (ins),
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!strconcat("mov.u64\t$d, ", regname),
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!strconcat("mov.u64\t$d, %", regname),
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[(set RRegu64:$d, (intop))]>;
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class PTX_READ_SPECIAL_REGISTER_R32<string regname, Intrinsic intop>
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: InstPTX<(outs RRegu32:$d), (ins),
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!strconcat("mov.u32\t$d, %", regname),
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[(set RRegu32:$d, (intop))]>;
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class PTX_READ_SPECIAL_SUB_REGISTER<string regname, Intrinsic intop>
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: InstPTX<(outs RRegu16:$d), (ins),
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!strconcat("mov.u16\t$d, ", regname),
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!strconcat("mov.u16\t$d, %", regname),
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[(set RRegu16:$d, (intop))]>;
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def PTX_READ_TID_R64 : PTX_READ_SPECIAL_REGISTER<"tid", int_ptx_read_tid_r64>;
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// TODO Add read vector-version of special registers
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def PTX_READ_TID_R64 : PTX_READ_SPECIAL_REGISTER_R64<"tid", int_ptx_read_tid_r64>;
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def PTX_READ_TID_X : PTX_READ_SPECIAL_SUB_REGISTER<"tid.x", int_ptx_read_tid_x>;
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def PTX_READ_TID_Y : PTX_READ_SPECIAL_SUB_REGISTER<"tid.y", int_ptx_read_tid_y>;
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def PTX_READ_TID_Z : PTX_READ_SPECIAL_SUB_REGISTER<"tid.z", int_ptx_read_tid_z>;
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def PTX_READ_TID_W : PTX_READ_SPECIAL_SUB_REGISTER<"tid.w", int_ptx_read_tid_w>;
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def PTX_READ_NTID_R64 : PTX_READ_SPECIAL_REGISTER<"ntid", int_ptx_read_ntid_r64>;
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def PTX_READ_NTID_R64 : PTX_READ_SPECIAL_REGISTER_R64<"ntid", int_ptx_read_ntid_r64>;
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def PTX_READ_NTID_X : PTX_READ_SPECIAL_SUB_REGISTER<"ntid.x", int_ptx_read_ntid_x>;
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def PTX_READ_NTID_Y : PTX_READ_SPECIAL_SUB_REGISTER<"ntid.y", int_ptx_read_ntid_y>;
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def PTX_READ_NTID_Z : PTX_READ_SPECIAL_SUB_REGISTER<"ntid.z", int_ptx_read_ntid_z>;
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def PTX_READ_NTID_W : PTX_READ_SPECIAL_SUB_REGISTER<"ntid.w", int_ptx_read_ntid_w>;
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def PTX_READ_CTAID_R64 : PTX_READ_SPECIAL_REGISTER<"ctaid", int_ptx_read_ctaid_r64>;
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def PTX_READ_LANEID : PTX_READ_SPECIAL_REGISTER_R32<"laneid", int_ptx_read_laneid>;
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def PTX_READ_WARPID : PTX_READ_SPECIAL_REGISTER_R32<"warpid", int_ptx_read_warpid>;
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def PTX_READ_NWARPID : PTX_READ_SPECIAL_REGISTER_R32<"nwarpid", int_ptx_read_nwarpid>;
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def PTX_READ_CTAID_R64 : PTX_READ_SPECIAL_REGISTER_R64<"ctaid", int_ptx_read_ctaid_r64>;
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def PTX_READ_CTAID_X : PTX_READ_SPECIAL_SUB_REGISTER<"ctaid.x", int_ptx_read_ctaid_x>;
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def PTX_READ_CTAID_Y : PTX_READ_SPECIAL_SUB_REGISTER<"ctaid.y", int_ptx_read_ctaid_y>;
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def PTX_READ_CTAID_Z : PTX_READ_SPECIAL_SUB_REGISTER<"ctaid.z", int_ptx_read_ctaid_z>;
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def PTX_READ_CTAID_W : PTX_READ_SPECIAL_SUB_REGISTER<"ctaid.w", int_ptx_read_ctaid_w>;
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def PTX_READ_NCTAID_R64 : PTX_READ_SPECIAL_REGISTER<"nctaid", int_ptx_read_nctaid_r64>;
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def PTX_READ_NCTAID_R64 : PTX_READ_SPECIAL_REGISTER_R64<"nctaid", int_ptx_read_nctaid_r64>;
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def PTX_READ_NCTAID_X : PTX_READ_SPECIAL_SUB_REGISTER<"nctaid.x", int_ptx_read_nctaid_x>;
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def PTX_READ_NCTAID_Y : PTX_READ_SPECIAL_SUB_REGISTER<"nctaid.y", int_ptx_read_nctaid_y>;
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def PTX_READ_NCTAID_Z : PTX_READ_SPECIAL_SUB_REGISTER<"nctaid.z", int_ptx_read_nctaid_z>;
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def PTX_READ_NCTAID_W : PTX_READ_SPECIAL_SUB_REGISTER<"nctaid.w", int_ptx_read_nctaid_w>;
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def PTX_READ_SMID : PTX_READ_SPECIAL_REGISTER_R32<"smid", int_ptx_read_smid>;
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def PTX_READ_NSMID : PTX_READ_SPECIAL_REGISTER_R32<"nsmid", int_ptx_read_nsmid>;
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def PTX_READ_GRIDID : PTX_READ_SPECIAL_REGISTER_R32<"gridid", int_ptx_read_gridid>;
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def PTX_READ_LANEMASK_EQ
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: PTX_READ_SPECIAL_REGISTER_R32<"lanemask_eq", int_ptx_read_lanemask_eq>;
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def PTX_READ_LANEMASK_LE
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: PTX_READ_SPECIAL_REGISTER_R32<"lanemask_le", int_ptx_read_lanemask_le>;
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def PTX_READ_LANEMASK_LT
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: PTX_READ_SPECIAL_REGISTER_R32<"lanemask_lt", int_ptx_read_lanemask_lt>;
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def PTX_READ_LANEMASK_GE
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: PTX_READ_SPECIAL_REGISTER_R32<"lanemask_ge", int_ptx_read_lanemask_ge>;
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def PTX_READ_LANEMASK_GT
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: PTX_READ_SPECIAL_REGISTER_R32<"lanemask_gt", int_ptx_read_lanemask_gt>;
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def PTX_READ_CLOCK
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: PTX_READ_SPECIAL_REGISTER_R32<"clock", int_ptx_read_clock>;
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def PTX_READ_CLOCK64
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: PTX_READ_SPECIAL_REGISTER_R64<"clock64", int_ptx_read_clock64>;
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def PTX_READ_PM0 : PTX_READ_SPECIAL_REGISTER_R32<"pm0", int_ptx_read_pm0>;
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def PTX_READ_PM1 : PTX_READ_SPECIAL_REGISTER_R32<"pm1", int_ptx_read_pm1>;
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def PTX_READ_PM2 : PTX_READ_SPECIAL_REGISTER_R32<"pm2", int_ptx_read_pm2>;
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def PTX_READ_PM3 : PTX_READ_SPECIAL_REGISTER_R32<"pm3", int_ptx_read_pm3>;
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// PTX Parallel Synchronization and Communication Intrinsics
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def PTX_BAR_SYNC : InstPTX<(outs), (ins i32imm:$i), "bar.sync\t$i",
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@ -1,118 +1,237 @@
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; RUN: llc < %s -march=ptx | FileCheck %s
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; RUN: llc < %s -march=ptx -mattr=+ptx20,+sm20 | FileCheck %s
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define ptx_device i16 @tid_x() {
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; CHECK: mov.u16 rh0, tid.x;
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define ptx_device i16 @test_tid_x() {
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; CHECK: mov.u16 rh0, %tid.x;
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; CHECK-NEXT: ret;
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%x = call i16 @llvm.ptx.read.tid.x()
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ret i16 %x
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}
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define ptx_device i16 @tid_y() {
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; CHECK: mov.u16 rh0, tid.y;
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define ptx_device i16 @test_tid_y() {
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; CHECK: mov.u16 rh0, %tid.y;
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; CHECK-NEXT: ret;
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%x = call i16 @llvm.ptx.read.tid.y()
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ret i16 %x
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}
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define ptx_device i16 @tid_z() {
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; CHECK: mov.u16 rh0, tid.z;
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define ptx_device i16 @test_tid_z() {
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; CHECK: mov.u16 rh0, %tid.z;
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; CHECK-NEXT: ret;
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%x = call i16 @llvm.ptx.read.tid.z()
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ret i16 %x
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}
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define ptx_device i16 @tid_w() {
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; CHECK: mov.u16 rh0, tid.w;
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define ptx_device i16 @test_tid_w() {
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; CHECK: mov.u16 rh0, %tid.w;
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; CHECK-NEXT: ret;
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%x = call i16 @llvm.ptx.read.tid.w()
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ret i16 %x
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}
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define ptx_device i16 @ntid_x() {
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; CHECK: mov.u16 rh0, ntid.x;
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define ptx_device i16 @test_ntid_x() {
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; CHECK: mov.u16 rh0, %ntid.x;
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; CHECK-NEXT: ret;
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%x = call i16 @llvm.ptx.read.ntid.x()
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ret i16 %x
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}
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define ptx_device i16 @ntid_y() {
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; CHECK: mov.u16 rh0, ntid.y;
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define ptx_device i16 @test_ntid_y() {
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; CHECK: mov.u16 rh0, %ntid.y;
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; CHECK-NEXT: ret;
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%x = call i16 @llvm.ptx.read.ntid.y()
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ret i16 %x
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}
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define ptx_device i16 @ntid_z() {
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; CHECK: mov.u16 rh0, ntid.z;
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define ptx_device i16 @test_ntid_z() {
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; CHECK: mov.u16 rh0, %ntid.z;
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; CHECK-NEXT: ret;
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%x = call i16 @llvm.ptx.read.ntid.z()
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ret i16 %x
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}
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define ptx_device i16 @ntid_w() {
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; CHECK: mov.u16 rh0, ntid.w;
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define ptx_device i16 @test_ntid_w() {
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; CHECK: mov.u16 rh0, %ntid.w;
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; CHECK-NEXT: ret;
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%x = call i16 @llvm.ptx.read.ntid.w()
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ret i16 %x
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}
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define ptx_device i16 @ctaid_x() {
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; CHECK: mov.u16 rh0, ctaid.x;
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define ptx_device i32 @test_laneid() {
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; CHECK: mov.u32 r0, %laneid;
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; CHECK-NEXT: ret;
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%x = call i32 @llvm.ptx.read.laneid()
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ret i32 %x
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}
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define ptx_device i32 @test_warpid() {
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; CHECK: mov.u32 r0, %warpid;
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; CHECK-NEXT: ret;
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%x = call i32 @llvm.ptx.read.warpid()
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ret i32 %x
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}
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define ptx_device i32 @test_nwarpid() {
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; CHECK: mov.u32 r0, %nwarpid;
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; CHECK-NEXT: ret;
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%x = call i32 @llvm.ptx.read.nwarpid()
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ret i32 %x
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}
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define ptx_device i16 @test_ctaid_x() {
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; CHECK: mov.u16 rh0, %ctaid.x;
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; CHECK-NEXT: ret;
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%x = call i16 @llvm.ptx.read.ctaid.x()
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ret i16 %x
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}
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define ptx_device i16 @ctaid_y() {
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; CHECK: mov.u16 rh0, ctaid.y;
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define ptx_device i16 @test_ctaid_y() {
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; CHECK: mov.u16 rh0, %ctaid.y;
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; CHECK-NEXT: ret;
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%x = call i16 @llvm.ptx.read.ctaid.y()
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ret i16 %x
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}
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define ptx_device i16 @ctaid_z() {
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; CHECK: mov.u16 rh0, ctaid.z;
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define ptx_device i16 @test_ctaid_z() {
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; CHECK: mov.u16 rh0, %ctaid.z;
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; CHECK-NEXT: ret;
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%x = call i16 @llvm.ptx.read.ctaid.z()
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ret i16 %x
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}
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define ptx_device i16 @ctaid_w() {
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; CHECK: mov.u16 rh0, ctaid.w;
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define ptx_device i16 @test_ctaid_w() {
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; CHECK: mov.u16 rh0, %ctaid.w;
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; CHECK-NEXT: ret;
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%x = call i16 @llvm.ptx.read.ctaid.w()
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ret i16 %x
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}
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define ptx_device i16 @nctaid_x() {
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; CHECK: mov.u16 rh0, nctaid.x;
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define ptx_device i16 @test_nctaid_x() {
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; CHECK: mov.u16 rh0, %nctaid.x;
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; CHECK-NEXT: ret;
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%x = call i16 @llvm.ptx.read.nctaid.x()
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ret i16 %x
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}
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define ptx_device i16 @nctaid_y() {
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; CHECK: mov.u16 rh0, nctaid.y;
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define ptx_device i16 @test_nctaid_y() {
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; CHECK: mov.u16 rh0, %nctaid.y;
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; CHECK-NEXT: ret;
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%x = call i16 @llvm.ptx.read.nctaid.y()
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ret i16 %x
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}
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define ptx_device i16 @nctaid_z() {
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; CHECK: mov.u16 rh0, nctaid.z;
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define ptx_device i16 @test_nctaid_z() {
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; CHECK: mov.u16 rh0, %nctaid.z;
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; CHECK-NEXT: ret;
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%x = call i16 @llvm.ptx.read.nctaid.z()
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ret i16 %x
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}
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define ptx_device i16 @nctaid_w() {
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; CHECK: mov.u16 rh0, nctaid.w;
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define ptx_device i16 @test_nctaid_w() {
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; CHECK: mov.u16 rh0, %nctaid.w;
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; CHECK-NEXT: ret;
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%x = call i16 @llvm.ptx.read.nctaid.w()
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ret i16 %x
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}
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define ptx_device void @bar_sync() {
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define ptx_device i32 @test_smid() {
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; CHECK: mov.u32 r0, %smid;
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; CHECK-NEXT: ret;
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%x = call i32 @llvm.ptx.read.smid()
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ret i32 %x
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}
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define ptx_device i32 @test_nsmid() {
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; CHECK: mov.u32 r0, %nsmid;
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; CHECK-NEXT: ret;
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%x = call i32 @llvm.ptx.read.nsmid()
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ret i32 %x
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}
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define ptx_device i32 @test_gridid() {
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; CHECK: mov.u32 r0, %gridid;
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; CHECK-NEXT: ret;
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%x = call i32 @llvm.ptx.read.gridid()
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ret i32 %x
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}
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define ptx_device i32 @test_lanemask_eq() {
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; CHECK: mov.u32 r0, %lanemask_eq;
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; CHECK-NEXT: ret;
|
||||
%x = call i32 @llvm.ptx.read.lanemask.eq()
|
||||
ret i32 %x
|
||||
}
|
||||
|
||||
define ptx_device i32 @test_lanemask_le() {
|
||||
; CHECK: mov.u32 r0, %lanemask_le;
|
||||
; CHECK-NEXT: ret;
|
||||
%x = call i32 @llvm.ptx.read.lanemask.le()
|
||||
ret i32 %x
|
||||
}
|
||||
|
||||
define ptx_device i32 @test_lanemask_lt() {
|
||||
; CHECK: mov.u32 r0, %lanemask_lt;
|
||||
; CHECK-NEXT: ret;
|
||||
%x = call i32 @llvm.ptx.read.lanemask.lt()
|
||||
ret i32 %x
|
||||
}
|
||||
|
||||
define ptx_device i32 @test_lanemask_ge() {
|
||||
; CHECK: mov.u32 r0, %lanemask_ge;
|
||||
; CHECK-NEXT: ret;
|
||||
%x = call i32 @llvm.ptx.read.lanemask.ge()
|
||||
ret i32 %x
|
||||
}
|
||||
|
||||
define ptx_device i32 @test_lanemask_gt() {
|
||||
; CHECK: mov.u32 r0, %lanemask_gt;
|
||||
; CHECK-NEXT: ret;
|
||||
%x = call i32 @llvm.ptx.read.lanemask.gt()
|
||||
ret i32 %x
|
||||
}
|
||||
|
||||
define ptx_device i32 @test_clock() {
|
||||
; CHECK: mov.u32 r0, %clock;
|
||||
; CHECK-NEXT: ret;
|
||||
%x = call i32 @llvm.ptx.read.clock()
|
||||
ret i32 %x
|
||||
}
|
||||
|
||||
define ptx_device i64 @test_clock64() {
|
||||
; CHECK: mov.u64 rd0, %clock64;
|
||||
; CHECK-NEXT: ret;
|
||||
%x = call i64 @llvm.ptx.read.clock64()
|
||||
ret i64 %x
|
||||
}
|
||||
|
||||
define ptx_device i32 @test_pm0() {
|
||||
; CHECK: mov.u32 r0, %pm0;
|
||||
; CHECK-NEXT: ret;
|
||||
%x = call i32 @llvm.ptx.read.pm0()
|
||||
ret i32 %x
|
||||
}
|
||||
|
||||
define ptx_device i32 @test_pm1() {
|
||||
; CHECK: mov.u32 r0, %pm1;
|
||||
; CHECK-NEXT: ret;
|
||||
%x = call i32 @llvm.ptx.read.pm1()
|
||||
ret i32 %x
|
||||
}
|
||||
|
||||
define ptx_device i32 @test_pm2() {
|
||||
; CHECK: mov.u32 r0, %pm2;
|
||||
; CHECK-NEXT: ret;
|
||||
%x = call i32 @llvm.ptx.read.pm2()
|
||||
ret i32 %x
|
||||
}
|
||||
|
||||
define ptx_device i32 @test_pm3() {
|
||||
; CHECK: mov.u32 r0, %pm3;
|
||||
; CHECK-NEXT: ret;
|
||||
%x = call i32 @llvm.ptx.read.pm3()
|
||||
ret i32 %x
|
||||
}
|
||||
|
||||
define ptx_device void @test_bar_sync() {
|
||||
; CHECK: bar.sync 0
|
||||
; CHECK-NEXT: ret;
|
||||
call void @llvm.ptx.bar.sync(i32 0)
|
||||
@ -127,6 +246,11 @@ declare i16 @llvm.ptx.read.ntid.x()
|
||||
declare i16 @llvm.ptx.read.ntid.y()
|
||||
declare i16 @llvm.ptx.read.ntid.z()
|
||||
declare i16 @llvm.ptx.read.ntid.w()
|
||||
|
||||
declare i32 @llvm.ptx.read.laneid()
|
||||
declare i32 @llvm.ptx.read.warpid()
|
||||
declare i32 @llvm.ptx.read.nwarpid()
|
||||
|
||||
declare i16 @llvm.ptx.read.ctaid.x()
|
||||
declare i16 @llvm.ptx.read.ctaid.y()
|
||||
declare i16 @llvm.ptx.read.ctaid.z()
|
||||
@ -136,4 +260,22 @@ declare i16 @llvm.ptx.read.nctaid.y()
|
||||
declare i16 @llvm.ptx.read.nctaid.z()
|
||||
declare i16 @llvm.ptx.read.nctaid.w()
|
||||
|
||||
declare i32 @llvm.ptx.read.smid()
|
||||
declare i32 @llvm.ptx.read.nsmid()
|
||||
declare i32 @llvm.ptx.read.gridid()
|
||||
|
||||
declare i32 @llvm.ptx.read.lanemask.eq()
|
||||
declare i32 @llvm.ptx.read.lanemask.le()
|
||||
declare i32 @llvm.ptx.read.lanemask.lt()
|
||||
declare i32 @llvm.ptx.read.lanemask.ge()
|
||||
declare i32 @llvm.ptx.read.lanemask.gt()
|
||||
|
||||
declare i32 @llvm.ptx.read.clock()
|
||||
declare i64 @llvm.ptx.read.clock64()
|
||||
|
||||
declare i32 @llvm.ptx.read.pm0()
|
||||
declare i32 @llvm.ptx.read.pm1()
|
||||
declare i32 @llvm.ptx.read.pm2()
|
||||
declare i32 @llvm.ptx.read.pm3()
|
||||
|
||||
declare void @llvm.ptx.bar.sync(i32 %i)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user