From fc73640f83563eafd9c1b46d2a736cd5d9c2254e Mon Sep 17 00:00:00 2001 From: Evan Cheng Date: Wed, 10 Dec 2008 21:54:21 +0000 Subject: [PATCH] Preliminary ARM debug support based on patch by Mikael of FlexyCore. llvm-svn: 60851 --- lib/Target/ARM/ARMISelDAGToDAG.cpp | 40 +++++++++++++++++++-- lib/Target/ARM/ARMInstrInfo.cpp | 14 ++++++-- lib/Target/ARM/ARMRegisterInfo.cpp | 3 +- lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp | 20 ++++------- 4 files changed, 57 insertions(+), 20 deletions(-) diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp index ac3abe670a4..537f6faf788 100644 --- a/lib/Target/ARM/ARMISelDAGToDAG.cpp +++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp @@ -12,9 +12,10 @@ //===----------------------------------------------------------------------===// #include "ARM.h" +#include "ARMAddressingModes.h" +#include "ARMConstantPoolValue.h" #include "ARMISelLowering.h" #include "ARMTargetMachine.h" -#include "ARMAddressingModes.h" #include "llvm/CallingConv.h" #include "llvm/Constants.h" #include "llvm/DerivedTypes.h" @@ -821,11 +822,46 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) { break; case MVT::f64: Opc = ARM::FNEGDcc; - break; + break; } return CurDAG->SelectNodeTo(Op.getNode(), Opc, VT, Ops, 5); } + + case ISD::DECLARE: { + SDValue Chain = Op.getOperand(0); + SDValue N1 = Op.getOperand(1); + SDValue N2 = Op.getOperand(2); + FrameIndexSDNode *FINode = dyn_cast(N1); + if (!FINode) + break; + if (N2.getOpcode() == ARMISD::PIC_ADD && isa(N2.getOperand(0))) + N2 = N2.getOperand(0); + LoadSDNode *Ld = dyn_cast(N2); + if (!Ld) + break; + SDValue BasePtr = Ld->getBasePtr(); + assert(BasePtr.getOpcode() == ARMISD::Wrapper && + isa(BasePtr.getOperand(0)) && + "llvm.dbg.variable should be a constantpool node"); + ConstantPoolSDNode *CP = cast(BasePtr.getOperand(0)); + GlobalValue *GV = 0; + if (CP->isMachineConstantPoolEntry()) { + ARMConstantPoolValue *ACPV = (ARMConstantPoolValue*)CP->getMachineCPVal(); + GV = ACPV->getGV(); + } else + GV = dyn_cast(CP->getConstVal()); + if (GV) { + SDValue Tmp1 = CurDAG->getTargetFrameIndex(FINode->getIndex(), + TLI.getPointerTy()); + SDValue Tmp2 = CurDAG->getTargetGlobalAddress(GV, TLI.getPointerTy()); + SDValue Ops[] = { Tmp1, Tmp2, Chain }; + return CurDAG->getTargetNode(TargetInstrInfo::DECLARE, + MVT::Other, Ops, 3); + } + break; } + } + return SelectCode(Op); } diff --git a/lib/Target/ARM/ARMInstrInfo.cpp b/lib/Target/ARM/ARMInstrInfo.cpp index a809a93bb77..bd16af05bf0 100644 --- a/lib/Target/ARM/ARMInstrInfo.cpp +++ b/lib/Target/ARM/ARMInstrInfo.cpp @@ -900,16 +900,24 @@ unsigned ARMInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const { unsigned TSFlags = TID.TSFlags; switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) { - default: + default: { // If this machine instr is an inline asm, measure it. if (MI->getOpcode() == ARM::INLINEASM) return TAI->getInlineAsmLength(MI->getOperand(0).getSymbolName()); if (MI->isLabel()) return 0; - if (MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF) + switch (MI->getOpcode()) { + default: + assert(0 && "Unknown or unset size field for instr!"); + break; + case TargetInstrInfo::IMPLICIT_DEF: + case TargetInstrInfo::DECLARE: + case TargetInstrInfo::DBG_LABEL: + case TargetInstrInfo::EH_LABEL: return 0; - assert(0 && "Unknown or unset size field for instr!"); + } break; + } case ARMII::Size8Bytes: return 8; // Arm instruction x 2. case ARMII::Size4Bytes: return 4; // Arm instruction. case ARMII::Size2Bytes: return 2; // Thumb instruction. diff --git a/lib/Target/ARM/ARMRegisterInfo.cpp b/lib/Target/ARM/ARMRegisterInfo.cpp index cd5f321f98b..df0d98b5c2c 100644 --- a/lib/Target/ARM/ARMRegisterInfo.cpp +++ b/lib/Target/ARM/ARMRegisterInfo.cpp @@ -1455,8 +1455,7 @@ unsigned ARMRegisterInfo::getEHHandlerRegister() const { } int ARMRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const { - assert(0 && "What is the dwarf register number"); - return -1; + return ARMGenRegisterInfo::getDwarfRegNumFull(RegNum, 0); } #include "ARMGenRegisterInfo.inc" diff --git a/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp b/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp index f44b9a1cee7..97b4a1ba7ca 100644 --- a/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp +++ b/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp @@ -231,8 +231,7 @@ bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) { O << CurrentFnName << ":\n"; // Emit pre-function debug information. - // FIXME: Dwarf support. - //DW.BeginFunction(&MF); + DW.BeginFunction(&MF); if (Subtarget->isTargetDarwin()) { // If the function is empty, then we need to emit *something*. Otherwise, @@ -263,8 +262,7 @@ bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) { O << "\t.size " << CurrentFnName << ", .-" << CurrentFnName << "\n"; // Emit post-function debug information. - // FIXME: Dwarf support. - //DW.EndFunction(); + DW.EndFunction(&MF); O.flush(); @@ -779,16 +777,14 @@ void ARMAsmPrinter::printMachineInstruction(const MachineInstr *MI) { bool ARMAsmPrinter::doInitialization(Module &M) { // Emit initial debug information. - // FIXME: Dwarf support. - //DW.BeginModule(&M); - + DW.BeginModule(&M); + bool Result = AsmPrinter::doInitialization(M); // AsmPrinter::doInitialization should have done this analysis. MMI = getAnalysisToUpdate(); assert(MMI); - // FIXME: Dwarf support. - //DW.SetModuleInfo(MMI); + DW.SetModuleInfo(MMI); // Darwin wants symbols to be quoted if they have complex names. if (Subtarget->isTargetDarwin()) @@ -1016,8 +1012,7 @@ bool ARMAsmPrinter::doFinalization(Module &M) { // Emit initial debug information. - // FIXME: Dwarf support. - //DW.EndModule(); + DW.EndModule(); // Funny Darwin hack: This flag tells the linker that no global symbols // contain code that falls through to other global symbols (e.g. the obvious @@ -1027,8 +1022,7 @@ bool ARMAsmPrinter::doFinalization(Module &M) { O << "\t.subsections_via_symbols\n"; } else { // Emit final debug information for ELF. - // FIXME: Dwarf support. - //DW.EndModule(); + DW.EndModule(); } return AsmPrinter::doFinalization(M);