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[AArch64] Improve single vector lane stores
When storing the 0th lane of a vector, use a simpler and usually more efficient scalar store instead. Differential revision: https://reviews.llvm.org/D46655 llvm-svn: 332251
This commit is contained in:
Evandro Menezes
parent
c6b21b2d69
commit
fca3a5cdd4
@ -2249,12 +2249,11 @@ multiclass VecROStoreLane0Pat<ROAddrMode ro, SDPatternOperator storeop,
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let AddedComplexity = 19 in {
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defm : VecROStoreLane0Pat<ro16, truncstorei16, v8i16, i32, hsub, STRHroW, STRHroX>;
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defm : VecROStoreLane0Pat<ro16, store , v8i16, i16, hsub, STRHroW, STRHroX>;
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defm : VecROStoreLane0Pat<ro32, truncstorei32, v4i32, i32, ssub, STRSroW, STRSroX>;
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defm : VecROStoreLane0Pat<ro32, store , v4i32, i32, ssub, STRSroW, STRSroX>;
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defm : VecROStoreLane0Pat<ro32, store , v4f32, f32, ssub, STRSroW, STRSroX>;
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defm : VecROStoreLane0Pat<ro64, store , v2i64, i64, dsub, STRDroW, STRDroX>;
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defm : VecROStoreLane0Pat<ro64, store , v2f64, f64, dsub, STRDroW, STRDroX>;
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defm : VecROStoreLane0Pat<ro16, store, v8f16, f16, hsub, STRHroW, STRHroX>;
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defm : VecROStoreLane0Pat<ro32, store, v4i32, i32, ssub, STRSroW, STRSroX>;
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defm : VecROStoreLane0Pat<ro32, store, v4f32, f32, ssub, STRSroW, STRSroX>;
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defm : VecROStoreLane0Pat<ro64, store, v2i64, i64, dsub, STRDroW, STRDroX>;
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defm : VecROStoreLane0Pat<ro64, store, v2f64, f64, dsub, STRDroW, STRDroX>;
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}
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//---
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@ -2288,8 +2287,16 @@ defm STRBB : StoreUIz<0b00, 0, 0b00, GPR32z, uimm12s1, "strb",
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(am_indexed8 GPR64sp:$Rn,
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uimm12s1:$offset))]>;
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// Match all store 64 bits width whose type is compatible with FPR64
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let AddedComplexity = 10 in {
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// Match all store 64 bits width whose type is compatible with FPR64
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def : Pat<(store (v1i64 FPR64:$Rt),
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(am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
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(STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
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def : Pat<(store (v1f64 FPR64:$Rt),
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(am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
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(STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
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let Predicates = [IsLE] in {
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// We must use ST1 to store vectors in big-endian.
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def : Pat<(store (v2f32 FPR64:$Rt),
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@ -2308,14 +2315,12 @@ let Predicates = [IsLE] in {
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(am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
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(STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
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}
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def : Pat<(store (v1f64 FPR64:$Rt),
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(am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
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(STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
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def : Pat<(store (v1i64 FPR64:$Rt),
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(am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
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(STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
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// Match all store 128 bits width whose type is compatible with FPR128
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def : Pat<(store (f128 FPR128:$Rt),
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(am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
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(STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
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let Predicates = [IsLE] in {
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// We must use ST1 to store vectors in big-endian.
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def : Pat<(store (v4f32 FPR128:$Rt),
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@ -2340,9 +2345,6 @@ let Predicates = [IsLE] in {
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(am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
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(STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
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}
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def : Pat<(store (f128 FPR128:$Rt),
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(am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
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(STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
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// truncstore i64
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def : Pat<(truncstorei32 GPR64:$Rt,
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@ -2356,6 +2358,26 @@ def : Pat<(truncstorei8 GPR64:$Rt, (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset)),
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} // AddedComplexity = 10
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// Match stores from lane 0 to the appropriate subreg's store.
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multiclass VecStoreLane0Pat<Operand UIAddrMode, SDPatternOperator storeop,
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ValueType VTy, ValueType STy,
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SubRegIndex SubRegIdx, Operand IndexType,
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Instruction STR> {
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def : Pat<(storeop (STy (vector_extract (VTy VecListOne128:$Vt), 0)),
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(UIAddrMode GPR64sp:$Rn, IndexType:$offset)),
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(STR (EXTRACT_SUBREG VecListOne128:$Vt, SubRegIdx),
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GPR64sp:$Rn, IndexType:$offset)>;
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}
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let AddedComplexity = 19 in {
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defm : VecStoreLane0Pat<am_indexed16, truncstorei16, v8i16, i32, hsub, uimm12s2, STRHui>;
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defm : VecStoreLane0Pat<am_indexed16, store, v8f16, f16, hsub, uimm12s2, STRHui>;
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defm : VecStoreLane0Pat<am_indexed32, store, v4i32, i32, ssub, uimm12s4, STRSui>;
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defm : VecStoreLane0Pat<am_indexed32, store, v4f32, f32, ssub, uimm12s4, STRSui>;
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defm : VecStoreLane0Pat<am_indexed64, store, v2i64, i64, dsub, uimm12s8, STRDui>;
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defm : VecStoreLane0Pat<am_indexed64, store, v2f64, f64, dsub, uimm12s8, STRDui>;
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}
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//---
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// (unscaled immediate)
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defm STURX : StoreUnscaled<0b11, 0, 0b00, GPR64z, "stur",
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@ -2387,6 +2409,13 @@ defm STURBB : StoreUnscaled<0b00, 0, 0b00, GPR32z, "sturb",
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(am_unscaled8 GPR64sp:$Rn, simm9:$offset))]>;
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// Match all store 64 bits width whose type is compatible with FPR64
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def : Pat<(store (v1f64 FPR64:$Rt), (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
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(STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
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def : Pat<(store (v1i64 FPR64:$Rt), (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
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(STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
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let AddedComplexity = 10 in {
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let Predicates = [IsLE] in {
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// We must use ST1 to store vectors in big-endian.
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def : Pat<(store (v2f32 FPR64:$Rt),
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@ -2405,12 +2434,11 @@ let Predicates = [IsLE] in {
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(am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
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(STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
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}
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def : Pat<(store (v1f64 FPR64:$Rt), (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
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(STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
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def : Pat<(store (v1i64 FPR64:$Rt), (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
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(STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
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// Match all store 128 bits width whose type is compatible with FPR128
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def : Pat<(store (f128 FPR128:$Rt), (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
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(STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
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let Predicates = [IsLE] in {
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// We must use ST1 to store vectors in big-endian.
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def : Pat<(store (v4f32 FPR128:$Rt),
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@ -2439,6 +2467,8 @@ let Predicates = [IsLE] in {
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(STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
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}
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} // AddedComplexity = 10
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// unscaled i64 truncating stores
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def : Pat<(truncstorei32 GPR64:$Rt, (am_unscaled32 GPR64sp:$Rn, simm9:$offset)),
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(STURWi (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, simm9:$offset)>;
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@ -4151,12 +4181,18 @@ def : Pat<(v4i16 (scalar_to_vector GPR32:$Rn)),
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(SUBREG_TO_REG (i32 0),
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(f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
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def : Pat<(v4f16 (scalar_to_vector (f16 FPR16:$Rn))),
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(INSERT_SUBREG (v4f16 (IMPLICIT_DEF)), FPR16:$Rn, hsub)>;
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def : Pat<(v8f16 (scalar_to_vector (f16 FPR16:$Rn))),
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(INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), FPR16:$Rn, hsub)>;
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def : Pat<(v2i32 (scalar_to_vector (i32 FPR32:$Rn))),
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(v2i32 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
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(i32 FPR32:$Rn), ssub))>;
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def : Pat<(v4i32 (scalar_to_vector (i32 FPR32:$Rn))),
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(v4i32 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
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(i32 FPR32:$Rn), ssub))>;
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def : Pat<(v2i64 (scalar_to_vector (i64 FPR64:$Rn))),
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(v2i64 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)),
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(i64 FPR64:$Rn), dsub))>;
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@ -4170,6 +4206,7 @@ def : Pat<(v4f32 (scalar_to_vector (f32 FPR32:$Rn))),
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(INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rn, ssub)>;
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def : Pat<(v2f32 (scalar_to_vector (f32 FPR32:$Rn))),
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(INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), FPR32:$Rn, ssub)>;
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def : Pat<(v2f64 (scalar_to_vector (f64 FPR64:$Rn))),
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(INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$Rn, dsub)>;
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@ -925,7 +925,7 @@ define <4 x i16> @test_extracts_inserts_varidx_extract(<8 x i16> %x, i32 %idx) {
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; CHECK-LABEL: test_extracts_inserts_varidx_insert:
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; CHECK: and [[MASKED_IDX:x[0-9]+]], x0, #0x3
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; CHECK: bfi x9, [[MASKED_IDX]], #1, #2
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; CHECK: st1 { v0.h }[0], [x9]
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; CHECK: str h0, [x9]
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; CHECK-DAG: ldr d[[R:[0-9]+]]
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; CHECK-DAG: mov v[[R]].h[1], v0.h[1]
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; CHECK-DAG: mov v[[R]].h[2], v0.h[2]
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@ -391,6 +391,15 @@ entry:
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ret void
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}
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define void @test_vst1q_lane0_s16(i16* %a, <8 x i16> %b) {
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; CHECK-LABEL: test_vst1q_lane0_s16:
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; CHECK: str {{h[0-9]+}}, [x0]
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entry:
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%0 = extractelement <8 x i16> %b, i32 0
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store i16 %0, i16* %a, align 2
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ret void
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}
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define void @test_vst1q_lane_s32(i32* %a, <4 x i32> %b) {
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; CHECK-LABEL: test_vst1q_lane_s32:
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; CHECK: st1 { {{v[0-9]+}}.s }[{{[0-9]+}}], [x0]
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@ -400,6 +409,15 @@ entry:
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ret void
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}
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define void @test_vst1q_lane0_s32(i32* %a, <4 x i32> %b) {
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; CHECK-LABEL: test_vst1q_lane0_s32:
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; CHECK: str {{s[0-9]+}}, [x0]
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entry:
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%0 = extractelement <4 x i32> %b, i32 0
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store i32 %0, i32* %a, align 4
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ret void
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}
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define void @test_vst1q_lane_s64(i64* %a, <2 x i64> %b) {
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; CHECK-LABEL: test_vst1q_lane_s64:
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; CHECK: st1 { {{v[0-9]+}}.d }[{{[0-9]+}}], [x0]
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@ -409,6 +427,15 @@ entry:
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ret void
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}
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define void @test_vst1q_lane0_s64(i64* %a, <2 x i64> %b) {
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; CHECK-LABEL: test_vst1q_lane0_s64:
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; CHECK: str {{d[0-9]+}}, [x0]
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entry:
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%0 = extractelement <2 x i64> %b, i32 0
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store i64 %0, i64* %a, align 8
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ret void
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}
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define void @test_vst1q_lane_f32(float* %a, <4 x float> %b) {
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; CHECK-LABEL: test_vst1q_lane_f32:
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; CHECK: st1 { {{v[0-9]+}}.s }[{{[0-9]+}}], [x0]
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@ -418,6 +445,15 @@ entry:
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ret void
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}
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define void @test_vst1q_lane0_f32(float* %a, <4 x float> %b) {
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; CHECK-LABEL: test_vst1q_lane0_f32:
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; CHECK: str {{s[0-9]+}}, [x0]
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entry:
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%0 = extractelement <4 x float> %b, i32 0
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store float %0, float* %a, align 4
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ret void
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}
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define void @test_vst1q_lane_f64(double* %a, <2 x double> %b) {
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; CHECK-LABEL: test_vst1q_lane_f64:
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; CHECK: st1 { {{v[0-9]+}}.d }[{{[0-9]+}}], [x0]
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@ -427,6 +463,15 @@ entry:
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ret void
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}
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define void @test_vst1q_lane0_f64(double* %a, <2 x double> %b) {
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; CHECK-LABEL: test_vst1q_lane0_f64:
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; CHECK: str {{d[0-9]+}}, [x0]
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entry:
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%0 = extractelement <2 x double> %b, i32 0
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store double %0, double* %a, align 8
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ret void
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}
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define void @test_vst1_lane_s8(i8* %a, <8 x i8> %b) {
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; CHECK-LABEL: test_vst1_lane_s8:
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; CHECK: st1 { {{v[0-9]+}}.b }[{{[0-9]+}}], [x0]
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@ -445,6 +490,15 @@ entry:
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ret void
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}
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define void @test_vst1_lane0_s16(i16* %a, <4 x i16> %b) {
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; CHECK-LABEL: test_vst1_lane0_s16:
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; CHECK: str {{h[0-9]+}}, [x0]
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entry:
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%0 = extractelement <4 x i16> %b, i32 0
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store i16 %0, i16* %a, align 2
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ret void
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}
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define void @test_vst1_lane_s32(i32* %a, <2 x i32> %b) {
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; CHECK-LABEL: test_vst1_lane_s32:
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; CHECK: st1 { {{v[0-9]+}}.s }[{{[0-9]+}}], [x0]
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@ -454,9 +508,18 @@ entry:
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ret void
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}
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define void @test_vst1_lane0_s32(i32* %a, <2 x i32> %b) {
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; CHECK-LABEL: test_vst1_lane0_s32:
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; CHECK: str {{s[0-9]+}}, [x0]
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entry:
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%0 = extractelement <2 x i32> %b, i32 0
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store i32 %0, i32* %a, align 4
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ret void
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}
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define void @test_vst1_lane_s64(i64* %a, <1 x i64> %b) {
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; CHECK-LABEL: test_vst1_lane_s64:
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; CHECK: st1 { {{v[0-9]+}}.d }[{{[0-9]+}}], [x0]
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; CHECK: str {{d[0-9]+}}, [x0]
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entry:
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%0 = extractelement <1 x i64> %b, i32 0
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store i64 %0, i64* %a, align 8
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@ -472,6 +535,15 @@ entry:
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ret void
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}
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define void @test_vst1_lane0_f32(float* %a, <2 x float> %b) {
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; CHECK-LABEL: test_vst1_lane0_f32:
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; CHECK: str {{s[0-9]+}}, [x0]
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entry:
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%0 = extractelement <2 x float> %b, i32 0
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store float %0, float* %a, align 4
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ret void
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}
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define void @test_vst1_lane_f64(double* %a, <1 x double> %b) {
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; CHECK-LABEL: test_vst1_lane_f64:
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; CHECK: str {{d[0-9]+}}, [x0]
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@ -10,6 +10,23 @@ define void @st1lane_16b(<16 x i8> %A, i8* %D) {
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ret void
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}
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define void @st1lane0_16b(<16 x i8> %A, i8* %D) {
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; CHECK-LABEL: st1lane0_16b
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; CHECK: st1.b
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%tmp = extractelement <16 x i8> %A, i32 0
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store i8 %tmp, i8* %D
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ret void
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}
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define void @st1lane0u_16b(<16 x i8> %A, i8* %D) {
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; CHECK-LABEL: st1lane0u_16b
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; CHECK: st1.b
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%ptr = getelementptr i8, i8* %D, i64 -1
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%tmp = extractelement <16 x i8> %A, i32 0
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store i8 %tmp, i8* %ptr
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ret void
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}
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define void @st1lane_ro_16b(<16 x i8> %A, i8* %D, i64 %offset) {
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; CHECK-LABEL: st1lane_ro_16b
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; CHECK: add x[[XREG:[0-9]+]], x0, x1
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@ -38,6 +55,23 @@ define void @st1lane_8h(<8 x i16> %A, i16* %D) {
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ret void
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}
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define void @st1lane0_8h(<8 x i16> %A, i16* %D) {
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; CHECK-LABEL: st1lane0_8h
|
||||
; CHECK: str
|
||||
%tmp = extractelement <8 x i16> %A, i32 0
|
||||
store i16 %tmp, i16* %D
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @st1lane0u_8h(<8 x i16> %A, i16* %D) {
|
||||
; CHECK-LABEL: st1lane0u_8h
|
||||
; CHECK: st1.h
|
||||
%ptr = getelementptr i16, i16* %D, i64 -1
|
||||
%tmp = extractelement <8 x i16> %A, i32 0
|
||||
store i16 %tmp, i16* %ptr
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @st1lane_ro_8h(<8 x i16> %A, i16* %D, i64 %offset) {
|
||||
; CHECK-LABEL: st1lane_ro_8h
|
||||
; CHECK: add x[[XREG:[0-9]+]], x0, x1
|
||||
@ -65,6 +99,23 @@ define void @st1lane_4s(<4 x i32> %A, i32* %D) {
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @st1lane0_4s(<4 x i32> %A, i32* %D) {
|
||||
; CHECK-LABEL: st1lane0_4s
|
||||
; CHECK: str
|
||||
%tmp = extractelement <4 x i32> %A, i32 0
|
||||
store i32 %tmp, i32* %D
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @st1lane0u_4s(<4 x i32> %A, i32* %D) {
|
||||
; CHECK-LABEL: st1lane0u_4s
|
||||
; CHECK: st1.s
|
||||
%ptr = getelementptr i32, i32* %D, i64 -1
|
||||
%tmp = extractelement <4 x i32> %A, i32 0
|
||||
store i32 %tmp, i32* %ptr
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @st1lane_ro_4s(<4 x i32> %A, i32* %D, i64 %offset) {
|
||||
; CHECK-LABEL: st1lane_ro_4s
|
||||
; CHECK: add x[[XREG:[0-9]+]], x0, x1
|
||||
@ -92,6 +143,23 @@ define void @st1lane_4s_float(<4 x float> %A, float* %D) {
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @st1lane0_4s_float(<4 x float> %A, float* %D) {
|
||||
; CHECK-LABEL: st1lane0_4s_float
|
||||
; CHECK: str
|
||||
%tmp = extractelement <4 x float> %A, i32 0
|
||||
store float %tmp, float* %D
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @st1lane0u_4s_float(<4 x float> %A, float* %D) {
|
||||
; CHECK-LABEL: st1lane0u_4s_float
|
||||
; CHECK: st1.s
|
||||
%ptr = getelementptr float, float* %D, i64 -1
|
||||
%tmp = extractelement <4 x float> %A, i32 0
|
||||
store float %tmp, float* %ptr
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @st1lane_ro_4s_float(<4 x float> %A, float* %D, i64 %offset) {
|
||||
; CHECK-LABEL: st1lane_ro_4s_float
|
||||
; CHECK: add x[[XREG:[0-9]+]], x0, x1
|
||||
@ -119,6 +187,23 @@ define void @st1lane_2d(<2 x i64> %A, i64* %D) {
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @st1lane0_2d(<2 x i64> %A, i64* %D) {
|
||||
; CHECK-LABEL: st1lane0_2d
|
||||
; CHECK: str
|
||||
%tmp = extractelement <2 x i64> %A, i32 0
|
||||
store i64 %tmp, i64* %D
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @st1lane0u_2d(<2 x i64> %A, i64* %D) {
|
||||
; CHECK-LABEL: st1lane0u_2d
|
||||
; CHECK: st1.d
|
||||
%ptr = getelementptr i64, i64* %D, i64 -1
|
||||
%tmp = extractelement <2 x i64> %A, i32 0
|
||||
store i64 %tmp, i64* %ptr
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @st1lane_ro_2d(<2 x i64> %A, i64* %D, i64 %offset) {
|
||||
; CHECK-LABEL: st1lane_ro_2d
|
||||
; CHECK: add x[[XREG:[0-9]+]], x0, x1
|
||||
@ -146,6 +231,23 @@ define void @st1lane_2d_double(<2 x double> %A, double* %D) {
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @st1lane0_2d_double(<2 x double> %A, double* %D) {
|
||||
; CHECK-LABEL: st1lane0_2d_double
|
||||
; CHECK: str
|
||||
%tmp = extractelement <2 x double> %A, i32 0
|
||||
store double %tmp, double* %D
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @st1lane0u_2d_double(<2 x double> %A, double* %D) {
|
||||
; CHECK-LABEL: st1lane0u_2d_double
|
||||
; CHECK: st1.d
|
||||
%ptr = getelementptr double, double* %D, i64 -1
|
||||
%tmp = extractelement <2 x double> %A, i32 0
|
||||
store double %tmp, double* %ptr
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @st1lane_ro_2d_double(<2 x double> %A, double* %D, i64 %offset) {
|
||||
; CHECK-LABEL: st1lane_ro_2d_double
|
||||
; CHECK: add x[[XREG:[0-9]+]], x0, x1
|
||||
@ -201,6 +303,23 @@ define void @st1lane_4h(<4 x i16> %A, i16* %D) {
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @st1lane0_4h(<4 x i16> %A, i16* %D) {
|
||||
; CHECK-LABEL: st1lane0_4h
|
||||
; CHECK: str
|
||||
%tmp = extractelement <4 x i16> %A, i32 0
|
||||
store i16 %tmp, i16* %D
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @st1lane0u_4h(<4 x i16> %A, i16* %D) {
|
||||
; CHECK-LABEL: st1lane0u_4h
|
||||
; CHECK: st1.h
|
||||
%ptr = getelementptr i16, i16* %D, i64 -1
|
||||
%tmp = extractelement <4 x i16> %A, i32 0
|
||||
store i16 %tmp, i16* %ptr
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @st1lane_ro_4h(<4 x i16> %A, i16* %D, i64 %offset) {
|
||||
; CHECK-LABEL: st1lane_ro_4h
|
||||
; CHECK: add x[[XREG:[0-9]+]], x0, x1
|
||||
@ -228,6 +347,23 @@ define void @st1lane_2s(<2 x i32> %A, i32* %D) {
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @st1lane0_2s(<2 x i32> %A, i32* %D) {
|
||||
; CHECK-LABEL: st1lane0_2s
|
||||
; CHECK: str
|
||||
%tmp = extractelement <2 x i32> %A, i32 0
|
||||
store i32 %tmp, i32* %D
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @st1lane0u_2s(<2 x i32> %A, i32* %D) {
|
||||
; CHECK-LABEL: st1lane0u_2s
|
||||
; CHECK: st1.s
|
||||
%ptr = getelementptr i32, i32* %D, i64 -1
|
||||
%tmp = extractelement <2 x i32> %A, i32 0
|
||||
store i32 %tmp, i32* %ptr
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @st1lane_ro_2s(<2 x i32> %A, i32* %D, i64 %offset) {
|
||||
; CHECK-LABEL: st1lane_ro_2s
|
||||
; CHECK: add x[[XREG:[0-9]+]], x0, x1
|
||||
@ -255,6 +391,23 @@ define void @st1lane_2s_float(<2 x float> %A, float* %D) {
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @st1lane0_2s_float(<2 x float> %A, float* %D) {
|
||||
; CHECK-LABEL: st1lane0_2s_float
|
||||
; CHECK: str
|
||||
%tmp = extractelement <2 x float> %A, i32 0
|
||||
store float %tmp, float* %D
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @st1lane0u_2s_float(<2 x float> %A, float* %D) {
|
||||
; CHECK-LABEL: st1lane0u_2s_float
|
||||
; CHECK: st1.s
|
||||
%ptr = getelementptr float, float* %D, i64 -1
|
||||
%tmp = extractelement <2 x float> %A, i32 0
|
||||
store float %tmp, float* %ptr
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @st1lane_ro_2s_float(<2 x float> %A, float* %D, i64 %offset) {
|
||||
; CHECK-LABEL: st1lane_ro_2s_float
|
||||
; CHECK: add x[[XREG:[0-9]+]], x0, x1
|
||||
@ -274,6 +427,58 @@ define void @st1lane0_ro_2s_float(<2 x float> %A, float* %D, i64 %offset) {
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @st1lane0_1d(<1 x i64> %A, i64* %D) {
|
||||
; CHECK-LABEL: st1lane0_1d
|
||||
; CHECK: str
|
||||
%tmp = extractelement <1 x i64> %A, i32 0
|
||||
store i64 %tmp, i64* %D
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @st1lane0u_1d(<1 x i64> %A, i64* %D) {
|
||||
; CHECK-LABEL: st1lane0u_1d
|
||||
; CHECK: st1.d
|
||||
%ptr = getelementptr i64, i64* %D, i64 -1
|
||||
%tmp = extractelement <1 x i64> %A, i32 0
|
||||
store i64 %tmp, i64* %ptr
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @st1lane0_ro_1d(<1 x i64> %A, i64* %D, i64 %offset) {
|
||||
; CHECK-LABEL: st1lane0_ro_1d
|
||||
; CHECK: str d0, [x0, x1, lsl #3]
|
||||
%ptr = getelementptr i64, i64* %D, i64 %offset
|
||||
%tmp = extractelement <1 x i64> %A, i32 0
|
||||
store i64 %tmp, i64* %ptr
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @st1lane0_1d_double(<1 x double> %A, double* %D) {
|
||||
; CHECK-LABEL: st1lane0_1d_double
|
||||
; CHECK: str
|
||||
%tmp = extractelement <1 x double> %A, i32 0
|
||||
store double %tmp, double* %D
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @st1lane0u_1d_double(<1 x double> %A, double* %D) {
|
||||
; CHECK-LABEL: st1lane0u_1d_double
|
||||
; CHECK: stur
|
||||
%ptr = getelementptr double, double* %D, i64 -1
|
||||
%tmp = extractelement <1 x double> %A, i32 0
|
||||
store double %tmp, double* %ptr
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @st1lane0_ro_1d_double(<1 x double> %A, double* %D, i64 %offset) {
|
||||
; CHECK-LABEL: st1lane0_ro_1d_double
|
||||
; CHECK: str d0, [x0, x1, lsl #3]
|
||||
%ptr = getelementptr double, double* %D, i64 %offset
|
||||
%tmp = extractelement <1 x double> %A, i32 0
|
||||
store double %tmp, double* %ptr
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @st2lane_16b(<16 x i8> %A, <16 x i8> %B, i8* %D) {
|
||||
; CHECK-LABEL: st2lane_16b
|
||||
; CHECK: st2.b
|
||||
|
||||
@ -88,6 +88,45 @@ entry:
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_lane0_64(half* nocapture %a, <4 x half> %b) #1 {
|
||||
; CHECK-LABEL: store_lane0_64:
|
||||
; CHECK: str h0, [x0]
|
||||
entry:
|
||||
%0 = extractelement <4 x half> %b, i32 0
|
||||
store half %0, half* %a, align 2
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @storeu_lane0_64(half* nocapture %a, <4 x half> %b) #1 {
|
||||
; CHECK-LABEL: storeu_lane0_64:
|
||||
; CHECK: st1 { v0.h }[0], [x{{[0-9]+}}]
|
||||
entry:
|
||||
%0 = getelementptr half, half* %a, i64 -1
|
||||
%1 = extractelement <4 x half> %b, i32 0
|
||||
store half %1, half* %0, align 2
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @storero_lane_64(half* nocapture %a, <4 x half> %b, i64 %c) #1 {
|
||||
; CHECK-LABEL: storero_lane_64:
|
||||
; CHECK: st1 { v0.h }[2], [x{{[0-9]+}}]
|
||||
entry:
|
||||
%0 = getelementptr half, half* %a, i64 %c
|
||||
%1 = extractelement <4 x half> %b, i32 2
|
||||
store half %1, half* %0, align 2
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @storero_lane0_64(half* nocapture %a, <4 x half> %b, i64 %c) #1 {
|
||||
; CHECK-LABEL: storero_lane0_64:
|
||||
; CHECK: str h0, [x0, x1, lsl #1]
|
||||
entry:
|
||||
%0 = getelementptr half, half* %a, i64 %c
|
||||
%1 = extractelement <4 x half> %b, i32 0
|
||||
store half %1, half* %0, align 2
|
||||
ret void
|
||||
}
|
||||
|
||||
; Store from one lane of v8f16
|
||||
define void @store_lane_128(half* nocapture %a, <8 x half> %b) #1 {
|
||||
; CHECK-LABEL: store_lane_128:
|
||||
@ -98,6 +137,45 @@ entry:
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_lane0_128(half* nocapture %a, <8 x half> %b) #1 {
|
||||
; CHECK-LABEL: store_lane0_128:
|
||||
; CHECK: str h0, [x0]
|
||||
entry:
|
||||
%0 = extractelement <8 x half> %b, i32 0
|
||||
store half %0, half* %a, align 2
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @storeu_lane0_128(half* nocapture %a, <8 x half> %b) #1 {
|
||||
; CHECK-LABEL: storeu_lane0_128:
|
||||
; CHECK: st1 { v0.h }[0], [x{{[0-9]+}}]
|
||||
entry:
|
||||
%0 = getelementptr half, half* %a, i64 -1
|
||||
%1 = extractelement <8 x half> %b, i32 0
|
||||
store half %1, half* %0, align 2
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @storero_lane_128(half* nocapture %a, <8 x half> %b, i64 %c) #1 {
|
||||
; CHECK-LABEL: storero_lane_128:
|
||||
; CHECK: st1 { v0.h }[4], [x{{[0-9]+}}]
|
||||
entry:
|
||||
%0 = getelementptr half, half* %a, i64 %c
|
||||
%1 = extractelement <8 x half> %b, i32 4
|
||||
store half %1, half* %0, align 2
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @storero_lane0_128(half* nocapture %a, <8 x half> %b, i64 %c) #1 {
|
||||
; CHECK-LABEL: storero_lane0_128:
|
||||
; CHECK: str h0, [x0, x1, lsl #1]
|
||||
entry:
|
||||
%0 = getelementptr half, half* %a, i64 %c
|
||||
%1 = extractelement <8 x half> %b, i32 0
|
||||
store half %1, half* %0, align 2
|
||||
ret void
|
||||
}
|
||||
|
||||
; NEON intrinsics - (de-)interleaving loads and stores
|
||||
declare { <4 x half>, <4 x half> } @llvm.aarch64.neon.ld2.v4f16.p0v4f16(<4 x half>*)
|
||||
declare { <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld3.v4f16.p0v4f16(<4 x half>*)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user