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[DAGCombiner] Fix PR25763 - vector comparison constant folding + sign-extension
PR25763 demonstrated an issue with D14683 - vector comparison constant folding only works for i1 results, so we need to split off the sign-extension of the result to the required type. Luckily this can be done with the existing type legalization code. llvm-svn: 255289
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@ -3338,12 +3338,15 @@ SDValue SelectionDAG::FoldConstantVectorArithmetic(unsigned Opcode, SDLoc DL,
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!std::all_of(Ops.begin(), Ops.end(), IsScalarOrSameVectorSize))
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return SDValue();
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// If we are comparing vectors, then the result needs to be a i1 boolean
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// that is then sign-extended back to the legal result type.
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EVT SVT = (Opcode == ISD::SETCC ? MVT::i1 : VT.getScalarType());
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// Find legal integer scalar type for constant promotion and
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// ensure that its scalar size is at least as large as source.
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EVT SVT = VT.getScalarType();
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EVT LegalSVT = SVT;
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if (SVT.isInteger()) {
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LegalSVT = TLI->getTypeToTransformTo(*getContext(), SVT);
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EVT LegalSVT = VT.getScalarType();
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if (LegalSVT.isInteger()) {
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LegalSVT = TLI->getTypeToTransformTo(*getContext(), LegalSVT);
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if (LegalSVT.bitsLT(SVT))
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return SDValue();
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}
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@ -3380,7 +3383,7 @@ SDValue SelectionDAG::FoldConstantVectorArithmetic(unsigned Opcode, SDLoc DL,
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// Legalize the (integer) scalar constant if necessary.
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if (LegalSVT != SVT)
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ScalarResult = getNode(ISD::ANY_EXTEND, DL, LegalSVT, ScalarResult);
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ScalarResult = getNode(ISD::SIGN_EXTEND, DL, LegalSVT, ScalarResult);
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// Scalar folding only succeeded if the result is a constant or UNDEF.
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if (ScalarResult.getOpcode() != ISD::UNDEF &&
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@ -16,3 +16,19 @@ entry:
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%vget_lane = extractelement <1 x i64> %4, i32 0
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ret i64 %vget_lane
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}
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; PR25763 - folding constant vector comparisons with sign-extended result
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define <8 x i16> @dotests_458() {
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; CHECK-LABEL: dotests_458
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; CHECK: movi d0, #0x00000000ff0000
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; CHECK-NEXT: sshll v0.8h, v0.8b, #0
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; CHECK-NEXT: ret
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entry:
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%vclz_v.i = call <8 x i8> @llvm.ctlz.v8i8(<8 x i8> <i8 127, i8 38, i8 -1, i8 -128, i8 127, i8 0, i8 0, i8 0>, i1 false) #6
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%vsra_n = lshr <8 x i8> %vclz_v.i, <i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5>
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%name_6 = or <8 x i8> %vsra_n, <i8 127, i8 -128, i8 -1, i8 67, i8 84, i8 127, i8 -1, i8 0>
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%cmp.i603 = icmp slt <8 x i8> %name_6, <i8 -57, i8 -128, i8 127, i8 -128, i8 -1, i8 0, i8 -1, i8 -1>
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%vmovl.i4.i = sext <8 x i1> %cmp.i603 to <8 x i16>
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ret <8 x i16> %vmovl.i4.i
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}
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declare <8 x i8> @llvm.ctlz.v8i8(<8 x i8>, i1)
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