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Revert "[GlobalISel] Add scalar widening for G_MERGE_VALUES destination"
This reverts commit 0a37163d1d855a2db41e1f46ddbc3f4570bd7ca6. Reason: Broke the sanitizer msan bots. More details are available in the original Phabricator review: https://reviews.llvm.org/D106814.
This commit is contained in:
Mitch Phillips
parent
14491b35e0
commit
fcd0279b17
@ -165,10 +165,8 @@ public:
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Register widenWithUnmerge(LLT WideTy, Register OrigReg);
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Register widenWithUnmerge(LLT WideTy, Register OrigReg);
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private:
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private:
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LegalizeResult widenScalarSrcMergeValues(MachineInstr &MI, LLT WideTy);
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LegalizeResult
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LegalizeResult widenScalarDstMergeValues(MachineInstr &MI, LLT WideTy);
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widenScalarMergeValues(MachineInstr &MI, unsigned TypeIdx, LLT WideTy);
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LegalizeResult widenScalarMergeValues(MachineInstr &MI, unsigned TypeIdx,
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LLT WideTy);
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LegalizeResult
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LegalizeResult
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widenScalarUnmergeValues(MachineInstr &MI, unsigned TypeIdx, LLT WideTy);
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widenScalarUnmergeValues(MachineInstr &MI, unsigned TypeIdx, LLT WideTy);
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LegalizeResult
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LegalizeResult
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@ -1418,7 +1418,11 @@ void LegalizerHelper::bitcastDst(MachineInstr &MI, LLT CastTy, unsigned OpIdx) {
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}
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}
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LegalizerHelper::LegalizeResult
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LegalizerHelper::LegalizeResult
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LegalizerHelper::widenScalarSrcMergeValues(MachineInstr &MI, LLT WideTy) {
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LegalizerHelper::widenScalarMergeValues(MachineInstr &MI, unsigned TypeIdx,
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LLT WideTy) {
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if (TypeIdx != 1)
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return UnableToLegalize;
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Register DstReg = MI.getOperand(0).getReg();
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Register DstReg = MI.getOperand(0).getReg();
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LLT DstTy = MRI.getType(DstReg);
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LLT DstTy = MRI.getType(DstReg);
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if (DstTy.isVector())
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if (DstTy.isVector())
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@ -1535,44 +1539,6 @@ LegalizerHelper::widenScalarSrcMergeValues(MachineInstr &MI, LLT WideTy) {
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return Legalized;
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return Legalized;
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}
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}
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LegalizerHelper::LegalizeResult
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LegalizerHelper::widenScalarDstMergeValues(MachineInstr &MI, LLT WideTy) {
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// Disallow for vectors and pointers. Not sure about what to do with pointers.
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LLT DstTy = MRI.getType(MI.getOperand(0).getReg());
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if (!DstTy.isScalar())
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return UnableToLegalize;
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LLT SrcTy = MRI.getType(MI.getOperand(1).getReg());
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const int DstSize = DstTy.getSizeInBits();
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const int SrcSize = SrcTy.getSizeInBits();
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const int WideSize = WideTy.getSizeInBits();
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// If WideSize = DstSize + K * SrcSize then we can get WideSize by padding
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// with K undef elements.
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//
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// dst = G_MERGE_VALUES elt1, elt2, ..., eltN
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// -> wide_dst = G_MERGE_VALUES elt1, elt2, ... eltN, pad1, pad2, ... padK
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int Difference = WideSize - DstSize;
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if ((Difference) % SrcSize != 0)
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return UnableToLegalize;
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int NumPadEltsToAdd = Difference / SrcSize;
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assert(NumPadEltsToAdd && "Expected to add at least one element?");
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MachineFunction &MF = *MI.getMF();
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for (int I = 0; I < NumPadEltsToAdd; ++I) {
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auto PadElt = MIRBuilder.buildUndef(SrcTy);
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MI.addOperand(
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MF, MachineOperand::CreateReg(PadElt.getReg(0), /*isDef = */ false));
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}
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widenScalarDst(MI, WideTy, 0);
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return Legalized;
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}
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LegalizerHelper::LegalizeResult
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LegalizerHelper::widenScalarMergeValues(MachineInstr &MI, unsigned TypeIdx,
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LLT WideTy) {
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if (TypeIdx == 0)
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return widenScalarDstMergeValues(MI, WideTy);
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return widenScalarSrcMergeValues(MI, WideTy);
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}
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Register LegalizerHelper::widenWithUnmerge(LLT WideTy, Register OrigReg) {
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Register LegalizerHelper::widenWithUnmerge(LLT WideTy, Register OrigReg) {
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Register WideReg = MRI.createGenericVirtualRegister(WideTy);
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Register WideReg = MRI.createGenericVirtualRegister(WideTy);
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LLT OrigTy = MRI.getType(OrigReg);
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LLT OrigTy = MRI.getType(OrigReg);
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@ -1,5 +1,5 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=aarch64 -O0 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
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# RUN: llc -march=aarch64 -O0 -run-pass=legalizer %s -o - | FileCheck %s
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---
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---
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name: test_merge_s4
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name: test_merge_s4
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@ -26,127 +26,3 @@ body: |
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%4:_(s64) = G_ANYEXT %3
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%4:_(s64) = G_ANYEXT %3
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$x0 = COPY %4
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$x0 = COPY %4
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...
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...
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---
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name: test_merge_s24_s8
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $w0
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; 24 + 8 = 32 => Add 1 undef element as padding.
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; CHECK-LABEL: name: test_merge_s24_s8
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; CHECK: liveins: $w0
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; CHECK: %x:_(s8) = G_CONSTANT i8 0
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; CHECK: [[DEF:%[0-9]+]]:_(s8) = G_IMPLICIT_DEF
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; CHECK: [[MV:%[0-9]+]]:_(s32) = G_MERGE_VALUES %x(s8), %x(s8), %x(s8), [[DEF]](s8)
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[MV]](s32)
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; CHECK: %zext:_(s32) = G_AND [[COPY]], [[C]]
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; CHECK: $w0 = COPY %zext(s32)
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; CHECK: RET_ReallyLR implicit $w0
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%x:_(s8) = G_CONSTANT i8 0
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%merge:_(s24) = G_MERGE_VALUES %x, %x, %x
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%zext:_(s32) = G_ZEXT %merge
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$w0 = COPY %zext
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RET_ReallyLR implicit $w0
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...
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---
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name: test_merge_s40_s8
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $x0
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; 64 - 40 = 24; 24 / 8 = 3 => Add 3 undef elements as padding.
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; CHECK-LABEL: name: test_merge_s40_s8
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; CHECK: liveins: $x0
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; CHECK: %x:_(s8) = G_CONSTANT i8 0
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; CHECK: [[DEF:%[0-9]+]]:_(s8) = G_IMPLICIT_DEF
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; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES %x(s8), %x(s8), %x(s8), %x(s8), %x(s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8)
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; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1099511627775
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; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY [[MV]](s64)
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; CHECK: %zext:_(s64) = G_AND [[COPY]], [[C]]
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; CHECK: $x0 = COPY %zext(s64)
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; CHECK: RET_ReallyLR implicit $x0
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%x:_(s8) = G_CONSTANT i8 0
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%merge:_(s40) = G_MERGE_VALUES %x, %x, %x, %x, %x
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%zext:_(s64) = G_ZEXT %merge
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$x0 = COPY %zext
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RET_ReallyLR implicit $x0
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...
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---
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name: test_merge_s7_s1
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $w0
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; 7 + 1 = 8 -> Add one undef.
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; CHECK-LABEL: name: test_merge_s7_s1
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; CHECK: liveins: $w0
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; CHECK: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 0
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; CHECK: %x:_(s1) = G_TRUNC [[C]](s8)
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; CHECK: [[DEF:%[0-9]+]]:_(s1) = G_IMPLICIT_DEF
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; CHECK: [[MV:%[0-9]+]]:_(s8) = G_MERGE_VALUES %x(s1), %x(s1), %x(s1), %x(s1), %x(s1), %x(s1), %x(s1), [[DEF]](s1)
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; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
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; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[MV]](s8)
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; CHECK: %zext:_(s32) = G_AND [[ANYEXT]], [[C1]]
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; CHECK: $w0 = COPY %zext(s32)
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; CHECK: RET_ReallyLR implicit $w0
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%x:_(s1) = G_CONSTANT i1 0
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%merge:_(s7) = G_MERGE_VALUES %x, %x, %x, %x, %x, %x, %x
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%zext:_(s32) = G_ZEXT %merge
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$w0 = COPY %zext
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RET_ReallyLR implicit $w0
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...
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---
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name: test_merge_s21_s7
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $w0
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; Can't legalize this one yet.
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; CHECK-LABEL: name: test_merge_s21_s7
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; CHECK: liveins: $w0
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; CHECK: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 0
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; CHECK: %x:_(s7) = G_TRUNC [[C]](s8)
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; CHECK: %merge:_(s21) = G_MERGE_VALUES %x(s7), %x(s7), %x(s7)
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; CHECK: %zext:_(s32) = G_ZEXT %merge(s21)
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; CHECK: $w0 = COPY %zext(s32)
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; CHECK: RET_ReallyLR implicit $w0
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%x:_(s7) = G_CONSTANT i7 0
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%merge:_(s21) = G_MERGE_VALUES %x, %x, %x
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%zext:_(s32) = G_ZEXT %merge
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$w0 = COPY %zext
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RET_ReallyLR implicit $w0
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...
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---
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name: test_merge_s11_s1
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $w0
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; 7 + 1 = 8 -> Add one undef.
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; CHECK-LABEL: name: test_merge_s11_s1
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; CHECK: liveins: $w0
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; CHECK: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 0
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; CHECK: %x:_(s1) = G_TRUNC [[C]](s8)
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; CHECK: [[DEF:%[0-9]+]]:_(s1) = G_IMPLICIT_DEF
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; CHECK: [[MV:%[0-9]+]]:_(s16) = G_MERGE_VALUES %x(s1), %x(s1), %x(s1), %x(s1), %x(s1), %x(s1), %x(s1), %x(s1), %x(s1), %x(s1), %x(s1), [[DEF]](s1), [[DEF]](s1), [[DEF]](s1), [[DEF]](s1), [[DEF]](s1)
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; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2047
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; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[MV]](s16)
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; CHECK: %zext:_(s32) = G_AND [[ANYEXT]], [[C1]]
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; CHECK: $w0 = COPY %zext(s32)
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; CHECK: RET_ReallyLR implicit $w0
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%x:_(s1) = G_CONSTANT i1 0
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%merge:_(s11) = G_MERGE_VALUES %x, %x, %x, %x, %x, %x, %x, %x, %x, %x, %x
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%zext:_(s32) = G_ZEXT %merge
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$w0 = COPY %zext
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RET_ReallyLR implicit $w0
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