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[AArch64] Add a comment to make it explicit why we increased the complexity.
Follow-up of r233653. llvm-svn: 233936
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@ -1637,6 +1637,10 @@ multiclass AddSub<bit isSub, string mnemonic,
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SDPatternOperator OpNode = null_frag> {
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let hasSideEffects = 0, isReMaterializable = 1, isAsCheapAsAMove = 1 in {
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// Add/Subtract immediate
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// Increase the weight of the immediate variant to try to match it before
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// the extended register variant.
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// We used to match the register variant before the immediate when the
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// register argument could be implicitly zero-extended.
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let AddedComplexity = 6 in
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def Wri : BaseAddSubImm<isSub, 0, GPR32sp, GPR32sp, addsub_shifted_imm32,
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mnemonic, OpNode> {
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