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[X86] Remove some more code from combineShuffle that is no longer needed with widening legalization.
llvm-svn: 368523
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@ -33546,53 +33546,6 @@ static SDValue combineShuffle(SDNode *N, SelectionDAG &DAG,
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}
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}
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// Look for a truncating shuffle to v2i32 of a PMULUDQ where one of the
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// operands is an extend from v2i32 to v2i64. Turn it into a pmulld.
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// FIXME: This can probably go away once we default to widening legalization.
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if (Subtarget.hasSSE41() && VT == MVT::v4i32 &&
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N->getOpcode() == ISD::VECTOR_SHUFFLE &&
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N->getOperand(0).getOpcode() == ISD::BITCAST &&
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N->getOperand(0).getOperand(0).getOpcode() == X86ISD::PMULUDQ) {
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SDValue BC = N->getOperand(0);
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SDValue MULUDQ = BC.getOperand(0);
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ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
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ArrayRef<int> Mask = SVOp->getMask();
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if (BC.hasOneUse() && MULUDQ.hasOneUse() &&
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Mask[0] == 0 && Mask[1] == 2 && Mask[2] == -1 && Mask[3] == -1) {
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SDValue Op0 = MULUDQ.getOperand(0);
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SDValue Op1 = MULUDQ.getOperand(1);
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if (Op0.getOpcode() == ISD::BITCAST &&
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Op0.getOperand(0).getOpcode() == ISD::VECTOR_SHUFFLE &&
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Op0.getOperand(0).getValueType() == MVT::v4i32) {
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ShuffleVectorSDNode *SVOp0 =
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cast<ShuffleVectorSDNode>(Op0.getOperand(0));
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ArrayRef<int> Mask2 = SVOp0->getMask();
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if (Mask2[0] == 0 && Mask2[1] == -1 &&
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Mask2[2] == 1 && Mask2[3] == -1) {
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Op0 = SVOp0->getOperand(0);
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Op1 = DAG.getBitcast(MVT::v4i32, Op1);
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Op1 = DAG.getVectorShuffle(MVT::v4i32, dl, Op1, Op1, Mask);
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return DAG.getNode(ISD::MUL, dl, MVT::v4i32, Op0, Op1);
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}
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}
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if (Op1.getOpcode() == ISD::BITCAST &&
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Op1.getOperand(0).getOpcode() == ISD::VECTOR_SHUFFLE &&
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Op1.getOperand(0).getValueType() == MVT::v4i32) {
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ShuffleVectorSDNode *SVOp1 =
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cast<ShuffleVectorSDNode>(Op1.getOperand(0));
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ArrayRef<int> Mask2 = SVOp1->getMask();
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if (Mask2[0] == 0 && Mask2[1] == -1 &&
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Mask2[2] == 1 && Mask2[3] == -1) {
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Op0 = DAG.getBitcast(MVT::v4i32, Op0);
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Op0 = DAG.getVectorShuffle(MVT::v4i32, dl, Op0, Op0, Mask);
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Op1 = SVOp1->getOperand(0);
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return DAG.getNode(ISD::MUL, dl, MVT::v4i32, Op0, Op1);
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}
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}
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}
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}
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return SDValue();
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}
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