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AMDGPU/GlobalISel: Start matching s_lshlN_add_u32 instructions
Use a hack to only enable this for GlobalISel. Technically this also works with SelectionDAG, but the divergence selection isn't reliable enough and a few cases fail, but I have no desire to spend time writing the manual expansion code for it. The DAG actually does a better job since it catches using v_add_lshl_u32 in the mixed SGPR/VGPR cases.
This commit is contained in:
Matt Arsenault
parent
87153cc1e9
commit
fd1c619371
@ -630,6 +630,16 @@ def add_ctpop : PatFrag <
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(add (ctpop $src0), $src1)
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>;
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foreach I = 1-4 in {
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def shl#I#_add : PatFrag <
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(ops node:$src0, node:$src1),
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(add (shl_oneuse $src0, (i32 I)), $src1)> {
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// FIXME: Poor substitute for disabling pattern in SelectionDAG
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let PredicateCode = [{return false;}];
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let GISelPredicateCode = [{return true;}];
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}
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}
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multiclass SIAtomicM0Glue2 <string op_name, bit is_amdgpu = 0,
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SDTypeProfile tc = SDTAtomic2,
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bit IsInt = 1> {
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@ -613,10 +613,18 @@ let SubtargetPredicate = isGFX9Plus in {
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def S_PACK_HH_B32_B16 : SOP2_32<"s_pack_hh_b32_b16">;
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let Defs = [SCC] in {
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def S_LSHL1_ADD_U32 : SOP2_32<"s_lshl1_add_u32">;
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def S_LSHL2_ADD_U32 : SOP2_32<"s_lshl2_add_u32">;
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def S_LSHL3_ADD_U32 : SOP2_32<"s_lshl3_add_u32">;
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def S_LSHL4_ADD_U32 : SOP2_32<"s_lshl4_add_u32">;
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def S_LSHL1_ADD_U32 : SOP2_32<"s_lshl1_add_u32",
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[(set i32:$sdst, (shl1_add SSrc_b32:$src0, SSrc_b32:$src1))]
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>;
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def S_LSHL2_ADD_U32 : SOP2_32<"s_lshl2_add_u32",
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[(set i32:$sdst, (shl2_add SSrc_b32:$src0, SSrc_b32:$src1))]
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>;
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def S_LSHL3_ADD_U32 : SOP2_32<"s_lshl3_add_u32",
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[(set i32:$sdst, (shl3_add SSrc_b32:$src0, SSrc_b32:$src1))]
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>;
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def S_LSHL4_ADD_U32 : SOP2_32<"s_lshl4_add_u32",
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[(set i32:$sdst, (shl4_add SSrc_b32:$src0, SSrc_b32:$src1))]
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>;
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} // End Defs = [SCC]
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let isCommutable = 1 in {
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410
test/CodeGen/AMDGPU/GlobalISel/shlN_add.ll
Normal file
410
test/CodeGen/AMDGPU/GlobalISel/shlN_add.ll
Normal file
@ -0,0 +1,410 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -global-isel -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9 %s
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; RUN: llc -global-isel -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX8 %s
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; Test gfx9+ s_shl[1-4]_add_u32 pattern matching
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define amdgpu_ps i32 @s_shl1_add_u32(i32 inreg %src0, i32 inreg %src1) {
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; GFX9-LABEL: s_shl1_add_u32:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_lshl1_add_u32 s0, s0, s1
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; GFX9-NEXT: ; return to shader part epilog
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;
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; GFX8-LABEL: s_shl1_add_u32:
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; GFX8: ; %bb.0:
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; GFX8-NEXT: s_lshl_b32 s0, s0, 1
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; GFX8-NEXT: s_add_i32 s0, s0, s1
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; GFX8-NEXT: ; return to shader part epilog
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%shl = shl i32 %src0, 1
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%add = add i32 %shl, %src1
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ret i32 %add
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}
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define amdgpu_ps i32 @s_shl2_add_u32(i32 inreg %src0, i32 inreg %src1) {
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; GFX9-LABEL: s_shl2_add_u32:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_lshl2_add_u32 s0, s0, s1
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; GFX9-NEXT: ; return to shader part epilog
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;
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; GFX8-LABEL: s_shl2_add_u32:
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; GFX8: ; %bb.0:
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; GFX8-NEXT: s_lshl_b32 s0, s0, 2
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; GFX8-NEXT: s_add_i32 s0, s0, s1
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; GFX8-NEXT: ; return to shader part epilog
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%shl = shl i32 %src0, 2
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%add = add i32 %shl, %src1
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ret i32 %add
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}
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define amdgpu_ps i32 @s_shl3_add_u32(i32 inreg %src0, i32 inreg %src1) {
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; GFX9-LABEL: s_shl3_add_u32:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_lshl3_add_u32 s0, s0, s1
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; GFX9-NEXT: ; return to shader part epilog
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;
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; GFX8-LABEL: s_shl3_add_u32:
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; GFX8: ; %bb.0:
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; GFX8-NEXT: s_lshl_b32 s0, s0, 3
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; GFX8-NEXT: s_add_i32 s0, s0, s1
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; GFX8-NEXT: ; return to shader part epilog
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%shl = shl i32 %src0, 3
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%add = add i32 %shl, %src1
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ret i32 %add
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}
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define amdgpu_ps i32 @s_shl4_add_u32(i32 inreg %src0, i32 inreg %src1) {
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; GFX9-LABEL: s_shl4_add_u32:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_lshl4_add_u32 s0, s0, s1
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; GFX9-NEXT: ; return to shader part epilog
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;
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; GFX8-LABEL: s_shl4_add_u32:
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; GFX8: ; %bb.0:
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; GFX8-NEXT: s_lshl_b32 s0, s0, 4
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; GFX8-NEXT: s_add_i32 s0, s0, s1
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; GFX8-NEXT: ; return to shader part epilog
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%shl = shl i32 %src0, 4
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%add = add i32 %shl, %src1
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ret i32 %add
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}
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define amdgpu_ps i32 @s_shl5_add_u32(i32 inreg %src0, i32 inreg %src1) {
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; GCN-LABEL: s_shl5_add_u32:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_lshl_b32 s0, s0, 5
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; GCN-NEXT: s_add_i32 s0, s0, s1
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; GCN-NEXT: ; return to shader part epilog
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%shl = shl i32 %src0, 5
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%add = add i32 %shl, %src1
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ret i32 %add
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}
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define i32 @v_shl1_add_u32(i32 %src0, i32 %src1) {
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; GFX9-LABEL: v_shl1_add_u32:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9-NEXT: v_lshl_add_u32 v0, v0, 1, v1
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; GFX9-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX8-LABEL: v_shl1_add_u32:
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; GFX8: ; %bb.0:
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; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX8-NEXT: v_lshlrev_b32_e32 v0, 1, v0
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; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v1
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; GFX8-NEXT: s_setpc_b64 s[30:31]
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%shl = shl i32 %src0, 1
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%add = add i32 %shl, %src1
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ret i32 %add
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}
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define i32 @v_shl2_add_u32(i32 %src0, i32 %src1) {
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; GFX9-LABEL: v_shl2_add_u32:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9-NEXT: v_lshl_add_u32 v0, v0, 2, v1
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; GFX9-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX8-LABEL: v_shl2_add_u32:
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; GFX8: ; %bb.0:
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; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX8-NEXT: v_lshlrev_b32_e32 v0, 2, v0
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; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v1
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; GFX8-NEXT: s_setpc_b64 s[30:31]
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%shl = shl i32 %src0, 2
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%add = add i32 %shl, %src1
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ret i32 %add
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}
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define i32 @v_shl3_add_u32(i32 %src0, i32 %src1) {
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; GFX9-LABEL: v_shl3_add_u32:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9-NEXT: v_lshl_add_u32 v0, v0, 3, v1
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; GFX9-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX8-LABEL: v_shl3_add_u32:
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; GFX8: ; %bb.0:
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; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX8-NEXT: v_lshlrev_b32_e32 v0, 3, v0
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; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v1
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; GFX8-NEXT: s_setpc_b64 s[30:31]
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%shl = shl i32 %src0, 3
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%add = add i32 %shl, %src1
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ret i32 %add
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}
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define i32 @v_shl4_add_u32(i32 %src0, i32 %src1) {
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; GFX9-LABEL: v_shl4_add_u32:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9-NEXT: v_lshl_add_u32 v0, v0, 4, v1
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; GFX9-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX8-LABEL: v_shl4_add_u32:
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; GFX8: ; %bb.0:
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; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX8-NEXT: v_lshlrev_b32_e32 v0, 4, v0
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; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v1
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; GFX8-NEXT: s_setpc_b64 s[30:31]
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%shl = shl i32 %src0, 4
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%add = add i32 %shl, %src1
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ret i32 %add
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}
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define i32 @v_shl5_add_u32(i32 %src0, i32 %src1) {
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; GFX9-LABEL: v_shl5_add_u32:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9-NEXT: v_lshl_add_u32 v0, v0, 5, v1
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; GFX9-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX8-LABEL: v_shl5_add_u32:
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; GFX8: ; %bb.0:
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; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX8-NEXT: v_lshlrev_b32_e32 v0, 5, v0
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; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v1
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; GFX8-NEXT: s_setpc_b64 s[30:31]
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%shl = shl i32 %src0, 5
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%add = add i32 %shl, %src1
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ret i32 %add
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}
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; FIXME: Use v_lshl_add_u32
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; shift is scalar, but add is vector.
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define amdgpu_ps float @shl1_add_u32_vgpr1(i32 inreg %src0, i32 %src1) {
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; GFX9-LABEL: shl1_add_u32_vgpr1:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_lshl_b32 s0, s0, 1
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; GFX9-NEXT: v_add_u32_e32 v0, s0, v0
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; GFX9-NEXT: ; return to shader part epilog
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;
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; GFX8-LABEL: shl1_add_u32_vgpr1:
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; GFX8: ; %bb.0:
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; GFX8-NEXT: s_lshl_b32 s0, s0, 1
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; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v0
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; GFX8-NEXT: ; return to shader part epilog
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%shl = shl i32 %src0, 1
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%add = add i32 %shl, %src1
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%cast = bitcast i32 %add to float
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ret float %cast
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}
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define amdgpu_ps float @shl2_add_u32_vgpr1(i32 inreg %src0, i32 %src1) {
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; GFX9-LABEL: shl2_add_u32_vgpr1:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_lshl_b32 s0, s0, 2
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; GFX9-NEXT: v_add_u32_e32 v0, s0, v0
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; GFX9-NEXT: ; return to shader part epilog
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;
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; GFX8-LABEL: shl2_add_u32_vgpr1:
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; GFX8: ; %bb.0:
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; GFX8-NEXT: s_lshl_b32 s0, s0, 2
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; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v0
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; GFX8-NEXT: ; return to shader part epilog
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%shl = shl i32 %src0, 2
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%add = add i32 %shl, %src1
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%cast = bitcast i32 %add to float
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ret float %cast
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}
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define amdgpu_ps float @shl3_add_u32_vgpr1(i32 inreg %src0, i32 %src1) {
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; GFX9-LABEL: shl3_add_u32_vgpr1:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_lshl_b32 s0, s0, 3
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; GFX9-NEXT: v_add_u32_e32 v0, s0, v0
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; GFX9-NEXT: ; return to shader part epilog
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;
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; GFX8-LABEL: shl3_add_u32_vgpr1:
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; GFX8: ; %bb.0:
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; GFX8-NEXT: s_lshl_b32 s0, s0, 3
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; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v0
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; GFX8-NEXT: ; return to shader part epilog
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%shl = shl i32 %src0, 3
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%add = add i32 %shl, %src1
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%cast = bitcast i32 %add to float
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ret float %cast
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}
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define amdgpu_ps float @shl4_add_u32_vgpr1(i32 inreg %src0, i32 %src1) {
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; GFX9-LABEL: shl4_add_u32_vgpr1:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_lshl_b32 s0, s0, 4
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; GFX9-NEXT: v_add_u32_e32 v0, s0, v0
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; GFX9-NEXT: ; return to shader part epilog
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;
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; GFX8-LABEL: shl4_add_u32_vgpr1:
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; GFX8: ; %bb.0:
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; GFX8-NEXT: s_lshl_b32 s0, s0, 4
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; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v0
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; GFX8-NEXT: ; return to shader part epilog
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%shl = shl i32 %src0, 4
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%add = add i32 %shl, %src1
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%cast = bitcast i32 %add to float
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ret float %cast
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}
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define amdgpu_ps float @shl5_add_u32_vgpr1(i32 inreg %src0, i32 %src1) {
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; GFX9-LABEL: shl5_add_u32_vgpr1:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_lshl_b32 s0, s0, 5
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; GFX9-NEXT: v_add_u32_e32 v0, s0, v0
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; GFX9-NEXT: ; return to shader part epilog
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;
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; GFX8-LABEL: shl5_add_u32_vgpr1:
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; GFX8: ; %bb.0:
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; GFX8-NEXT: s_lshl_b32 s0, s0, 5
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; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v0
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; GFX8-NEXT: ; return to shader part epilog
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%shl = shl i32 %src0, 5
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%add = add i32 %shl, %src1
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%cast = bitcast i32 %add to float
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ret float %cast
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}
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define amdgpu_ps <2 x i32> @s_shl1_add_u32_v2(<2 x i32> inreg %src0, <2 x i32> inreg %src1) {
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; GFX9-LABEL: s_shl1_add_u32_v2:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_lshl1_add_u32 s0, s0, s2
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; GFX9-NEXT: s_lshl1_add_u32 s1, s1, s3
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; GFX9-NEXT: ; return to shader part epilog
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;
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; GFX8-LABEL: s_shl1_add_u32_v2:
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; GFX8: ; %bb.0:
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; GFX8-NEXT: s_lshl_b32 s0, s0, 1
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; GFX8-NEXT: s_lshl_b32 s1, s1, 1
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; GFX8-NEXT: s_add_i32 s0, s0, s2
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; GFX8-NEXT: s_add_i32 s1, s1, s3
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; GFX8-NEXT: ; return to shader part epilog
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%shl = shl <2 x i32> %src0, <i32 1, i32 1>
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%add = add <2 x i32> %shl, %src1
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ret <2 x i32> %add
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}
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|
||||
define amdgpu_ps <2 x i32> @s_shl2_add_u32_v2(<2 x i32> inreg %src0, <2 x i32> inreg %src1) {
|
||||
; GFX9-LABEL: s_shl2_add_u32_v2:
|
||||
; GFX9: ; %bb.0:
|
||||
; GFX9-NEXT: s_lshl2_add_u32 s0, s0, s2
|
||||
; GFX9-NEXT: s_lshl2_add_u32 s1, s1, s3
|
||||
; GFX9-NEXT: ; return to shader part epilog
|
||||
;
|
||||
; GFX8-LABEL: s_shl2_add_u32_v2:
|
||||
; GFX8: ; %bb.0:
|
||||
; GFX8-NEXT: s_lshl_b32 s0, s0, 2
|
||||
; GFX8-NEXT: s_lshl_b32 s1, s1, 2
|
||||
; GFX8-NEXT: s_add_i32 s0, s0, s2
|
||||
; GFX8-NEXT: s_add_i32 s1, s1, s3
|
||||
; GFX8-NEXT: ; return to shader part epilog
|
||||
%shl = shl <2 x i32> %src0, <i32 2, i32 2>
|
||||
%add = add <2 x i32> %shl, %src1
|
||||
ret <2 x i32> %add
|
||||
}
|
||||
|
||||
define amdgpu_ps <2 x i32> @s_shl3_add_u32_v2(<2 x i32> inreg %src0, <2 x i32> inreg %src1) {
|
||||
; GFX9-LABEL: s_shl3_add_u32_v2:
|
||||
; GFX9: ; %bb.0:
|
||||
; GFX9-NEXT: s_lshl3_add_u32 s0, s0, s2
|
||||
; GFX9-NEXT: s_lshl3_add_u32 s1, s1, s3
|
||||
; GFX9-NEXT: ; return to shader part epilog
|
||||
;
|
||||
; GFX8-LABEL: s_shl3_add_u32_v2:
|
||||
; GFX8: ; %bb.0:
|
||||
; GFX8-NEXT: s_lshl_b32 s0, s0, 3
|
||||
; GFX8-NEXT: s_lshl_b32 s1, s1, 3
|
||||
; GFX8-NEXT: s_add_i32 s0, s0, s2
|
||||
; GFX8-NEXT: s_add_i32 s1, s1, s3
|
||||
; GFX8-NEXT: ; return to shader part epilog
|
||||
%shl = shl <2 x i32> %src0, <i32 3, i32 3>
|
||||
%add = add <2 x i32> %shl, %src1
|
||||
ret <2 x i32> %add
|
||||
}
|
||||
|
||||
define amdgpu_ps <2 x i32> @s_shl4_add_u32_v2(<2 x i32> inreg %src0, <2 x i32> inreg %src1) {
|
||||
; GFX9-LABEL: s_shl4_add_u32_v2:
|
||||
; GFX9: ; %bb.0:
|
||||
; GFX9-NEXT: s_lshl4_add_u32 s0, s0, s2
|
||||
; GFX9-NEXT: s_lshl4_add_u32 s1, s1, s3
|
||||
; GFX9-NEXT: ; return to shader part epilog
|
||||
;
|
||||
; GFX8-LABEL: s_shl4_add_u32_v2:
|
||||
; GFX8: ; %bb.0:
|
||||
; GFX8-NEXT: s_lshl_b32 s0, s0, 4
|
||||
; GFX8-NEXT: s_lshl_b32 s1, s1, 4
|
||||
; GFX8-NEXT: s_add_i32 s0, s0, s2
|
||||
; GFX8-NEXT: s_add_i32 s1, s1, s3
|
||||
; GFX8-NEXT: ; return to shader part epilog
|
||||
%shl = shl <2 x i32> %src0, <i32 4, i32 4>
|
||||
%add = add <2 x i32> %shl, %src1
|
||||
ret <2 x i32> %add
|
||||
}
|
||||
|
||||
define amdgpu_ps <2 x i32> @s_shl_2_4_add_u32_v2(<2 x i32> inreg %src0, <2 x i32> inreg %src1) {
|
||||
; GFX9-LABEL: s_shl_2_4_add_u32_v2:
|
||||
; GFX9: ; %bb.0:
|
||||
; GFX9-NEXT: s_lshl2_add_u32 s0, s0, s2
|
||||
; GFX9-NEXT: s_lshl4_add_u32 s1, s1, s3
|
||||
; GFX9-NEXT: ; return to shader part epilog
|
||||
;
|
||||
; GFX8-LABEL: s_shl_2_4_add_u32_v2:
|
||||
; GFX8: ; %bb.0:
|
||||
; GFX8-NEXT: s_lshl_b32 s0, s0, 2
|
||||
; GFX8-NEXT: s_lshl_b32 s1, s1, 4
|
||||
; GFX8-NEXT: s_add_i32 s0, s0, s2
|
||||
; GFX8-NEXT: s_add_i32 s1, s1, s3
|
||||
; GFX8-NEXT: ; return to shader part epilog
|
||||
%shl = shl <2 x i32> %src0, <i32 2, i32 4>
|
||||
%add = add <2 x i32> %shl, %src1
|
||||
ret <2 x i32> %add
|
||||
}
|
||||
|
||||
define amdgpu_ps { i32, i32 } @s_shl4_add_u32_multi_use(i32 inreg %src0, i32 inreg %src1) {
|
||||
; GCN-LABEL: s_shl4_add_u32_multi_use:
|
||||
; GCN: ; %bb.0:
|
||||
; GCN-NEXT: s_lshl_b32 s0, s0, 4
|
||||
; GCN-NEXT: s_add_i32 s1, s0, s1
|
||||
; GCN-NEXT: ; return to shader part epilog
|
||||
%shl = shl i32 %src0, 4
|
||||
%add = add i32 %shl, %src1
|
||||
%insert0 = insertvalue { i32, i32 } undef, i32 %shl, 0
|
||||
%insert1 = insertvalue { i32, i32 } %insert0, i32 %add, 1
|
||||
ret { i32, i32 } %insert1
|
||||
}
|
||||
|
||||
define amdgpu_ps { i32, i32 } @s_shl3_add_u32_multi_use(i32 inreg %src0, i32 inreg %src1) {
|
||||
; GCN-LABEL: s_shl3_add_u32_multi_use:
|
||||
; GCN: ; %bb.0:
|
||||
; GCN-NEXT: s_lshl_b32 s0, s0, 3
|
||||
; GCN-NEXT: s_add_i32 s1, s0, s1
|
||||
; GCN-NEXT: ; return to shader part epilog
|
||||
%shl = shl i32 %src0, 3
|
||||
%add = add i32 %shl, %src1
|
||||
%insert0 = insertvalue { i32, i32 } undef, i32 %shl, 0
|
||||
%insert1 = insertvalue { i32, i32 } %insert0, i32 %add, 1
|
||||
ret { i32, i32 } %insert1
|
||||
}
|
||||
|
||||
define amdgpu_ps { i32, i32 } @s_shl2_add_u32_multi_use(i32 inreg %src0, i32 inreg %src1) {
|
||||
; GCN-LABEL: s_shl2_add_u32_multi_use:
|
||||
; GCN: ; %bb.0:
|
||||
; GCN-NEXT: s_lshl_b32 s0, s0, 2
|
||||
; GCN-NEXT: s_add_i32 s1, s0, s1
|
||||
; GCN-NEXT: ; return to shader part epilog
|
||||
%shl = shl i32 %src0, 2
|
||||
%add = add i32 %shl, %src1
|
||||
%insert0 = insertvalue { i32, i32 } undef, i32 %shl, 0
|
||||
%insert1 = insertvalue { i32, i32 } %insert0, i32 %add, 1
|
||||
ret { i32, i32 } %insert1
|
||||
}
|
||||
|
||||
|
||||
define amdgpu_ps { i32, i32 } @s_shl1_add_u32_multi_use(i32 inreg %src0, i32 inreg %src1) {
|
||||
; GCN-LABEL: s_shl1_add_u32_multi_use:
|
||||
; GCN: ; %bb.0:
|
||||
; GCN-NEXT: s_lshl_b32 s0, s0, 1
|
||||
; GCN-NEXT: s_add_i32 s1, s0, s1
|
||||
; GCN-NEXT: ; return to shader part epilog
|
||||
%shl = shl i32 %src0, 1
|
||||
%add = add i32 %shl, %src1
|
||||
%insert0 = insertvalue { i32, i32 } undef, i32 %shl, 0
|
||||
%insert1 = insertvalue { i32, i32 } %insert0, i32 %add, 1
|
||||
ret { i32, i32 } %insert1
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user