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Change names for MIPS "generic" processors defined in Mips.td to match what GNU

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tools use. Patch by Simon Atanasyan.

"mips32r1" => "mips32"
"4ke" => mips32r2"
"mips64r1" => "mips64"

llvm-svn: 145451
This commit is contained in:
Akira Hatanaka 2011-11-29 23:08:41 +00:00
parent 538759efa7
commit fd548b69f5
8 changed files with 12 additions and 12 deletions
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6
lib/Target/Mips/Mips.td
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@ -79,9 +79,9 @@ def FeatureMips64r2 : SubtargetFeature<"mips64r2", "MipsArchVersion",
class Proc<string Name, list<SubtargetFeature> Features>
: Processor<Name, MipsGenericItineraries, Features>;
def : Proc<"mips32r1", [FeatureMips32]>;
def : Proc<"4ke", [FeatureMips32r2]>;
def : Proc<"mips64r1", [FeatureMips64]>;
def : Proc<"mips32", [FeatureMips32]>;
def : Proc<"mips32r2", [FeatureMips32r2]>;
def : Proc<"mips64", [FeatureMips64]>;
def : Proc<"mips64r2", [FeatureMips64r2]>;
def MipsAsmWriter : AsmWriter {

2
lib/Target/Mips/MipsSubtarget.cpp
View File

@ -31,7 +31,7 @@ MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU,
{
std::string CPUName = CPU;
if (CPUName.empty())
CPUName = "mips32r1";
CPUName = "mips32";
// Parse features string.
ParseSubtargetFeatures(CPUName, FS);

2
test/CodeGen/Mips/extins.ll
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@ -1,4 +1,4 @@
; RUN: llc -march=mips -mcpu=4ke < %s | FileCheck %s
; RUN: llc -march=mips -mcpu=mips32r2 < %s | FileCheck %s
define i32 @ext0_5_9(i32 %s, i32 %pos, i32 %sz) nounwind readnone {
entry:

2
test/CodeGen/Mips/largeimmprinting.ll
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@ -1,4 +1,4 @@
; RUN: llc -march=mipsel -mcpu=4ke < %s | FileCheck %s
; RUN: llc -march=mipsel -mcpu=mips32r2 < %s | FileCheck %s
%struct.S1 = type { [65536 x i8] }

4
test/CodeGen/Mips/mips64fpldst.ll
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@ -1,5 +1,5 @@
; RUN: llc < %s -march=mips64el -mcpu=mips64r1 -mattr=n64 | FileCheck %s -check-prefix=CHECK-N64
; RUN: llc < %s -march=mips64el -mcpu=mips64r1 -mattr=n32 | FileCheck %s -check-prefix=CHECK-N32
; RUN: llc < %s -march=mips64el -mcpu=mips64 -mattr=n64 | FileCheck %s -check-prefix=CHECK-N64
; RUN: llc < %s -march=mips64el -mcpu=mips64 -mattr=n32 | FileCheck %s -check-prefix=CHECK-N32
@f0 = common global float 0.000000e+00, align 4
@d0 = common global double 0.000000e+00, align 8

2
test/CodeGen/Mips/mips64instrs.ll
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@ -1,4 +1,4 @@
; RUN: llc -march=mips64el -mcpu=mips64r1 < %s | FileCheck %s
; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s
define i64 @f0(i64 %a0, i64 %a1) nounwind readnone {
entry:

4
test/CodeGen/Mips/mips64intldst.ll
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@ -1,5 +1,5 @@
; RUN: llc < %s -march=mips64el -mcpu=mips64r1 -mattr=n64 | FileCheck %s -check-prefix=CHECK-N64
; RUN: llc < %s -march=mips64el -mcpu=mips64r1 -mattr=n32 | FileCheck %s -check-prefix=CHECK-N32
; RUN: llc < %s -march=mips64el -mcpu=mips64 -mattr=n64 | FileCheck %s -check-prefix=CHECK-N64
; RUN: llc < %s -march=mips64el -mcpu=mips64 -mattr=n32 | FileCheck %s -check-prefix=CHECK-N32
@c = common global i8 0, align 4
@s = common global i16 0, align 4

2
test/CodeGen/Mips/rotate.ll
View File

@ -1,4 +1,4 @@
; RUN: llc -march=mips -mcpu=4ke < %s | FileCheck %s
; RUN: llc -march=mips -mcpu=mips32r2 < %s | FileCheck %s
; CHECK: rotrv $2, $4
define i32 @rot0(i32 %a, i32 %b) nounwind readnone {