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[ARM] KnownBits for CSINC/CSNEG/CSINV
This adds some simple known bits handling for the three CSINC/NEG/INV instructions. From the operands known bits we can compute the common bits of the first operand and incremented/negated/inverted second operand. The first, especially CSINC ZR, ZR, comes up fair amount in the tests. The others are more rare so a unit test for them is added. Differential Revision: https://reviews.llvm.org/D97788
This commit is contained in:
David Green
parent
8d6ae1909f
commit
fd710d5689
@ -17800,6 +17800,28 @@ void ARMTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
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Known = KnownOp.zext(32);
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break;
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}
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case ARMISD::CSINC:
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case ARMISD::CSINV:
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case ARMISD::CSNEG: {
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KnownBits KnownOp0 = DAG.computeKnownBits(Op->getOperand(0), Depth + 1);
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KnownBits KnownOp1 = DAG.computeKnownBits(Op->getOperand(1), Depth + 1);
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// The result is either:
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// CSINC: KnownOp0 or KnownOp1 + 1
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// CSINV: KnownOp0 or ~KnownOp1
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// CSNEG: KnownOp0 or KnownOp1 * -1
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if (Op.getOpcode() == ARMISD::CSINC)
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KnownOp1 = KnownBits::computeForAddSub(
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true, false, KnownOp1, KnownBits::makeConstant(APInt(32, 1)));
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else if (Op.getOpcode() == ARMISD::CSINV)
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std::swap(KnownOp1.Zero, KnownOp1.One);
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else if (Op.getOpcode() == ARMISD::CSNEG)
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KnownOp1 = KnownBits::computeForMul(
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KnownOp1, KnownBits::makeConstant(APInt(32, -1)));
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Known = KnownBits::commonBits(KnownOp0, KnownOp1);
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break;
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}
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}
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}
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@ -19,11 +19,9 @@ define arm_aapcs_vfpcc void @fast_float_mul(float* nocapture %a, float* nocaptur
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; CHECK-NEXT: cset r4, hi
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; CHECK-NEXT: cmp r5, r0
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; CHECK-NEXT: cset r5, hi
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; CHECK-NEXT: ands r4, r5
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; CHECK-NEXT: lsls r4, r4, #31
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; CHECK-NEXT: itt eq
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; CHECK-NEXT: andeq.w r5, lr, r12
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; CHECK-NEXT: lslseq.w r5, r5, #31
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; CHECK-NEXT: tst r5, r4
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; CHECK-NEXT: it eq
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; CHECK-NEXT: andseq.w r5, lr, r12
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; CHECK-NEXT: beq .LBB0_4
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; CHECK-NEXT: @ %bb.2: @ %for.body.preheader
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; CHECK-NEXT: subs r5, r3, #1
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@ -26,11 +26,9 @@ define arm_aapcs_vfpcc void @float_float_mul(float* nocapture readonly %a, float
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; CHECK-NEXT: cmp r4, r2
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; CHECK-NEXT: cset r4, hi
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; CHECK-NEXT: mov.w r12, #0
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; CHECK-NEXT: ands r5, r4
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; CHECK-NEXT: lsls r5, r5, #31
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; CHECK-NEXT: itt eq
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; CHECK-NEXT: andeq r7, r6
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; CHECK-NEXT: lslseq.w r7, r7, #31
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; CHECK-NEXT: tst r4, r5
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; CHECK-NEXT: it eq
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; CHECK-NEXT: andseq.w r7, r7, r6
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; CHECK-NEXT: beq .LBB0_11
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; CHECK-NEXT: .LBB0_4: @ %for.body.preheader22
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; CHECK-NEXT: mvn.w r7, r12
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@ -241,11 +239,9 @@ define arm_aapcs_vfpcc void @float_float_add(float* nocapture readonly %a, float
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; CHECK-NEXT: cmp r4, r2
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; CHECK-NEXT: cset r4, hi
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; CHECK-NEXT: mov.w r12, #0
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; CHECK-NEXT: ands r5, r4
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; CHECK-NEXT: lsls r5, r5, #31
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; CHECK-NEXT: itt eq
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; CHECK-NEXT: andeq r7, r6
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; CHECK-NEXT: lslseq.w r7, r7, #31
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; CHECK-NEXT: tst r4, r5
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; CHECK-NEXT: it eq
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; CHECK-NEXT: andseq.w r7, r7, r6
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; CHECK-NEXT: beq .LBB1_11
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; CHECK-NEXT: .LBB1_4: @ %for.body.preheader22
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; CHECK-NEXT: mvn.w r7, r12
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@ -456,11 +452,9 @@ define arm_aapcs_vfpcc void @float_float_sub(float* nocapture readonly %a, float
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; CHECK-NEXT: cmp r4, r2
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; CHECK-NEXT: cset r4, hi
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; CHECK-NEXT: mov.w r12, #0
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; CHECK-NEXT: ands r5, r4
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; CHECK-NEXT: lsls r5, r5, #31
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; CHECK-NEXT: itt eq
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; CHECK-NEXT: andeq r7, r6
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; CHECK-NEXT: lslseq.w r7, r7, #31
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; CHECK-NEXT: tst r4, r5
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; CHECK-NEXT: it eq
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; CHECK-NEXT: andseq.w r7, r7, r6
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; CHECK-NEXT: beq .LBB2_11
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; CHECK-NEXT: .LBB2_4: @ %for.body.preheader22
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; CHECK-NEXT: mvn.w r7, r12
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@ -393,11 +393,9 @@ define arm_aapcs_vfpcc void @test_vec_mul_scalar_add_char(i8* nocapture readonly
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; CHECK-NEXT: cset r5, hi
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; CHECK-NEXT: cmp r4, r3
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; CHECK-NEXT: cset r4, hi
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; CHECK-NEXT: ands r5, r4
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; CHECK-NEXT: lsls r5, r5, #31
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; CHECK-NEXT: itt eq
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; CHECK-NEXT: andeq r7, r6
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; CHECK-NEXT: lslseq.w r7, r7, #31
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; CHECK-NEXT: tst r4, r5
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; CHECK-NEXT: it eq
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; CHECK-NEXT: andseq.w r7, r7, r6
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; CHECK-NEXT: beq .LBB5_4
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; CHECK-NEXT: @ %bb.2: @ %for.body.preheader
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; CHECK-NEXT: sub.w r4, r12, #1
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@ -691,11 +689,9 @@ define arm_aapcs_vfpcc void @test_vec_mul_scalar_add_uchar(i8* nocapture readonl
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; CHECK-NEXT: cset r5, hi
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; CHECK-NEXT: cmp r4, r3
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; CHECK-NEXT: cset r4, hi
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; CHECK-NEXT: ands r5, r4
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; CHECK-NEXT: lsls r5, r5, #31
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; CHECK-NEXT: itt eq
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; CHECK-NEXT: andeq r7, r6
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; CHECK-NEXT: lslseq.w r7, r7, #31
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; CHECK-NEXT: tst r4, r5
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; CHECK-NEXT: it eq
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; CHECK-NEXT: andseq.w r7, r7, r6
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; CHECK-NEXT: beq .LBB7_4
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; CHECK-NEXT: @ %bb.2: @ %for.body.preheader
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; CHECK-NEXT: sub.w r4, r12, #1
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@ -989,11 +985,9 @@ define arm_aapcs_vfpcc void @test_vec_mul_scalar_add_int(i32* nocapture readonly
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; CHECK-NEXT: cset r5, hi
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; CHECK-NEXT: cmp r4, r3
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; CHECK-NEXT: cset r4, hi
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; CHECK-NEXT: ands r5, r4
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; CHECK-NEXT: lsls r5, r5, #31
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; CHECK-NEXT: itt eq
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; CHECK-NEXT: andeq r7, r6
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; CHECK-NEXT: lslseq.w r7, r7, #31
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; CHECK-NEXT: tst r4, r5
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; CHECK-NEXT: it eq
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; CHECK-NEXT: andseq.w r7, r7, r6
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; CHECK-NEXT: beq .LBB9_4
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; CHECK-NEXT: @ %bb.2: @ %for.body.preheader
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; CHECK-NEXT: sub.w r4, r12, #1
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@ -661,7 +661,7 @@ define i32 @wrongop(%struct.date* nocapture readonly %pd) {
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; CHECK-NEXT: movw r3, :lower16:days
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; CHECK-NEXT: movs r4, #52
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; CHECK-NEXT: movt r3, :upper16:days
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; CHECK-NEXT: mla r1, r1, r4, r3
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; CHECK-NEXT: smlabb r1, r1, r4, r3
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; CHECK-NEXT: movs r3, #0
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; CHECK-NEXT: vdup.32 q0, r3
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; CHECK-NEXT: vmov.32 q0[0], r0
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@ -464,11 +464,11 @@ define void @test_width2(i32* nocapture readnone %x, i32* nocapture %y, i8 zeroe
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; CHECK-NEXT: eor.w r0, r5, r3
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; CHECK-NEXT: orrs.w r0, r0, r12
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; CHECK-NEXT: cset r0, ne
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; CHECK-NEXT: tst.w r0, #1
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; CHECK-NEXT: cmp r0, #0
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; CHECK-NEXT: csetm r0, ne
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; CHECK-NEXT: teq.w r7, r9
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; CHECK-NEXT: cset r2, ne
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; CHECK-NEXT: tst.w r2, #1
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; CHECK-NEXT: cmp r2, #0
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; CHECK-NEXT: csetm r2, ne
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; CHECK-NEXT: vmov q4[2], q4[0], r2, r0
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; CHECK-NEXT: vmov q4[3], q4[1], r2, r0
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@ -4,26 +4,26 @@
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define arm_aapcs_vfpcc <2 x i64> @ctlz_2i64_0_t(<2 x i64> %src){
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; CHECK-LABEL: ctlz_2i64_0_t:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov r2, s2
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; CHECK-NEXT: vmov r0, s3
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; CHECK-NEXT: clz r2, r2
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; CHECK-NEXT: cmp r0, #0
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; CHECK-NEXT: add.w r2, r2, #32
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; CHECK-NEXT: cset r1, ne
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; CHECK-NEXT: lsls r1, r1, #31
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; CHECK-NEXT: vmov r1, s2
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; CHECK-NEXT: clz r1, r1
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; CHECK-NEXT: add.w r1, r1, #32
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; CHECK-NEXT: cmp r1, #0
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; CHECK-NEXT: it ne
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; CHECK-NEXT: clzne r1, r0
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; CHECK-NEXT: clzne r2, r0
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; CHECK-NEXT: vmov s6, r2
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; CHECK-NEXT: vmov r2, s0
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; CHECK-NEXT: vmov r0, s1
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; CHECK-NEXT: vmov s6, r1
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; CHECK-NEXT: clz r2, r2
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; CHECK-NEXT: cmp r0, #0
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; CHECK-NEXT: add.w r2, r2, #32
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; CHECK-NEXT: cset r1, ne
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; CHECK-NEXT: lsls r1, r1, #31
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; CHECK-NEXT: vmov r1, s0
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; CHECK-NEXT: clz r1, r1
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; CHECK-NEXT: add.w r1, r1, #32
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; CHECK-NEXT: cmp r1, #0
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; CHECK-NEXT: it ne
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; CHECK-NEXT: clzne r1, r0
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; CHECK-NEXT: vmov s4, r1
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; CHECK-NEXT: clzne r2, r0
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; CHECK-NEXT: vmov s4, r2
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; CHECK-NEXT: vldr s5, .LCPI0_0
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; CHECK-NEXT: vmov.f32 s7, s5
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; CHECK-NEXT: vmov q0, q1
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@ -70,26 +70,26 @@ entry:
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define arm_aapcs_vfpcc <2 x i64> @ctlz_2i64_1_t(<2 x i64> %src){
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; CHECK-LABEL: ctlz_2i64_1_t:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov r2, s2
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; CHECK-NEXT: vmov r0, s3
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; CHECK-NEXT: clz r2, r2
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; CHECK-NEXT: cmp r0, #0
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; CHECK-NEXT: add.w r2, r2, #32
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; CHECK-NEXT: cset r1, ne
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; CHECK-NEXT: lsls r1, r1, #31
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; CHECK-NEXT: vmov r1, s2
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; CHECK-NEXT: clz r1, r1
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; CHECK-NEXT: add.w r1, r1, #32
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; CHECK-NEXT: cmp r1, #0
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; CHECK-NEXT: it ne
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; CHECK-NEXT: clzne r1, r0
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; CHECK-NEXT: clzne r2, r0
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; CHECK-NEXT: vmov s6, r2
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; CHECK-NEXT: vmov r2, s0
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; CHECK-NEXT: vmov r0, s1
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; CHECK-NEXT: vmov s6, r1
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; CHECK-NEXT: clz r2, r2
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; CHECK-NEXT: cmp r0, #0
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; CHECK-NEXT: add.w r2, r2, #32
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; CHECK-NEXT: cset r1, ne
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; CHECK-NEXT: lsls r1, r1, #31
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; CHECK-NEXT: vmov r1, s0
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; CHECK-NEXT: clz r1, r1
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; CHECK-NEXT: add.w r1, r1, #32
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; CHECK-NEXT: cmp r1, #0
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; CHECK-NEXT: it ne
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; CHECK-NEXT: clzne r1, r0
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; CHECK-NEXT: vmov s4, r1
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; CHECK-NEXT: clzne r2, r0
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; CHECK-NEXT: vmov s4, r2
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; CHECK-NEXT: vldr s5, .LCPI4_0
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; CHECK-NEXT: vmov.f32 s7, s5
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; CHECK-NEXT: vmov q0, q1
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@ -4,33 +4,33 @@
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define arm_aapcs_vfpcc <2 x i64> @cttz_2i64_0_t(<2 x i64> %src){
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; CHECK-LABEL: cttz_2i64_0_t:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov r0, s2
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; CHECK-NEXT: vmov q1, q0
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; CHECK-NEXT: vmov r2, s7
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; CHECK-NEXT: vmov r0, s6
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; CHECK-NEXT: rbit r2, r2
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; CHECK-NEXT: cmp r0, #0
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; CHECK-NEXT: rbit r0, r0
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; CHECK-NEXT: clz r2, r2
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; CHECK-NEXT: cset r1, ne
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; CHECK-NEXT: lsls r1, r1, #31
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; CHECK-NEXT: vmov r1, s3
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; CHECK-NEXT: rbit r1, r1
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; CHECK-NEXT: clz r1, r1
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; CHECK-NEXT: add.w r1, r1, #32
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; CHECK-NEXT: adds r2, #32
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; CHECK-NEXT: rbit r0, r0
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; CHECK-NEXT: cmp r1, #0
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; CHECK-NEXT: it ne
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; CHECK-NEXT: clzne r1, r0
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; CHECK-NEXT: vmov r0, s0
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; CHECK-NEXT: vmov s6, r1
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; CHECK-NEXT: clzne r2, r0
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; CHECK-NEXT: vmov s2, r2
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; CHECK-NEXT: vmov r2, s5
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; CHECK-NEXT: vmov r0, s4
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; CHECK-NEXT: rbit r2, r2
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; CHECK-NEXT: cmp r0, #0
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; CHECK-NEXT: rbit r0, r0
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; CHECK-NEXT: clz r2, r2
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; CHECK-NEXT: cset r1, ne
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; CHECK-NEXT: lsls r1, r1, #31
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; CHECK-NEXT: vmov r1, s1
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; CHECK-NEXT: rbit r1, r1
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; CHECK-NEXT: clz r1, r1
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; CHECK-NEXT: add.w r1, r1, #32
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; CHECK-NEXT: adds r2, #32
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; CHECK-NEXT: rbit r0, r0
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; CHECK-NEXT: cmp r1, #0
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; CHECK-NEXT: it ne
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; CHECK-NEXT: clzne r1, r0
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; CHECK-NEXT: vmov s4, r1
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; CHECK-NEXT: vldr s5, .LCPI0_0
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; CHECK-NEXT: vmov.f32 s7, s5
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; CHECK-NEXT: vmov q0, q1
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; CHECK-NEXT: clzne r2, r0
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; CHECK-NEXT: vmov s0, r2
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; CHECK-NEXT: vldr s1, .LCPI0_0
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; CHECK-NEXT: vmov.f32 s3, s1
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; CHECK-NEXT: bx lr
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; CHECK-NEXT: .p2align 2
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; CHECK-NEXT: @ %bb.1:
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@ -80,33 +80,33 @@ entry:
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define arm_aapcs_vfpcc <2 x i64> @cttz_2i64_1_t(<2 x i64> %src){
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; CHECK-LABEL: cttz_2i64_1_t:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov r0, s2
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; CHECK-NEXT: vmov q1, q0
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; CHECK-NEXT: vmov r2, s7
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; CHECK-NEXT: vmov r0, s6
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; CHECK-NEXT: rbit r2, r2
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; CHECK-NEXT: cmp r0, #0
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; CHECK-NEXT: rbit r0, r0
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; CHECK-NEXT: clz r2, r2
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; CHECK-NEXT: cset r1, ne
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; CHECK-NEXT: lsls r1, r1, #31
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; CHECK-NEXT: vmov r1, s3
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; CHECK-NEXT: rbit r1, r1
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; CHECK-NEXT: clz r1, r1
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; CHECK-NEXT: add.w r1, r1, #32
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; CHECK-NEXT: adds r2, #32
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; CHECK-NEXT: rbit r0, r0
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; CHECK-NEXT: cmp r1, #0
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; CHECK-NEXT: it ne
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; CHECK-NEXT: clzne r1, r0
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; CHECK-NEXT: vmov r0, s0
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; CHECK-NEXT: vmov s6, r1
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; CHECK-NEXT: clzne r2, r0
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; CHECK-NEXT: vmov s2, r2
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; CHECK-NEXT: vmov r2, s5
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; CHECK-NEXT: vmov r0, s4
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; CHECK-NEXT: rbit r2, r2
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; CHECK-NEXT: cmp r0, #0
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; CHECK-NEXT: rbit r0, r0
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; CHECK-NEXT: clz r2, r2
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; CHECK-NEXT: cset r1, ne
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; CHECK-NEXT: lsls r1, r1, #31
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; CHECK-NEXT: vmov r1, s1
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; CHECK-NEXT: rbit r1, r1
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; CHECK-NEXT: clz r1, r1
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; CHECK-NEXT: add.w r1, r1, #32
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; CHECK-NEXT: adds r2, #32
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; CHECK-NEXT: rbit r0, r0
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; CHECK-NEXT: cmp r1, #0
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; CHECK-NEXT: it ne
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; CHECK-NEXT: clzne r1, r0
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; CHECK-NEXT: vmov s4, r1
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; CHECK-NEXT: vldr s5, .LCPI4_0
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; CHECK-NEXT: vmov.f32 s7, s5
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; CHECK-NEXT: vmov q0, q1
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; CHECK-NEXT: clzne r2, r0
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; CHECK-NEXT: vmov s0, r2
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; CHECK-NEXT: vldr s1, .LCPI4_0
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; CHECK-NEXT: vmov.f32 s3, s1
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; CHECK-NEXT: bx lr
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; CHECK-NEXT: .p2align 2
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; CHECK-NEXT: @ %bb.1:
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@ -412,10 +412,10 @@ define arm_aapcs_vfpcc <8 x half> @vfma16_v1_pred(<8 x half> %src1, <8 x half> %
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; CHECK-MVE-NEXT: movmi r1, #1
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: vmovx.f16 s12, s8
|
||||
; CHECK-MVE-NEXT: cset r1, ne
|
||||
; CHECK-MVE-NEXT: vmov.f32 s15, s13
|
||||
; CHECK-MVE-NEXT: lsls r1, r1, #31
|
||||
; CHECK-MVE-NEXT: cset r1, ne
|
||||
; CHECK-MVE-NEXT: vmla.f16 s15, s14, s12
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: vcmp.f16 s4, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f16 s16, s13, s15
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
@ -423,10 +423,10 @@ define arm_aapcs_vfpcc <8 x half> @vfma16_v1_pred(<8 x half> %src1, <8 x half> %
|
||||
; CHECK-MVE-NEXT: it mi
|
||||
; CHECK-MVE-NEXT: movmi r1, #1
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: cset r1, ne
|
||||
; CHECK-MVE-NEXT: vmov.f32 s12, s0
|
||||
; CHECK-MVE-NEXT: cset r1, ne
|
||||
; CHECK-MVE-NEXT: vmovx.f16 s18, s5
|
||||
; CHECK-MVE-NEXT: lsls r1, r1, #31
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: vmla.f16 s12, s4, s8
|
||||
; CHECK-MVE-NEXT: vcmp.f16 s18, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f16 s12, s0, s12
|
||||
@ -440,8 +440,8 @@ define arm_aapcs_vfpcc <8 x half> @vfma16_v1_pred(<8 x half> %src1, <8 x half> %
|
||||
; CHECK-MVE-NEXT: vins.f16 s12, s16
|
||||
; CHECK-MVE-NEXT: vmovx.f16 s16, s9
|
||||
; CHECK-MVE-NEXT: vmov.f32 s22, s20
|
||||
; CHECK-MVE-NEXT: lsls r1, r1, #31
|
||||
; CHECK-MVE-NEXT: vmla.f16 s22, s18, s16
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: vcmp.f16 s5, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f16 s16, s20, s22
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
@ -449,9 +449,9 @@ define arm_aapcs_vfpcc <8 x half> @vfma16_v1_pred(<8 x half> %src1, <8 x half> %
|
||||
; CHECK-MVE-NEXT: it mi
|
||||
; CHECK-MVE-NEXT: movmi r1, #1
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: cset r1, ne
|
||||
; CHECK-MVE-NEXT: vmov.f32 s18, s1
|
||||
; CHECK-MVE-NEXT: lsls r1, r1, #31
|
||||
; CHECK-MVE-NEXT: cset r1, ne
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: vmla.f16 s18, s5, s9
|
||||
; CHECK-MVE-NEXT: vseleq.f16 s13, s1, s18
|
||||
; CHECK-MVE-NEXT: vmovx.f16 s18, s6
|
||||
@ -466,8 +466,8 @@ define arm_aapcs_vfpcc <8 x half> @vfma16_v1_pred(<8 x half> %src1, <8 x half> %
|
||||
; CHECK-MVE-NEXT: vins.f16 s13, s16
|
||||
; CHECK-MVE-NEXT: vmovx.f16 s16, s10
|
||||
; CHECK-MVE-NEXT: vmov.f32 s22, s20
|
||||
; CHECK-MVE-NEXT: lsls r1, r1, #31
|
||||
; CHECK-MVE-NEXT: vmla.f16 s22, s18, s16
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: vcmp.f16 s6, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f16 s16, s20, s22
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
@ -475,9 +475,9 @@ define arm_aapcs_vfpcc <8 x half> @vfma16_v1_pred(<8 x half> %src1, <8 x half> %
|
||||
; CHECK-MVE-NEXT: it mi
|
||||
; CHECK-MVE-NEXT: movmi r1, #1
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: cset r1, ne
|
||||
; CHECK-MVE-NEXT: vmov.f32 s18, s2
|
||||
; CHECK-MVE-NEXT: lsls r1, r1, #31
|
||||
; CHECK-MVE-NEXT: cset r1, ne
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: vmla.f16 s18, s6, s10
|
||||
; CHECK-MVE-NEXT: vseleq.f16 s14, s2, s18
|
||||
; CHECK-MVE-NEXT: vmovx.f16 s18, s7
|
||||
@ -493,7 +493,7 @@ define arm_aapcs_vfpcc <8 x half> @vfma16_v1_pred(<8 x half> %src1, <8 x half> %
|
||||
; CHECK-MVE-NEXT: vmovx.f16 s16, s11
|
||||
; CHECK-MVE-NEXT: vmov.f32 s22, s20
|
||||
; CHECK-MVE-NEXT: vmla.f16 s22, s18, s16
|
||||
; CHECK-MVE-NEXT: lsls r1, r1, #31
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: vcmp.f16 s7, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f16 s16, s20, s22
|
||||
; CHECK-MVE-NEXT: movs r0, #0
|
||||
@ -501,10 +501,10 @@ define arm_aapcs_vfpcc <8 x half> @vfma16_v1_pred(<8 x half> %src1, <8 x half> %
|
||||
; CHECK-MVE-NEXT: it mi
|
||||
; CHECK-MVE-NEXT: movmi r0, #1
|
||||
; CHECK-MVE-NEXT: cmp r0, #0
|
||||
; CHECK-MVE-NEXT: cset r0, ne
|
||||
; CHECK-MVE-NEXT: vmov.f32 s18, s3
|
||||
; CHECK-MVE-NEXT: cset r0, ne
|
||||
; CHECK-MVE-NEXT: vmla.f16 s18, s7, s11
|
||||
; CHECK-MVE-NEXT: lsls r0, r0, #31
|
||||
; CHECK-MVE-NEXT: cmp r0, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f16 s15, s3, s18
|
||||
; CHECK-MVE-NEXT: vins.f16 s15, s16
|
||||
; CHECK-MVE-NEXT: vmov q0, q3
|
||||
@ -545,10 +545,10 @@ define arm_aapcs_vfpcc <8 x half> @vfma16_v2_pred(<8 x half> %src1, <8 x half> %
|
||||
; CHECK-MVE-NEXT: movmi r1, #1
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: vmovx.f16 s12, s8
|
||||
; CHECK-MVE-NEXT: cset r1, ne
|
||||
; CHECK-MVE-NEXT: vmov.f32 s15, s13
|
||||
; CHECK-MVE-NEXT: lsls r1, r1, #31
|
||||
; CHECK-MVE-NEXT: cset r1, ne
|
||||
; CHECK-MVE-NEXT: vmla.f16 s15, s14, s12
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: vcmp.f16 s4, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f16 s16, s13, s15
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
@ -556,10 +556,10 @@ define arm_aapcs_vfpcc <8 x half> @vfma16_v2_pred(<8 x half> %src1, <8 x half> %
|
||||
; CHECK-MVE-NEXT: it mi
|
||||
; CHECK-MVE-NEXT: movmi r1, #1
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: cset r1, ne
|
||||
; CHECK-MVE-NEXT: vmov.f32 s12, s0
|
||||
; CHECK-MVE-NEXT: cset r1, ne
|
||||
; CHECK-MVE-NEXT: vmovx.f16 s18, s5
|
||||
; CHECK-MVE-NEXT: lsls r1, r1, #31
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: vmla.f16 s12, s4, s8
|
||||
; CHECK-MVE-NEXT: vcmp.f16 s18, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f16 s12, s0, s12
|
||||
@ -573,8 +573,8 @@ define arm_aapcs_vfpcc <8 x half> @vfma16_v2_pred(<8 x half> %src1, <8 x half> %
|
||||
; CHECK-MVE-NEXT: vins.f16 s12, s16
|
||||
; CHECK-MVE-NEXT: vmovx.f16 s16, s9
|
||||
; CHECK-MVE-NEXT: vmov.f32 s22, s20
|
||||
; CHECK-MVE-NEXT: lsls r1, r1, #31
|
||||
; CHECK-MVE-NEXT: vmla.f16 s22, s18, s16
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: vcmp.f16 s5, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f16 s16, s20, s22
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
@ -582,9 +582,9 @@ define arm_aapcs_vfpcc <8 x half> @vfma16_v2_pred(<8 x half> %src1, <8 x half> %
|
||||
; CHECK-MVE-NEXT: it mi
|
||||
; CHECK-MVE-NEXT: movmi r1, #1
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: cset r1, ne
|
||||
; CHECK-MVE-NEXT: vmov.f32 s18, s1
|
||||
; CHECK-MVE-NEXT: lsls r1, r1, #31
|
||||
; CHECK-MVE-NEXT: cset r1, ne
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: vmla.f16 s18, s5, s9
|
||||
; CHECK-MVE-NEXT: vseleq.f16 s13, s1, s18
|
||||
; CHECK-MVE-NEXT: vmovx.f16 s18, s6
|
||||
@ -599,8 +599,8 @@ define arm_aapcs_vfpcc <8 x half> @vfma16_v2_pred(<8 x half> %src1, <8 x half> %
|
||||
; CHECK-MVE-NEXT: vins.f16 s13, s16
|
||||
; CHECK-MVE-NEXT: vmovx.f16 s16, s10
|
||||
; CHECK-MVE-NEXT: vmov.f32 s22, s20
|
||||
; CHECK-MVE-NEXT: lsls r1, r1, #31
|
||||
; CHECK-MVE-NEXT: vmla.f16 s22, s18, s16
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: vcmp.f16 s6, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f16 s16, s20, s22
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
@ -608,9 +608,9 @@ define arm_aapcs_vfpcc <8 x half> @vfma16_v2_pred(<8 x half> %src1, <8 x half> %
|
||||
; CHECK-MVE-NEXT: it mi
|
||||
; CHECK-MVE-NEXT: movmi r1, #1
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: cset r1, ne
|
||||
; CHECK-MVE-NEXT: vmov.f32 s18, s2
|
||||
; CHECK-MVE-NEXT: lsls r1, r1, #31
|
||||
; CHECK-MVE-NEXT: cset r1, ne
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: vmla.f16 s18, s6, s10
|
||||
; CHECK-MVE-NEXT: vseleq.f16 s14, s2, s18
|
||||
; CHECK-MVE-NEXT: vmovx.f16 s18, s7
|
||||
@ -626,7 +626,7 @@ define arm_aapcs_vfpcc <8 x half> @vfma16_v2_pred(<8 x half> %src1, <8 x half> %
|
||||
; CHECK-MVE-NEXT: vmovx.f16 s16, s11
|
||||
; CHECK-MVE-NEXT: vmov.f32 s22, s20
|
||||
; CHECK-MVE-NEXT: vmla.f16 s22, s18, s16
|
||||
; CHECK-MVE-NEXT: lsls r1, r1, #31
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: vcmp.f16 s7, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f16 s16, s20, s22
|
||||
; CHECK-MVE-NEXT: movs r0, #0
|
||||
@ -634,10 +634,10 @@ define arm_aapcs_vfpcc <8 x half> @vfma16_v2_pred(<8 x half> %src1, <8 x half> %
|
||||
; CHECK-MVE-NEXT: it mi
|
||||
; CHECK-MVE-NEXT: movmi r0, #1
|
||||
; CHECK-MVE-NEXT: cmp r0, #0
|
||||
; CHECK-MVE-NEXT: cset r0, ne
|
||||
; CHECK-MVE-NEXT: vmov.f32 s18, s3
|
||||
; CHECK-MVE-NEXT: cset r0, ne
|
||||
; CHECK-MVE-NEXT: vmla.f16 s18, s7, s11
|
||||
; CHECK-MVE-NEXT: lsls r0, r0, #31
|
||||
; CHECK-MVE-NEXT: cmp r0, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f16 s15, s3, s18
|
||||
; CHECK-MVE-NEXT: vins.f16 s15, s16
|
||||
; CHECK-MVE-NEXT: vmov q0, q3
|
||||
@ -678,10 +678,10 @@ define arm_aapcs_vfpcc <8 x half> @vfms16_pred(<8 x half> %src1, <8 x half> %src
|
||||
; CHECK-MVE-NEXT: movmi r1, #1
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: vmovx.f16 s12, s8
|
||||
; CHECK-MVE-NEXT: cset r1, ne
|
||||
; CHECK-MVE-NEXT: vmov.f32 s15, s13
|
||||
; CHECK-MVE-NEXT: lsls r1, r1, #31
|
||||
; CHECK-MVE-NEXT: cset r1, ne
|
||||
; CHECK-MVE-NEXT: vmls.f16 s15, s14, s12
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: vcmp.f16 s4, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f16 s16, s13, s15
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
@ -689,10 +689,10 @@ define arm_aapcs_vfpcc <8 x half> @vfms16_pred(<8 x half> %src1, <8 x half> %src
|
||||
; CHECK-MVE-NEXT: it mi
|
||||
; CHECK-MVE-NEXT: movmi r1, #1
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: cset r1, ne
|
||||
; CHECK-MVE-NEXT: vmov.f32 s12, s0
|
||||
; CHECK-MVE-NEXT: cset r1, ne
|
||||
; CHECK-MVE-NEXT: vmovx.f16 s18, s5
|
||||
; CHECK-MVE-NEXT: lsls r1, r1, #31
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: vmls.f16 s12, s4, s8
|
||||
; CHECK-MVE-NEXT: vcmp.f16 s18, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f16 s12, s0, s12
|
||||
@ -706,8 +706,8 @@ define arm_aapcs_vfpcc <8 x half> @vfms16_pred(<8 x half> %src1, <8 x half> %src
|
||||
; CHECK-MVE-NEXT: vins.f16 s12, s16
|
||||
; CHECK-MVE-NEXT: vmovx.f16 s16, s9
|
||||
; CHECK-MVE-NEXT: vmov.f32 s22, s20
|
||||
; CHECK-MVE-NEXT: lsls r1, r1, #31
|
||||
; CHECK-MVE-NEXT: vmls.f16 s22, s18, s16
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: vcmp.f16 s5, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f16 s16, s20, s22
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
@ -715,9 +715,9 @@ define arm_aapcs_vfpcc <8 x half> @vfms16_pred(<8 x half> %src1, <8 x half> %src
|
||||
; CHECK-MVE-NEXT: it mi
|
||||
; CHECK-MVE-NEXT: movmi r1, #1
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: cset r1, ne
|
||||
; CHECK-MVE-NEXT: vmov.f32 s18, s1
|
||||
; CHECK-MVE-NEXT: lsls r1, r1, #31
|
||||
; CHECK-MVE-NEXT: cset r1, ne
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: vmls.f16 s18, s5, s9
|
||||
; CHECK-MVE-NEXT: vseleq.f16 s13, s1, s18
|
||||
; CHECK-MVE-NEXT: vmovx.f16 s18, s6
|
||||
@ -732,8 +732,8 @@ define arm_aapcs_vfpcc <8 x half> @vfms16_pred(<8 x half> %src1, <8 x half> %src
|
||||
; CHECK-MVE-NEXT: vins.f16 s13, s16
|
||||
; CHECK-MVE-NEXT: vmovx.f16 s16, s10
|
||||
; CHECK-MVE-NEXT: vmov.f32 s22, s20
|
||||
; CHECK-MVE-NEXT: lsls r1, r1, #31
|
||||
; CHECK-MVE-NEXT: vmls.f16 s22, s18, s16
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: vcmp.f16 s6, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f16 s16, s20, s22
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
@ -741,9 +741,9 @@ define arm_aapcs_vfpcc <8 x half> @vfms16_pred(<8 x half> %src1, <8 x half> %src
|
||||
; CHECK-MVE-NEXT: it mi
|
||||
; CHECK-MVE-NEXT: movmi r1, #1
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: cset r1, ne
|
||||
; CHECK-MVE-NEXT: vmov.f32 s18, s2
|
||||
; CHECK-MVE-NEXT: lsls r1, r1, #31
|
||||
; CHECK-MVE-NEXT: cset r1, ne
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: vmls.f16 s18, s6, s10
|
||||
; CHECK-MVE-NEXT: vseleq.f16 s14, s2, s18
|
||||
; CHECK-MVE-NEXT: vmovx.f16 s18, s7
|
||||
@ -759,7 +759,7 @@ define arm_aapcs_vfpcc <8 x half> @vfms16_pred(<8 x half> %src1, <8 x half> %src
|
||||
; CHECK-MVE-NEXT: vmovx.f16 s16, s11
|
||||
; CHECK-MVE-NEXT: vmov.f32 s22, s20
|
||||
; CHECK-MVE-NEXT: vmls.f16 s22, s18, s16
|
||||
; CHECK-MVE-NEXT: lsls r1, r1, #31
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: vcmp.f16 s7, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f16 s16, s20, s22
|
||||
; CHECK-MVE-NEXT: movs r0, #0
|
||||
@ -767,10 +767,10 @@ define arm_aapcs_vfpcc <8 x half> @vfms16_pred(<8 x half> %src1, <8 x half> %src
|
||||
; CHECK-MVE-NEXT: it mi
|
||||
; CHECK-MVE-NEXT: movmi r0, #1
|
||||
; CHECK-MVE-NEXT: cmp r0, #0
|
||||
; CHECK-MVE-NEXT: cset r0, ne
|
||||
; CHECK-MVE-NEXT: vmov.f32 s18, s3
|
||||
; CHECK-MVE-NEXT: cset r0, ne
|
||||
; CHECK-MVE-NEXT: vmls.f16 s18, s7, s11
|
||||
; CHECK-MVE-NEXT: lsls r0, r0, #31
|
||||
; CHECK-MVE-NEXT: cmp r0, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f16 s15, s3, s18
|
||||
; CHECK-MVE-NEXT: vins.f16 s15, s16
|
||||
; CHECK-MVE-NEXT: vmov q0, q3
|
||||
@ -814,10 +814,10 @@ define arm_aapcs_vfpcc <8 x half> @vfmar16_pred(<8 x half> %src1, <8 x half> %sr
|
||||
; CHECK-MVE-NEXT: movmi r1, #1
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: vmovx.f16 s10, s0
|
||||
; CHECK-MVE-NEXT: cset r1, ne
|
||||
; CHECK-MVE-NEXT: vmov.f32 s14, s10
|
||||
; CHECK-MVE-NEXT: lsls r1, r1, #31
|
||||
; CHECK-MVE-NEXT: cset r1, ne
|
||||
; CHECK-MVE-NEXT: vmla.f16 s14, s8, s12
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: vcmp.f16 s4, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f16 s14, s10, s14
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
@ -825,9 +825,9 @@ define arm_aapcs_vfpcc <8 x half> @vfmar16_pred(<8 x half> %src1, <8 x half> %sr
|
||||
; CHECK-MVE-NEXT: it mi
|
||||
; CHECK-MVE-NEXT: movmi r1, #1
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: cset r1, ne
|
||||
; CHECK-MVE-NEXT: vmov.f32 s8, s0
|
||||
; CHECK-MVE-NEXT: lsls r1, r1, #31
|
||||
; CHECK-MVE-NEXT: cset r1, ne
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: vmla.f16 s8, s4, s12
|
||||
; CHECK-MVE-NEXT: vseleq.f16 s8, s0, s8
|
||||
; CHECK-MVE-NEXT: movs r1, #0
|
||||
@ -842,7 +842,7 @@ define arm_aapcs_vfpcc <8 x half> @vfmar16_pred(<8 x half> %src1, <8 x half> %sr
|
||||
; CHECK-MVE-NEXT: vmov.f32 s15, s13
|
||||
; CHECK-MVE-NEXT: cset r1, ne
|
||||
; CHECK-MVE-NEXT: vmla.f16 s15, s14, s12
|
||||
; CHECK-MVE-NEXT: lsls r1, r1, #31
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: vcmp.f16 s5, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f16 s14, s13, s15
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
@ -853,33 +853,32 @@ define arm_aapcs_vfpcc <8 x half> @vfmar16_pred(<8 x half> %src1, <8 x half> %sr
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: cset r1, ne
|
||||
; CHECK-MVE-NEXT: vmla.f16 s13, s5, s12
|
||||
; CHECK-MVE-NEXT: lsls r1, r1, #31
|
||||
; CHECK-MVE-NEXT: mov.w r0, #0
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: mov.w r1, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f16 s9, s1, s13
|
||||
; CHECK-MVE-NEXT: movs r1, #0
|
||||
; CHECK-MVE-NEXT: vmovx.f16 s13, s2
|
||||
; CHECK-MVE-NEXT: vins.f16 s9, s14
|
||||
; CHECK-MVE-NEXT: vmovx.f16 s14, s6
|
||||
; CHECK-MVE-NEXT: vcmp.f16 s14, #0
|
||||
; CHECK-MVE-NEXT: vmovx.f16 s13, s2
|
||||
; CHECK-MVE-NEXT: vmov.f32 s15, s13
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: it mi
|
||||
; CHECK-MVE-NEXT: movmi r1, #1
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: vmov.f32 s15, s13
|
||||
; CHECK-MVE-NEXT: cset r1, ne
|
||||
; CHECK-MVE-NEXT: vmla.f16 s15, s14, s12
|
||||
; CHECK-MVE-NEXT: lsls r1, r1, #31
|
||||
; CHECK-MVE-NEXT: cset r1, ne
|
||||
; CHECK-MVE-NEXT: vcmp.f16 s6, #0
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: mov.w r1, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f16 s14, s13, s15
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: mov.w r1, #0
|
||||
; CHECK-MVE-NEXT: vmov.f32 s13, s2
|
||||
; CHECK-MVE-NEXT: it mi
|
||||
; CHECK-MVE-NEXT: movmi r1, #1
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: vmov.f32 s13, s2
|
||||
; CHECK-MVE-NEXT: cset r1, ne
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: vmla.f16 s13, s6, s12
|
||||
; CHECK-MVE-NEXT: lsls r1, r1, #31
|
||||
; CHECK-MVE-NEXT: vseleq.f16 s10, s2, s13
|
||||
; CHECK-MVE-NEXT: movs r1, #0
|
||||
; CHECK-MVE-NEXT: vins.f16 s10, s14
|
||||
@ -893,17 +892,18 @@ define arm_aapcs_vfpcc <8 x half> @vfmar16_pred(<8 x half> %src1, <8 x half> %sr
|
||||
; CHECK-MVE-NEXT: vmov.f32 s15, s13
|
||||
; CHECK-MVE-NEXT: cset r1, ne
|
||||
; CHECK-MVE-NEXT: vmla.f16 s15, s14, s12
|
||||
; CHECK-MVE-NEXT: lsls r1, r1, #31
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: vcmp.f16 s7, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f16 s14, s13, s15
|
||||
; CHECK-MVE-NEXT: movs r0, #0
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: it mi
|
||||
; CHECK-MVE-NEXT: movmi r0, #1
|
||||
; CHECK-MVE-NEXT: cmp r0, #0
|
||||
; CHECK-MVE-NEXT: cset r0, ne
|
||||
; CHECK-MVE-NEXT: vmov.f32 s13, s3
|
||||
; CHECK-MVE-NEXT: cset r0, ne
|
||||
; CHECK-MVE-NEXT: vmla.f16 s13, s7, s12
|
||||
; CHECK-MVE-NEXT: lsls r0, r0, #31
|
||||
; CHECK-MVE-NEXT: cmp r0, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f16 s11, s3, s13
|
||||
; CHECK-MVE-NEXT: vins.f16 s11, s14
|
||||
; CHECK-MVE-NEXT: vmov q0, q2
|
||||
@ -948,9 +948,9 @@ define arm_aapcs_vfpcc <8 x half> @vfma16_pred(<8 x half> %src1, <8 x half> %src
|
||||
; CHECK-MVE-NEXT: movmi r1, #1
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: vmovx.f16 s14, s0
|
||||
; CHECK-MVE-NEXT: cset r1, ne
|
||||
; CHECK-MVE-NEXT: vmov.f32 s8, s12
|
||||
; CHECK-MVE-NEXT: lsls r1, r1, #31
|
||||
; CHECK-MVE-NEXT: cset r1, ne
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: vmla.f16 s8, s14, s10
|
||||
; CHECK-MVE-NEXT: vcmp.f16 s4, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f16 s14, s14, s8
|
||||
@ -959,9 +959,9 @@ define arm_aapcs_vfpcc <8 x half> @vfma16_pred(<8 x half> %src1, <8 x half> %src
|
||||
; CHECK-MVE-NEXT: it mi
|
||||
; CHECK-MVE-NEXT: movmi r1, #1
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: cset r1, ne
|
||||
; CHECK-MVE-NEXT: vmov.f32 s8, s12
|
||||
; CHECK-MVE-NEXT: lsls r1, r1, #31
|
||||
; CHECK-MVE-NEXT: cset r1, ne
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: vmla.f16 s8, s0, s4
|
||||
; CHECK-MVE-NEXT: vseleq.f16 s8, s0, s8
|
||||
; CHECK-MVE-NEXT: movs r1, #0
|
||||
@ -976,7 +976,7 @@ define arm_aapcs_vfpcc <8 x half> @vfma16_pred(<8 x half> %src1, <8 x half> %src
|
||||
; CHECK-MVE-NEXT: vmov.f32 s15, s12
|
||||
; CHECK-MVE-NEXT: cset r1, ne
|
||||
; CHECK-MVE-NEXT: vmla.f16 s15, s13, s14
|
||||
; CHECK-MVE-NEXT: lsls r1, r1, #31
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: vcmp.f16 s5, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f16 s14, s13, s15
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
@ -987,14 +987,14 @@ define arm_aapcs_vfpcc <8 x half> @vfma16_pred(<8 x half> %src1, <8 x half> %src
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: cset r1, ne
|
||||
; CHECK-MVE-NEXT: vmla.f16 s13, s1, s5
|
||||
; CHECK-MVE-NEXT: lsls r1, r1, #31
|
||||
; CHECK-MVE-NEXT: vmov.f32 s15, s12
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: mov.w r1, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f16 s9, s1, s13
|
||||
; CHECK-MVE-NEXT: movs r1, #0
|
||||
; CHECK-MVE-NEXT: vmovx.f16 s13, s2
|
||||
; CHECK-MVE-NEXT: vins.f16 s9, s14
|
||||
; CHECK-MVE-NEXT: vmovx.f16 s14, s6
|
||||
; CHECK-MVE-NEXT: vcmp.f16 s14, #0
|
||||
; CHECK-MVE-NEXT: vmovx.f16 s13, s2
|
||||
; CHECK-MVE-NEXT: vmov.f32 s15, s12
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: it mi
|
||||
; CHECK-MVE-NEXT: movmi r1, #1
|
||||
@ -1002,41 +1002,41 @@ define arm_aapcs_vfpcc <8 x half> @vfma16_pred(<8 x half> %src1, <8 x half> %src
|
||||
; CHECK-MVE-NEXT: vmla.f16 s15, s13, s14
|
||||
; CHECK-MVE-NEXT: cset r1, ne
|
||||
; CHECK-MVE-NEXT: vcmp.f16 s6, #0
|
||||
; CHECK-MVE-NEXT: lsls r1, r1, #31
|
||||
; CHECK-MVE-NEXT: mov.w r0, #0
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: mov.w r1, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f16 s14, s13, s15
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: mov.w r1, #0
|
||||
; CHECK-MVE-NEXT: vmov.f32 s13, s12
|
||||
; CHECK-MVE-NEXT: it mi
|
||||
; CHECK-MVE-NEXT: movmi r1, #1
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: vmov.f32 s13, s12
|
||||
; CHECK-MVE-NEXT: cset r1, ne
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: vmla.f16 s13, s2, s6
|
||||
; CHECK-MVE-NEXT: lsls r1, r1, #31
|
||||
; CHECK-MVE-NEXT: vmov.f32 s15, s12
|
||||
; CHECK-MVE-NEXT: vseleq.f16 s10, s2, s13
|
||||
; CHECK-MVE-NEXT: movs r1, #0
|
||||
; CHECK-MVE-NEXT: vins.f16 s10, s14
|
||||
; CHECK-MVE-NEXT: vmovx.f16 s14, s7
|
||||
; CHECK-MVE-NEXT: vcmp.f16 s14, #0
|
||||
; CHECK-MVE-NEXT: vmovx.f16 s13, s3
|
||||
; CHECK-MVE-NEXT: vmov.f32 s15, s12
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: it mi
|
||||
; CHECK-MVE-NEXT: movmi r1, #1
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: vmla.f16 s15, s13, s14
|
||||
; CHECK-MVE-NEXT: vmovx.f16 s13, s3
|
||||
; CHECK-MVE-NEXT: cset r1, ne
|
||||
; CHECK-MVE-NEXT: vmla.f16 s15, s13, s14
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: vcmp.f16 s7, #0
|
||||
; CHECK-MVE-NEXT: lsls r1, r1, #31
|
||||
; CHECK-MVE-NEXT: vmla.f16 s12, s3, s7
|
||||
; CHECK-MVE-NEXT: vseleq.f16 s14, s13, s15
|
||||
; CHECK-MVE-NEXT: movs r0, #0
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: it mi
|
||||
; CHECK-MVE-NEXT: movmi r0, #1
|
||||
; CHECK-MVE-NEXT: cmp r0, #0
|
||||
; CHECK-MVE-NEXT: vmla.f16 s12, s3, s7
|
||||
; CHECK-MVE-NEXT: cset r0, ne
|
||||
; CHECK-MVE-NEXT: lsls r0, r0, #31
|
||||
; CHECK-MVE-NEXT: cmp r0, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f16 s11, s3, s12
|
||||
; CHECK-MVE-NEXT: vins.f16 s11, s14
|
||||
; CHECK-MVE-NEXT: vmov q0, q2
|
||||
@ -1068,50 +1068,50 @@ define arm_aapcs_vfpcc <4 x float> @vfma32_v1_pred(<4 x float> %src1, <4 x float
|
||||
;
|
||||
; CHECK-MVE-LABEL: vfma32_v1_pred:
|
||||
; CHECK-MVE: @ %bb.0: @ %entry
|
||||
; CHECK-MVE-NEXT: vcmp.f32 s4, #0
|
||||
; CHECK-MVE-NEXT: vcmp.f32 s5, #0
|
||||
; CHECK-MVE-NEXT: movs r1, #0
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: it mi
|
||||
; CHECK-MVE-NEXT: movmi r1, #1
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: vcmp.f32 s5, #0
|
||||
; CHECK-MVE-NEXT: vcmp.f32 s4, #0
|
||||
; CHECK-MVE-NEXT: vmov.f32 s13, s3
|
||||
; CHECK-MVE-NEXT: cset r1, ne
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: mov.w r2, #0
|
||||
; CHECK-MVE-NEXT: vmov.f32 s15, s3
|
||||
; CHECK-MVE-NEXT: vmov.f32 s12, s1
|
||||
; CHECK-MVE-NEXT: it mi
|
||||
; CHECK-MVE-NEXT: movmi r2, #1
|
||||
; CHECK-MVE-NEXT: vmov.f32 s14, s0
|
||||
; CHECK-MVE-NEXT: cmp r2, #0
|
||||
; CHECK-MVE-NEXT: vcmp.f32 s6, #0
|
||||
; CHECK-MVE-NEXT: vmov.f32 s15, s2
|
||||
; CHECK-MVE-NEXT: cset r2, ne
|
||||
; CHECK-MVE-NEXT: vmov.f32 s12, s0
|
||||
; CHECK-MVE-NEXT: vcmp.f32 s7, #0
|
||||
; CHECK-MVE-NEXT: movs r3, #0
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: vmov.f32 s14, s1
|
||||
; CHECK-MVE-NEXT: mov.w r3, #0
|
||||
; CHECK-MVE-NEXT: vmov.f32 s13, s2
|
||||
; CHECK-MVE-NEXT: it mi
|
||||
; CHECK-MVE-NEXT: movmi r3, #1
|
||||
; CHECK-MVE-NEXT: cmp r3, #0
|
||||
; CHECK-MVE-NEXT: vcmp.f32 s7, #0
|
||||
; CHECK-MVE-NEXT: vcmp.f32 s6, #0
|
||||
; CHECK-MVE-NEXT: cset r3, ne
|
||||
; CHECK-MVE-NEXT: movs r0, #0
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: it mi
|
||||
; CHECK-MVE-NEXT: movmi r0, #1
|
||||
; CHECK-MVE-NEXT: cmp r0, #0
|
||||
; CHECK-MVE-NEXT: vmla.f32 s15, s7, s11
|
||||
; CHECK-MVE-NEXT: vmla.f32 s13, s7, s11
|
||||
; CHECK-MVE-NEXT: cset r0, ne
|
||||
; CHECK-MVE-NEXT: vmla.f32 s12, s4, s8
|
||||
; CHECK-MVE-NEXT: lsls r0, r0, #31
|
||||
; CHECK-MVE-NEXT: vmla.f32 s14, s5, s9
|
||||
; CHECK-MVE-NEXT: vmla.f32 s13, s6, s10
|
||||
; CHECK-MVE-NEXT: vseleq.f32 s7, s3, s15
|
||||
; CHECK-MVE-NEXT: lsls r0, r3, #31
|
||||
; CHECK-MVE-NEXT: vseleq.f32 s6, s2, s13
|
||||
; CHECK-MVE-NEXT: lsls r0, r2, #31
|
||||
; CHECK-MVE-NEXT: vseleq.f32 s5, s1, s14
|
||||
; CHECK-MVE-NEXT: lsls r0, r1, #31
|
||||
; CHECK-MVE-NEXT: vseleq.f32 s4, s0, s12
|
||||
; CHECK-MVE-NEXT: cmp r3, #0
|
||||
; CHECK-MVE-NEXT: vmla.f32 s12, s5, s9
|
||||
; CHECK-MVE-NEXT: vmla.f32 s14, s4, s8
|
||||
; CHECK-MVE-NEXT: vmla.f32 s15, s6, s10
|
||||
; CHECK-MVE-NEXT: vseleq.f32 s7, s3, s13
|
||||
; CHECK-MVE-NEXT: cmp r0, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f32 s6, s2, s15
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f32 s5, s1, s12
|
||||
; CHECK-MVE-NEXT: cmp r2, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f32 s4, s0, s14
|
||||
; CHECK-MVE-NEXT: vmov q0, q1
|
||||
; CHECK-MVE-NEXT: bx lr
|
||||
entry:
|
||||
@ -1138,50 +1138,50 @@ define arm_aapcs_vfpcc <4 x float> @vfma32_v2_pred(<4 x float> %src1, <4 x float
|
||||
;
|
||||
; CHECK-MVE-LABEL: vfma32_v2_pred:
|
||||
; CHECK-MVE: @ %bb.0: @ %entry
|
||||
; CHECK-MVE-NEXT: vcmp.f32 s4, #0
|
||||
; CHECK-MVE-NEXT: vcmp.f32 s5, #0
|
||||
; CHECK-MVE-NEXT: movs r1, #0
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: it mi
|
||||
; CHECK-MVE-NEXT: movmi r1, #1
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: vcmp.f32 s5, #0
|
||||
; CHECK-MVE-NEXT: vcmp.f32 s4, #0
|
||||
; CHECK-MVE-NEXT: vmov.f32 s13, s3
|
||||
; CHECK-MVE-NEXT: cset r1, ne
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: mov.w r2, #0
|
||||
; CHECK-MVE-NEXT: vmov.f32 s15, s3
|
||||
; CHECK-MVE-NEXT: vmov.f32 s12, s1
|
||||
; CHECK-MVE-NEXT: it mi
|
||||
; CHECK-MVE-NEXT: movmi r2, #1
|
||||
; CHECK-MVE-NEXT: vmov.f32 s14, s0
|
||||
; CHECK-MVE-NEXT: cmp r2, #0
|
||||
; CHECK-MVE-NEXT: vcmp.f32 s6, #0
|
||||
; CHECK-MVE-NEXT: vmov.f32 s15, s2
|
||||
; CHECK-MVE-NEXT: cset r2, ne
|
||||
; CHECK-MVE-NEXT: vmov.f32 s12, s0
|
||||
; CHECK-MVE-NEXT: vcmp.f32 s7, #0
|
||||
; CHECK-MVE-NEXT: movs r3, #0
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: vmov.f32 s14, s1
|
||||
; CHECK-MVE-NEXT: mov.w r3, #0
|
||||
; CHECK-MVE-NEXT: vmov.f32 s13, s2
|
||||
; CHECK-MVE-NEXT: it mi
|
||||
; CHECK-MVE-NEXT: movmi r3, #1
|
||||
; CHECK-MVE-NEXT: cmp r3, #0
|
||||
; CHECK-MVE-NEXT: vcmp.f32 s7, #0
|
||||
; CHECK-MVE-NEXT: vcmp.f32 s6, #0
|
||||
; CHECK-MVE-NEXT: cset r3, ne
|
||||
; CHECK-MVE-NEXT: movs r0, #0
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: it mi
|
||||
; CHECK-MVE-NEXT: movmi r0, #1
|
||||
; CHECK-MVE-NEXT: cmp r0, #0
|
||||
; CHECK-MVE-NEXT: vmla.f32 s15, s7, s11
|
||||
; CHECK-MVE-NEXT: vmla.f32 s13, s7, s11
|
||||
; CHECK-MVE-NEXT: cset r0, ne
|
||||
; CHECK-MVE-NEXT: vmla.f32 s12, s4, s8
|
||||
; CHECK-MVE-NEXT: lsls r0, r0, #31
|
||||
; CHECK-MVE-NEXT: vmla.f32 s14, s5, s9
|
||||
; CHECK-MVE-NEXT: vmla.f32 s13, s6, s10
|
||||
; CHECK-MVE-NEXT: vseleq.f32 s7, s3, s15
|
||||
; CHECK-MVE-NEXT: lsls r0, r3, #31
|
||||
; CHECK-MVE-NEXT: vseleq.f32 s6, s2, s13
|
||||
; CHECK-MVE-NEXT: lsls r0, r2, #31
|
||||
; CHECK-MVE-NEXT: vseleq.f32 s5, s1, s14
|
||||
; CHECK-MVE-NEXT: lsls r0, r1, #31
|
||||
; CHECK-MVE-NEXT: vseleq.f32 s4, s0, s12
|
||||
; CHECK-MVE-NEXT: cmp r3, #0
|
||||
; CHECK-MVE-NEXT: vmla.f32 s12, s5, s9
|
||||
; CHECK-MVE-NEXT: vmla.f32 s14, s4, s8
|
||||
; CHECK-MVE-NEXT: vmla.f32 s15, s6, s10
|
||||
; CHECK-MVE-NEXT: vseleq.f32 s7, s3, s13
|
||||
; CHECK-MVE-NEXT: cmp r0, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f32 s6, s2, s15
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f32 s5, s1, s12
|
||||
; CHECK-MVE-NEXT: cmp r2, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f32 s4, s0, s14
|
||||
; CHECK-MVE-NEXT: vmov q0, q1
|
||||
; CHECK-MVE-NEXT: bx lr
|
||||
entry:
|
||||
@ -1208,50 +1208,50 @@ define arm_aapcs_vfpcc <4 x float> @vfms32_pred(<4 x float> %src1, <4 x float> %
|
||||
;
|
||||
; CHECK-MVE-LABEL: vfms32_pred:
|
||||
; CHECK-MVE: @ %bb.0: @ %entry
|
||||
; CHECK-MVE-NEXT: vcmp.f32 s4, #0
|
||||
; CHECK-MVE-NEXT: vcmp.f32 s5, #0
|
||||
; CHECK-MVE-NEXT: movs r1, #0
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: it mi
|
||||
; CHECK-MVE-NEXT: movmi r1, #1
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: vcmp.f32 s5, #0
|
||||
; CHECK-MVE-NEXT: vcmp.f32 s4, #0
|
||||
; CHECK-MVE-NEXT: vmov.f32 s13, s3
|
||||
; CHECK-MVE-NEXT: cset r1, ne
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: mov.w r2, #0
|
||||
; CHECK-MVE-NEXT: vmov.f32 s15, s3
|
||||
; CHECK-MVE-NEXT: vmov.f32 s12, s1
|
||||
; CHECK-MVE-NEXT: it mi
|
||||
; CHECK-MVE-NEXT: movmi r2, #1
|
||||
; CHECK-MVE-NEXT: vmov.f32 s14, s0
|
||||
; CHECK-MVE-NEXT: cmp r2, #0
|
||||
; CHECK-MVE-NEXT: vcmp.f32 s6, #0
|
||||
; CHECK-MVE-NEXT: vmov.f32 s15, s2
|
||||
; CHECK-MVE-NEXT: cset r2, ne
|
||||
; CHECK-MVE-NEXT: vmov.f32 s12, s0
|
||||
; CHECK-MVE-NEXT: vcmp.f32 s7, #0
|
||||
; CHECK-MVE-NEXT: movs r3, #0
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: vmov.f32 s14, s1
|
||||
; CHECK-MVE-NEXT: mov.w r3, #0
|
||||
; CHECK-MVE-NEXT: vmov.f32 s13, s2
|
||||
; CHECK-MVE-NEXT: it mi
|
||||
; CHECK-MVE-NEXT: movmi r3, #1
|
||||
; CHECK-MVE-NEXT: cmp r3, #0
|
||||
; CHECK-MVE-NEXT: vcmp.f32 s7, #0
|
||||
; CHECK-MVE-NEXT: vcmp.f32 s6, #0
|
||||
; CHECK-MVE-NEXT: cset r3, ne
|
||||
; CHECK-MVE-NEXT: movs r0, #0
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: it mi
|
||||
; CHECK-MVE-NEXT: movmi r0, #1
|
||||
; CHECK-MVE-NEXT: cmp r0, #0
|
||||
; CHECK-MVE-NEXT: vmls.f32 s15, s7, s11
|
||||
; CHECK-MVE-NEXT: vmls.f32 s13, s7, s11
|
||||
; CHECK-MVE-NEXT: cset r0, ne
|
||||
; CHECK-MVE-NEXT: vmls.f32 s12, s4, s8
|
||||
; CHECK-MVE-NEXT: lsls r0, r0, #31
|
||||
; CHECK-MVE-NEXT: vmls.f32 s14, s5, s9
|
||||
; CHECK-MVE-NEXT: vmls.f32 s13, s6, s10
|
||||
; CHECK-MVE-NEXT: vseleq.f32 s7, s3, s15
|
||||
; CHECK-MVE-NEXT: lsls r0, r3, #31
|
||||
; CHECK-MVE-NEXT: vseleq.f32 s6, s2, s13
|
||||
; CHECK-MVE-NEXT: lsls r0, r2, #31
|
||||
; CHECK-MVE-NEXT: vseleq.f32 s5, s1, s14
|
||||
; CHECK-MVE-NEXT: lsls r0, r1, #31
|
||||
; CHECK-MVE-NEXT: vseleq.f32 s4, s0, s12
|
||||
; CHECK-MVE-NEXT: cmp r3, #0
|
||||
; CHECK-MVE-NEXT: vmls.f32 s12, s5, s9
|
||||
; CHECK-MVE-NEXT: vmls.f32 s14, s4, s8
|
||||
; CHECK-MVE-NEXT: vmls.f32 s15, s6, s10
|
||||
; CHECK-MVE-NEXT: vseleq.f32 s7, s3, s13
|
||||
; CHECK-MVE-NEXT: cmp r0, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f32 s6, s2, s15
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f32 s5, s1, s12
|
||||
; CHECK-MVE-NEXT: cmp r2, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f32 s4, s0, s14
|
||||
; CHECK-MVE-NEXT: vmov q0, q1
|
||||
; CHECK-MVE-NEXT: bx lr
|
||||
entry:
|
||||
@ -1281,50 +1281,50 @@ define arm_aapcs_vfpcc <4 x float> @vfmar32_pred(<4 x float> %src1, <4 x float>
|
||||
;
|
||||
; CHECK-MVE-LABEL: vfmar32_pred:
|
||||
; CHECK-MVE: @ %bb.0: @ %entry
|
||||
; CHECK-MVE-NEXT: vcmp.f32 s4, #0
|
||||
; CHECK-MVE-NEXT: vcmp.f32 s5, #0
|
||||
; CHECK-MVE-NEXT: movs r1, #0
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: it mi
|
||||
; CHECK-MVE-NEXT: movmi r1, #1
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: vcmp.f32 s5, #0
|
||||
; CHECK-MVE-NEXT: vcmp.f32 s4, #0
|
||||
; CHECK-MVE-NEXT: vmov.f32 s14, s3
|
||||
; CHECK-MVE-NEXT: cset r1, ne
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: mov.w r2, #0
|
||||
; CHECK-MVE-NEXT: vmov.f32 s9, s3
|
||||
; CHECK-MVE-NEXT: vmov.f32 s10, s1
|
||||
; CHECK-MVE-NEXT: it mi
|
||||
; CHECK-MVE-NEXT: movmi r2, #1
|
||||
; CHECK-MVE-NEXT: vmov.f32 s12, s0
|
||||
; CHECK-MVE-NEXT: cmp r2, #0
|
||||
; CHECK-MVE-NEXT: vcmp.f32 s6, #0
|
||||
; CHECK-MVE-NEXT: vmov.f32 s9, s2
|
||||
; CHECK-MVE-NEXT: cset r2, ne
|
||||
; CHECK-MVE-NEXT: vmov.f32 s10, s0
|
||||
; CHECK-MVE-NEXT: vcmp.f32 s7, #0
|
||||
; CHECK-MVE-NEXT: movs r3, #0
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: vmov.f32 s12, s1
|
||||
; CHECK-MVE-NEXT: mov.w r3, #0
|
||||
; CHECK-MVE-NEXT: vmov.f32 s14, s2
|
||||
; CHECK-MVE-NEXT: it mi
|
||||
; CHECK-MVE-NEXT: movmi r3, #1
|
||||
; CHECK-MVE-NEXT: cmp r3, #0
|
||||
; CHECK-MVE-NEXT: vcmp.f32 s7, #0
|
||||
; CHECK-MVE-NEXT: vcmp.f32 s6, #0
|
||||
; CHECK-MVE-NEXT: cset r3, ne
|
||||
; CHECK-MVE-NEXT: movs r0, #0
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: it mi
|
||||
; CHECK-MVE-NEXT: movmi r0, #1
|
||||
; CHECK-MVE-NEXT: cmp r0, #0
|
||||
; CHECK-MVE-NEXT: vmla.f32 s9, s7, s8
|
||||
; CHECK-MVE-NEXT: vmla.f32 s14, s7, s8
|
||||
; CHECK-MVE-NEXT: cset r0, ne
|
||||
; CHECK-MVE-NEXT: vmla.f32 s10, s4, s8
|
||||
; CHECK-MVE-NEXT: lsls r0, r0, #31
|
||||
; CHECK-MVE-NEXT: vmla.f32 s12, s5, s8
|
||||
; CHECK-MVE-NEXT: vmla.f32 s14, s6, s8
|
||||
; CHECK-MVE-NEXT: vseleq.f32 s7, s3, s9
|
||||
; CHECK-MVE-NEXT: lsls r0, r3, #31
|
||||
; CHECK-MVE-NEXT: vseleq.f32 s6, s2, s14
|
||||
; CHECK-MVE-NEXT: lsls r0, r2, #31
|
||||
; CHECK-MVE-NEXT: vseleq.f32 s5, s1, s12
|
||||
; CHECK-MVE-NEXT: lsls r0, r1, #31
|
||||
; CHECK-MVE-NEXT: vseleq.f32 s4, s0, s10
|
||||
; CHECK-MVE-NEXT: cmp r3, #0
|
||||
; CHECK-MVE-NEXT: vmla.f32 s10, s5, s8
|
||||
; CHECK-MVE-NEXT: vmla.f32 s12, s4, s8
|
||||
; CHECK-MVE-NEXT: vmla.f32 s9, s6, s8
|
||||
; CHECK-MVE-NEXT: vseleq.f32 s7, s3, s14
|
||||
; CHECK-MVE-NEXT: cmp r0, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f32 s6, s2, s9
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f32 s5, s1, s10
|
||||
; CHECK-MVE-NEXT: cmp r2, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f32 s4, s0, s12
|
||||
; CHECK-MVE-NEXT: vmov q0, q1
|
||||
; CHECK-MVE-NEXT: bx lr
|
||||
entry:
|
||||
@ -1355,30 +1355,30 @@ define arm_aapcs_vfpcc <4 x float> @vfmas32_pred(<4 x float> %src1, <4 x float>
|
||||
;
|
||||
; CHECK-MVE-LABEL: vfmas32_pred:
|
||||
; CHECK-MVE: @ %bb.0: @ %entry
|
||||
; CHECK-MVE-NEXT: vcmp.f32 s4, #0
|
||||
; CHECK-MVE-NEXT: vcmp.f32 s5, #0
|
||||
; CHECK-MVE-NEXT: movs r1, #0
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: it mi
|
||||
; CHECK-MVE-NEXT: movmi r1, #1
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: vcmp.f32 s5, #0
|
||||
; CHECK-MVE-NEXT: vcmp.f32 s4, #0
|
||||
; CHECK-MVE-NEXT: vmov.f32 s14, s8
|
||||
; CHECK-MVE-NEXT: cset r1, ne
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: mov.w r2, #0
|
||||
; CHECK-MVE-NEXT: vcmp.f32 s6, #0
|
||||
; CHECK-MVE-NEXT: vmov.f32 s10, s8
|
||||
; CHECK-MVE-NEXT: it mi
|
||||
; CHECK-MVE-NEXT: movmi r2, #1
|
||||
; CHECK-MVE-NEXT: cmp r2, #0
|
||||
; CHECK-MVE-NEXT: vmov.f32 s10, s8
|
||||
; CHECK-MVE-NEXT: cset r2, ne
|
||||
; CHECK-MVE-NEXT: vmov.f32 s12, s8
|
||||
; CHECK-MVE-NEXT: cmp r2, #0
|
||||
; CHECK-MVE-NEXT: vcmp.f32 s7, #0
|
||||
; CHECK-MVE-NEXT: cset r2, ne
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: vmov.f32 s14, s8
|
||||
; CHECK-MVE-NEXT: mov.w r3, #0
|
||||
; CHECK-MVE-NEXT: it mi
|
||||
; CHECK-MVE-NEXT: movmi r3, #1
|
||||
; CHECK-MVE-NEXT: cmp r3, #0
|
||||
; CHECK-MVE-NEXT: vcmp.f32 s7, #0
|
||||
; CHECK-MVE-NEXT: vcmp.f32 s6, #0
|
||||
; CHECK-MVE-NEXT: cset r3, ne
|
||||
; CHECK-MVE-NEXT: movs r0, #0
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
@ -1386,18 +1386,18 @@ define arm_aapcs_vfpcc <4 x float> @vfmas32_pred(<4 x float> %src1, <4 x float>
|
||||
; CHECK-MVE-NEXT: movmi r0, #1
|
||||
; CHECK-MVE-NEXT: cmp r0, #0
|
||||
; CHECK-MVE-NEXT: cset r0, ne
|
||||
; CHECK-MVE-NEXT: vmla.f32 s8, s3, s7
|
||||
; CHECK-MVE-NEXT: lsls r0, r0, #31
|
||||
; CHECK-MVE-NEXT: vmla.f32 s10, s0, s4
|
||||
; CHECK-MVE-NEXT: vmla.f32 s12, s1, s5
|
||||
; CHECK-MVE-NEXT: vmla.f32 s14, s2, s6
|
||||
; CHECK-MVE-NEXT: vseleq.f32 s7, s3, s8
|
||||
; CHECK-MVE-NEXT: lsls r0, r3, #31
|
||||
; CHECK-MVE-NEXT: vseleq.f32 s6, s2, s14
|
||||
; CHECK-MVE-NEXT: lsls r0, r2, #31
|
||||
; CHECK-MVE-NEXT: vseleq.f32 s5, s1, s12
|
||||
; CHECK-MVE-NEXT: lsls r0, r1, #31
|
||||
; CHECK-MVE-NEXT: vseleq.f32 s4, s0, s10
|
||||
; CHECK-MVE-NEXT: vmla.f32 s14, s3, s7
|
||||
; CHECK-MVE-NEXT: cmp r3, #0
|
||||
; CHECK-MVE-NEXT: vmla.f32 s10, s1, s5
|
||||
; CHECK-MVE-NEXT: vmla.f32 s12, s0, s4
|
||||
; CHECK-MVE-NEXT: vmla.f32 s8, s2, s6
|
||||
; CHECK-MVE-NEXT: vseleq.f32 s7, s3, s14
|
||||
; CHECK-MVE-NEXT: cmp r0, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f32 s6, s2, s8
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f32 s5, s1, s10
|
||||
; CHECK-MVE-NEXT: cmp r2, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f32 s4, s0, s12
|
||||
; CHECK-MVE-NEXT: vmov q0, q1
|
||||
; CHECK-MVE-NEXT: bx lr
|
||||
entry:
|
||||
|
||||
@ -1042,62 +1042,62 @@ define arm_aapcs_vfpcc <8 x half> @copysign_float16_t(<8 x half> %src1, <8 x hal
|
||||
; CHECK-NEXT: vneg.f16 s6, s4
|
||||
; CHECK-NEXT: tst.w r0, #128
|
||||
; CHECK-NEXT: cset r0, ne
|
||||
; CHECK-NEXT: lsls r0, r0, #31
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: ldrb.w r0, [sp, #29]
|
||||
; CHECK-NEXT: vseleq.f16 s8, s4, s6
|
||||
; CHECK-NEXT: vabs.f16 s4, s0
|
||||
; CHECK-NEXT: vabs.f16 s0, s3
|
||||
; CHECK-NEXT: tst.w r0, #128
|
||||
; CHECK-NEXT: vneg.f16 s6, s4
|
||||
; CHECK-NEXT: cset r0, ne
|
||||
; CHECK-NEXT: lsls r0, r0, #31
|
||||
; CHECK-NEXT: vabs.f16 s0, s3
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: ldrb.w r0, [sp, #17]
|
||||
; CHECK-NEXT: vseleq.f16 s4, s4, s6
|
||||
; CHECK-NEXT: tst.w r0, #128
|
||||
; CHECK-NEXT: vins.f16 s4, s8
|
||||
; CHECK-NEXT: vmovx.f16 s8, s1
|
||||
; CHECK-NEXT: tst.w r0, #128
|
||||
; CHECK-NEXT: vabs.f16 s8, s8
|
||||
; CHECK-NEXT: cset r0, ne
|
||||
; CHECK-NEXT: vneg.f16 s10, s8
|
||||
; CHECK-NEXT: lsls r0, r0, #31
|
||||
; CHECK-NEXT: vabs.f16 s8, s8
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: ldrb.w r0, [sp, #21]
|
||||
; CHECK-NEXT: vneg.f16 s10, s8
|
||||
; CHECK-NEXT: vseleq.f16 s8, s8, s10
|
||||
; CHECK-NEXT: vabs.f16 s10, s1
|
||||
; CHECK-NEXT: tst.w r0, #128
|
||||
; CHECK-NEXT: vneg.f16 s12, s10
|
||||
; CHECK-NEXT: cset r0, ne
|
||||
; CHECK-NEXT: lsls r0, r0, #31
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: ldrb.w r0, [sp, #9]
|
||||
; CHECK-NEXT: vseleq.f16 s5, s10, s12
|
||||
; CHECK-NEXT: tst.w r0, #128
|
||||
; CHECK-NEXT: vins.f16 s5, s8
|
||||
; CHECK-NEXT: vmovx.f16 s8, s2
|
||||
; CHECK-NEXT: tst.w r0, #128
|
||||
; CHECK-NEXT: vabs.f16 s8, s8
|
||||
; CHECK-NEXT: cset r0, ne
|
||||
; CHECK-NEXT: vneg.f16 s10, s8
|
||||
; CHECK-NEXT: lsls r0, r0, #31
|
||||
; CHECK-NEXT: vabs.f16 s8, s8
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: ldrb.w r0, [sp, #13]
|
||||
; CHECK-NEXT: vneg.f16 s10, s8
|
||||
; CHECK-NEXT: vseleq.f16 s8, s8, s10
|
||||
; CHECK-NEXT: vabs.f16 s10, s2
|
||||
; CHECK-NEXT: vneg.f16 s2, s0
|
||||
; CHECK-NEXT: tst.w r0, #128
|
||||
; CHECK-NEXT: vneg.f16 s12, s10
|
||||
; CHECK-NEXT: cset r0, ne
|
||||
; CHECK-NEXT: lsls r0, r0, #31
|
||||
; CHECK-NEXT: vneg.f16 s2, s0
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: ldrb.w r0, [sp, #1]
|
||||
; CHECK-NEXT: vseleq.f16 s6, s10, s12
|
||||
; CHECK-NEXT: tst.w r0, #128
|
||||
; CHECK-NEXT: vins.f16 s6, s8
|
||||
; CHECK-NEXT: vmovx.f16 s8, s3
|
||||
; CHECK-NEXT: tst.w r0, #128
|
||||
; CHECK-NEXT: vabs.f16 s8, s8
|
||||
; CHECK-NEXT: cset r0, ne
|
||||
; CHECK-NEXT: vneg.f16 s10, s8
|
||||
; CHECK-NEXT: lsls r0, r0, #31
|
||||
; CHECK-NEXT: vabs.f16 s8, s8
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: ldrb.w r0, [sp, #5]
|
||||
; CHECK-NEXT: vneg.f16 s10, s8
|
||||
; CHECK-NEXT: vseleq.f16 s8, s8, s10
|
||||
; CHECK-NEXT: tst.w r0, #128
|
||||
; CHECK-NEXT: cset r0, ne
|
||||
; CHECK-NEXT: lsls r0, r0, #31
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: vseleq.f16 s7, s0, s2
|
||||
; CHECK-NEXT: vins.f16 s7, s8
|
||||
; CHECK-NEXT: vmov q0, q1
|
||||
|
||||
@ -1012,11 +1012,11 @@ define arm_aapcs_vfpcc <4 x i32> @ext_ops_trunc_i32(<4 x i32> %a, <4 x i32> %b)
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: cset r0, eq
|
||||
; CHECK-NEXT: mul r1, r8, r1
|
||||
; CHECK-NEXT: tst.w r0, #1
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: csetm r0, ne
|
||||
; CHECK-NEXT: cmp r4, #0
|
||||
; CHECK-NEXT: cset r4, eq
|
||||
; CHECK-NEXT: tst.w r4, #1
|
||||
; CHECK-NEXT: cmp r4, #0
|
||||
; CHECK-NEXT: csetm r4, ne
|
||||
; CHECK-NEXT: vmov.32 q4[1], r4
|
||||
; CHECK-NEXT: vmov q4[2], q4[0], r4, r0
|
||||
@ -1026,12 +1026,12 @@ define arm_aapcs_vfpcc <4 x i32> @ext_ops_trunc_i32(<4 x i32> %a, <4 x i32> %b)
|
||||
; CHECK-NEXT: orr.w r1, r1, r9, asr #31
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: cset r1, eq
|
||||
; CHECK-NEXT: tst.w r1, #1
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: csetm r1, ne
|
||||
; CHECK-NEXT: cmp r7, #0
|
||||
; CHECK-NEXT: cset r7, eq
|
||||
; CHECK-NEXT: vmov.32 q0[1], r1
|
||||
; CHECK-NEXT: tst.w r7, #1
|
||||
; CHECK-NEXT: cmp r7, #0
|
||||
; CHECK-NEXT: csetm r7, ne
|
||||
; CHECK-NEXT: vmov q0[2], q0[0], r1, r7
|
||||
; CHECK-NEXT: mla r7, r3, r5, r0
|
||||
|
||||
@ -1232,8 +1232,6 @@ define arm_aapcs_vfpcc void @masked_v4f16_align4(<4 x half> *%dest, <4 x float>
|
||||
; CHECK-LE-NEXT: vcmp.f32 s1, #0
|
||||
; CHECK-LE-NEXT: cset r1, ne
|
||||
; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-LE-NEXT: and r1, r1, #1
|
||||
; CHECK-LE-NEXT: vcmp.f32 s2, #0
|
||||
; CHECK-LE-NEXT: rsb.w r3, r1, #0
|
||||
; CHECK-LE-NEXT: mov.w r1, #0
|
||||
; CHECK-LE-NEXT: bfi r1, r3, #0, #1
|
||||
@ -1242,24 +1240,22 @@ define arm_aapcs_vfpcc void @masked_v4f16_align4(<4 x half> *%dest, <4 x float>
|
||||
; CHECK-LE-NEXT: movgt r3, #1
|
||||
; CHECK-LE-NEXT: cmp r3, #0
|
||||
; CHECK-LE-NEXT: cset r3, ne
|
||||
; CHECK-LE-NEXT: vcmp.f32 s2, #0
|
||||
; CHECK-LE-NEXT: rsbs r3, r3, #0
|
||||
; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-LE-NEXT: and r3, r3, #1
|
||||
; CHECK-LE-NEXT: vcmp.f32 s3, #0
|
||||
; CHECK-LE-NEXT: rsb.w r3, r3, #0
|
||||
; CHECK-LE-NEXT: mov.w r2, #0
|
||||
; CHECK-LE-NEXT: bfi r1, r3, #1, #1
|
||||
; CHECK-LE-NEXT: mov.w r3, #0
|
||||
; CHECK-LE-NEXT: it gt
|
||||
; CHECK-LE-NEXT: movgt r3, #1
|
||||
; CHECK-LE-NEXT: cmp r3, #0
|
||||
; CHECK-LE-NEXT: vcmp.f32 s3, #0
|
||||
; CHECK-LE-NEXT: cset r3, ne
|
||||
; CHECK-LE-NEXT: movs r2, #0
|
||||
; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-LE-NEXT: it gt
|
||||
; CHECK-LE-NEXT: movgt r2, #1
|
||||
; CHECK-LE-NEXT: cmp r2, #0
|
||||
; CHECK-LE-NEXT: and r3, r3, #1
|
||||
; CHECK-LE-NEXT: cset r2, ne
|
||||
; CHECK-LE-NEXT: and r2, r2, #1
|
||||
; CHECK-LE-NEXT: rsbs r3, r3, #0
|
||||
; CHECK-LE-NEXT: vcvtb.f16.f32 s4, s0
|
||||
; CHECK-LE-NEXT: bfi r1, r3, #2, #1
|
||||
@ -1316,8 +1312,6 @@ define arm_aapcs_vfpcc void @masked_v4f16_align4(<4 x half> *%dest, <4 x float>
|
||||
; CHECK-BE-NEXT: vcmp.f32 s6, #0
|
||||
; CHECK-BE-NEXT: cset r1, ne
|
||||
; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-BE-NEXT: and r1, r1, #1
|
||||
; CHECK-BE-NEXT: vcmp.f32 s5, #0
|
||||
; CHECK-BE-NEXT: rsb.w r3, r1, #0
|
||||
; CHECK-BE-NEXT: mov.w r1, #0
|
||||
; CHECK-BE-NEXT: bfi r1, r3, #0, #1
|
||||
@ -1326,25 +1320,23 @@ define arm_aapcs_vfpcc void @masked_v4f16_align4(<4 x half> *%dest, <4 x float>
|
||||
; CHECK-BE-NEXT: movgt r3, #1
|
||||
; CHECK-BE-NEXT: cmp r3, #0
|
||||
; CHECK-BE-NEXT: cset r3, ne
|
||||
; CHECK-BE-NEXT: vcmp.f32 s5, #0
|
||||
; CHECK-BE-NEXT: rsbs r3, r3, #0
|
||||
; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-BE-NEXT: and r3, r3, #1
|
||||
; CHECK-BE-NEXT: vcmp.f32 s4, #0
|
||||
; CHECK-BE-NEXT: rsb.w r3, r3, #0
|
||||
; CHECK-BE-NEXT: vcvtb.f16.f32 s0, s4
|
||||
; CHECK-BE-NEXT: bfi r1, r3, #1, #1
|
||||
; CHECK-BE-NEXT: mov.w r3, #0
|
||||
; CHECK-BE-NEXT: it gt
|
||||
; CHECK-BE-NEXT: movgt r3, #1
|
||||
; CHECK-BE-NEXT: cmp r3, #0
|
||||
; CHECK-BE-NEXT: vcmp.f32 s4, #0
|
||||
; CHECK-BE-NEXT: cset r3, ne
|
||||
; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-BE-NEXT: it gt
|
||||
; CHECK-BE-NEXT: movgt r2, #1
|
||||
; CHECK-BE-NEXT: cmp r2, #0
|
||||
; CHECK-BE-NEXT: and r3, r3, #1
|
||||
; CHECK-BE-NEXT: rsb.w r3, r3, #0
|
||||
; CHECK-BE-NEXT: cset r2, ne
|
||||
; CHECK-BE-NEXT: and r2, r2, #1
|
||||
; CHECK-BE-NEXT: rsbs r3, r3, #0
|
||||
; CHECK-BE-NEXT: vcvtb.f16.f32 s0, s4
|
||||
; CHECK-BE-NEXT: bfi r1, r3, #2, #1
|
||||
; CHECK-BE-NEXT: rsbs r2, r2, #0
|
||||
; CHECK-BE-NEXT: vcvtt.f16.f32 s0, s5
|
||||
@ -1404,8 +1396,6 @@ define arm_aapcs_vfpcc void @masked_v4f16_align2(<4 x half> *%dest, <4 x float>
|
||||
; CHECK-LE-NEXT: vcmp.f32 s1, #0
|
||||
; CHECK-LE-NEXT: cset r1, ne
|
||||
; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-LE-NEXT: and r1, r1, #1
|
||||
; CHECK-LE-NEXT: vcmp.f32 s2, #0
|
||||
; CHECK-LE-NEXT: rsb.w r3, r1, #0
|
||||
; CHECK-LE-NEXT: mov.w r1, #0
|
||||
; CHECK-LE-NEXT: bfi r1, r3, #0, #1
|
||||
@ -1414,24 +1404,22 @@ define arm_aapcs_vfpcc void @masked_v4f16_align2(<4 x half> *%dest, <4 x float>
|
||||
; CHECK-LE-NEXT: movgt r3, #1
|
||||
; CHECK-LE-NEXT: cmp r3, #0
|
||||
; CHECK-LE-NEXT: cset r3, ne
|
||||
; CHECK-LE-NEXT: vcmp.f32 s2, #0
|
||||
; CHECK-LE-NEXT: rsbs r3, r3, #0
|
||||
; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-LE-NEXT: and r3, r3, #1
|
||||
; CHECK-LE-NEXT: vcmp.f32 s3, #0
|
||||
; CHECK-LE-NEXT: rsb.w r3, r3, #0
|
||||
; CHECK-LE-NEXT: mov.w r2, #0
|
||||
; CHECK-LE-NEXT: bfi r1, r3, #1, #1
|
||||
; CHECK-LE-NEXT: mov.w r3, #0
|
||||
; CHECK-LE-NEXT: it gt
|
||||
; CHECK-LE-NEXT: movgt r3, #1
|
||||
; CHECK-LE-NEXT: cmp r3, #0
|
||||
; CHECK-LE-NEXT: vcmp.f32 s3, #0
|
||||
; CHECK-LE-NEXT: cset r3, ne
|
||||
; CHECK-LE-NEXT: movs r2, #0
|
||||
; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-LE-NEXT: it gt
|
||||
; CHECK-LE-NEXT: movgt r2, #1
|
||||
; CHECK-LE-NEXT: cmp r2, #0
|
||||
; CHECK-LE-NEXT: and r3, r3, #1
|
||||
; CHECK-LE-NEXT: cset r2, ne
|
||||
; CHECK-LE-NEXT: and r2, r2, #1
|
||||
; CHECK-LE-NEXT: rsbs r3, r3, #0
|
||||
; CHECK-LE-NEXT: vcvtb.f16.f32 s4, s0
|
||||
; CHECK-LE-NEXT: bfi r1, r3, #2, #1
|
||||
@ -1488,8 +1476,6 @@ define arm_aapcs_vfpcc void @masked_v4f16_align2(<4 x half> *%dest, <4 x float>
|
||||
; CHECK-BE-NEXT: vcmp.f32 s6, #0
|
||||
; CHECK-BE-NEXT: cset r1, ne
|
||||
; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-BE-NEXT: and r1, r1, #1
|
||||
; CHECK-BE-NEXT: vcmp.f32 s5, #0
|
||||
; CHECK-BE-NEXT: rsb.w r3, r1, #0
|
||||
; CHECK-BE-NEXT: mov.w r1, #0
|
||||
; CHECK-BE-NEXT: bfi r1, r3, #0, #1
|
||||
@ -1498,25 +1484,23 @@ define arm_aapcs_vfpcc void @masked_v4f16_align2(<4 x half> *%dest, <4 x float>
|
||||
; CHECK-BE-NEXT: movgt r3, #1
|
||||
; CHECK-BE-NEXT: cmp r3, #0
|
||||
; CHECK-BE-NEXT: cset r3, ne
|
||||
; CHECK-BE-NEXT: vcmp.f32 s5, #0
|
||||
; CHECK-BE-NEXT: rsbs r3, r3, #0
|
||||
; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-BE-NEXT: and r3, r3, #1
|
||||
; CHECK-BE-NEXT: vcmp.f32 s4, #0
|
||||
; CHECK-BE-NEXT: rsb.w r3, r3, #0
|
||||
; CHECK-BE-NEXT: vcvtb.f16.f32 s0, s4
|
||||
; CHECK-BE-NEXT: bfi r1, r3, #1, #1
|
||||
; CHECK-BE-NEXT: mov.w r3, #0
|
||||
; CHECK-BE-NEXT: it gt
|
||||
; CHECK-BE-NEXT: movgt r3, #1
|
||||
; CHECK-BE-NEXT: cmp r3, #0
|
||||
; CHECK-BE-NEXT: vcmp.f32 s4, #0
|
||||
; CHECK-BE-NEXT: cset r3, ne
|
||||
; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-BE-NEXT: it gt
|
||||
; CHECK-BE-NEXT: movgt r2, #1
|
||||
; CHECK-BE-NEXT: cmp r2, #0
|
||||
; CHECK-BE-NEXT: and r3, r3, #1
|
||||
; CHECK-BE-NEXT: rsb.w r3, r3, #0
|
||||
; CHECK-BE-NEXT: cset r2, ne
|
||||
; CHECK-BE-NEXT: and r2, r2, #1
|
||||
; CHECK-BE-NEXT: rsbs r3, r3, #0
|
||||
; CHECK-BE-NEXT: vcvtb.f16.f32 s0, s4
|
||||
; CHECK-BE-NEXT: bfi r1, r3, #2, #1
|
||||
; CHECK-BE-NEXT: rsbs r2, r2, #0
|
||||
; CHECK-BE-NEXT: vcvtt.f16.f32 s0, s5
|
||||
@ -1576,8 +1560,6 @@ define arm_aapcs_vfpcc void @masked_v4f16_align1(<4 x half> *%dest, <4 x float>
|
||||
; CHECK-LE-NEXT: vcmp.f32 s1, #0
|
||||
; CHECK-LE-NEXT: cset r1, ne
|
||||
; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-LE-NEXT: and r1, r1, #1
|
||||
; CHECK-LE-NEXT: vcmp.f32 s2, #0
|
||||
; CHECK-LE-NEXT: rsb.w r3, r1, #0
|
||||
; CHECK-LE-NEXT: mov.w r1, #0
|
||||
; CHECK-LE-NEXT: bfi r1, r3, #0, #1
|
||||
@ -1586,24 +1568,22 @@ define arm_aapcs_vfpcc void @masked_v4f16_align1(<4 x half> *%dest, <4 x float>
|
||||
; CHECK-LE-NEXT: movgt r3, #1
|
||||
; CHECK-LE-NEXT: cmp r3, #0
|
||||
; CHECK-LE-NEXT: cset r3, ne
|
||||
; CHECK-LE-NEXT: vcmp.f32 s2, #0
|
||||
; CHECK-LE-NEXT: rsbs r3, r3, #0
|
||||
; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-LE-NEXT: and r3, r3, #1
|
||||
; CHECK-LE-NEXT: vcmp.f32 s3, #0
|
||||
; CHECK-LE-NEXT: rsb.w r3, r3, #0
|
||||
; CHECK-LE-NEXT: mov.w r2, #0
|
||||
; CHECK-LE-NEXT: bfi r1, r3, #1, #1
|
||||
; CHECK-LE-NEXT: mov.w r3, #0
|
||||
; CHECK-LE-NEXT: it gt
|
||||
; CHECK-LE-NEXT: movgt r3, #1
|
||||
; CHECK-LE-NEXT: cmp r3, #0
|
||||
; CHECK-LE-NEXT: vcmp.f32 s3, #0
|
||||
; CHECK-LE-NEXT: cset r3, ne
|
||||
; CHECK-LE-NEXT: movs r2, #0
|
||||
; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-LE-NEXT: it gt
|
||||
; CHECK-LE-NEXT: movgt r2, #1
|
||||
; CHECK-LE-NEXT: cmp r2, #0
|
||||
; CHECK-LE-NEXT: and r3, r3, #1
|
||||
; CHECK-LE-NEXT: cset r2, ne
|
||||
; CHECK-LE-NEXT: and r2, r2, #1
|
||||
; CHECK-LE-NEXT: rsbs r3, r3, #0
|
||||
; CHECK-LE-NEXT: vcvtb.f16.f32 s4, s0
|
||||
; CHECK-LE-NEXT: bfi r1, r3, #2, #1
|
||||
@ -1668,8 +1648,6 @@ define arm_aapcs_vfpcc void @masked_v4f16_align1(<4 x half> *%dest, <4 x float>
|
||||
; CHECK-BE-NEXT: vcmp.f32 s6, #0
|
||||
; CHECK-BE-NEXT: cset r1, ne
|
||||
; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-BE-NEXT: and r1, r1, #1
|
||||
; CHECK-BE-NEXT: vcmp.f32 s5, #0
|
||||
; CHECK-BE-NEXT: rsb.w r3, r1, #0
|
||||
; CHECK-BE-NEXT: mov.w r1, #0
|
||||
; CHECK-BE-NEXT: bfi r1, r3, #0, #1
|
||||
@ -1678,25 +1656,23 @@ define arm_aapcs_vfpcc void @masked_v4f16_align1(<4 x half> *%dest, <4 x float>
|
||||
; CHECK-BE-NEXT: movgt r3, #1
|
||||
; CHECK-BE-NEXT: cmp r3, #0
|
||||
; CHECK-BE-NEXT: cset r3, ne
|
||||
; CHECK-BE-NEXT: vcmp.f32 s5, #0
|
||||
; CHECK-BE-NEXT: rsbs r3, r3, #0
|
||||
; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-BE-NEXT: and r3, r3, #1
|
||||
; CHECK-BE-NEXT: vcmp.f32 s4, #0
|
||||
; CHECK-BE-NEXT: rsb.w r3, r3, #0
|
||||
; CHECK-BE-NEXT: vcvtb.f16.f32 s0, s4
|
||||
; CHECK-BE-NEXT: bfi r1, r3, #1, #1
|
||||
; CHECK-BE-NEXT: mov.w r3, #0
|
||||
; CHECK-BE-NEXT: it gt
|
||||
; CHECK-BE-NEXT: movgt r3, #1
|
||||
; CHECK-BE-NEXT: cmp r3, #0
|
||||
; CHECK-BE-NEXT: vcmp.f32 s4, #0
|
||||
; CHECK-BE-NEXT: cset r3, ne
|
||||
; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-BE-NEXT: it gt
|
||||
; CHECK-BE-NEXT: movgt r2, #1
|
||||
; CHECK-BE-NEXT: cmp r2, #0
|
||||
; CHECK-BE-NEXT: and r3, r3, #1
|
||||
; CHECK-BE-NEXT: rsb.w r3, r3, #0
|
||||
; CHECK-BE-NEXT: cset r2, ne
|
||||
; CHECK-BE-NEXT: and r2, r2, #1
|
||||
; CHECK-BE-NEXT: rsbs r3, r3, #0
|
||||
; CHECK-BE-NEXT: vcvtb.f16.f32 s0, s4
|
||||
; CHECK-BE-NEXT: bfi r1, r3, #2, #1
|
||||
; CHECK-BE-NEXT: rsbs r2, r2, #0
|
||||
; CHECK-BE-NEXT: vcvtt.f16.f32 s0, s5
|
||||
|
||||
@ -20,11 +20,9 @@ define void @tailpred(half* nocapture readonly %pSrcA, half* nocapture readonly
|
||||
; CHECK-NEXT: cset r4, hi
|
||||
; CHECK-NEXT: cmp r5, r2
|
||||
; CHECK-NEXT: cset r5, hi
|
||||
; CHECK-NEXT: ands r4, r5
|
||||
; CHECK-NEXT: lsls r4, r4, #31
|
||||
; CHECK-NEXT: itt eq
|
||||
; CHECK-NEXT: andeq.w r5, lr, r12
|
||||
; CHECK-NEXT: lslseq.w r5, r5, #31
|
||||
; CHECK-NEXT: tst r5, r4
|
||||
; CHECK-NEXT: it eq
|
||||
; CHECK-NEXT: andseq.w r5, lr, r12
|
||||
; CHECK-NEXT: beq .LBB0_4
|
||||
; CHECK-NEXT: @ %bb.2: @ %while.body.preheader
|
||||
; CHECK-NEXT: dls lr, r3
|
||||
@ -130,11 +128,9 @@ define void @notailpred(half* nocapture readonly %pSrcA, half* nocapture readonl
|
||||
; CHECK-NEXT: cset r5, hi
|
||||
; CHECK-NEXT: cmp r4, r2
|
||||
; CHECK-NEXT: cset r4, hi
|
||||
; CHECK-NEXT: ands r5, r4
|
||||
; CHECK-NEXT: lsls r5, r5, #31
|
||||
; CHECK-NEXT: itt eq
|
||||
; CHECK-NEXT: andeq r7, r6
|
||||
; CHECK-NEXT: lslseq.w r7, r7, #31
|
||||
; CHECK-NEXT: tst r4, r5
|
||||
; CHECK-NEXT: it eq
|
||||
; CHECK-NEXT: andseq.w r7, r7, r6
|
||||
; CHECK-NEXT: beq .LBB1_7
|
||||
; CHECK-NEXT: .LBB1_3:
|
||||
; CHECK-NEXT: mov r5, r3
|
||||
|
||||
@ -581,11 +581,11 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeqz_v2i1(<2 x i64> %a, <2 x i64> %b) {
|
||||
; CHECK-NEXT: orrs r0, r1
|
||||
; CHECK-NEXT: vmov r1, s9
|
||||
; CHECK-NEXT: cset r0, eq
|
||||
; CHECK-NEXT: tst.w r0, #1
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: csetm r0, ne
|
||||
; CHECK-NEXT: orrs r1, r2
|
||||
; CHECK-NEXT: cset r1, eq
|
||||
; CHECK-NEXT: tst.w r1, #1
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: csetm r1, ne
|
||||
; CHECK-NEXT: vmov q2[2], q2[0], r1, r0
|
||||
; CHECK-NEXT: vmov q2[3], q2[1], r1, r0
|
||||
@ -615,7 +615,7 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeq_v2i1(<2 x i64> %a, <2 x i64> %b, <2 x i6
|
||||
; CHECK-NEXT: orrs r0, r1
|
||||
; CHECK-NEXT: vmov r1, s9
|
||||
; CHECK-NEXT: cset r0, eq
|
||||
; CHECK-NEXT: tst.w r0, #1
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: csetm r0, ne
|
||||
; CHECK-NEXT: eors r1, r2
|
||||
; CHECK-NEXT: vmov r2, s8
|
||||
@ -623,7 +623,7 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeq_v2i1(<2 x i64> %a, <2 x i64> %b, <2 x i6
|
||||
; CHECK-NEXT: orrs r1, r2
|
||||
; CHECK-NEXT: vmov r2, s0
|
||||
; CHECK-NEXT: cset r1, eq
|
||||
; CHECK-NEXT: tst.w r1, #1
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: csetm r1, ne
|
||||
; CHECK-NEXT: vmov q2[2], q2[0], r1, r0
|
||||
; CHECK-NEXT: vmov q2[3], q2[1], r1, r0
|
||||
@ -632,11 +632,11 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeq_v2i1(<2 x i64> %a, <2 x i64> %b, <2 x i6
|
||||
; CHECK-NEXT: orrs r0, r1
|
||||
; CHECK-NEXT: vmov r1, s1
|
||||
; CHECK-NEXT: cset r0, eq
|
||||
; CHECK-NEXT: tst.w r0, #1
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: csetm r0, ne
|
||||
; CHECK-NEXT: orrs r1, r2
|
||||
; CHECK-NEXT: cset r1, eq
|
||||
; CHECK-NEXT: tst.w r1, #1
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: csetm r1, ne
|
||||
; CHECK-NEXT: vmov q3[2], q3[0], r1, r0
|
||||
; CHECK-NEXT: vmov q3[3], q3[1], r1, r0
|
||||
@ -663,7 +663,7 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeqr_v2i1(<2 x i64> %a, <2 x i64> %b, i64 %c
|
||||
; CHECK-NEXT: orrs r2, r3
|
||||
; CHECK-NEXT: vmov r3, s5
|
||||
; CHECK-NEXT: cset r2, eq
|
||||
; CHECK-NEXT: tst.w r2, #1
|
||||
; CHECK-NEXT: cmp r2, #0
|
||||
; CHECK-NEXT: csetm r2, ne
|
||||
; CHECK-NEXT: eors r1, r3
|
||||
; CHECK-NEXT: vmov r3, s4
|
||||
@ -671,7 +671,7 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeqr_v2i1(<2 x i64> %a, <2 x i64> %b, i64 %c
|
||||
; CHECK-NEXT: orrs r0, r1
|
||||
; CHECK-NEXT: vmov r1, s2
|
||||
; CHECK-NEXT: cset r0, eq
|
||||
; CHECK-NEXT: tst.w r0, #1
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: csetm r0, ne
|
||||
; CHECK-NEXT: vmov q2[2], q2[0], r0, r2
|
||||
; CHECK-NEXT: vmov q2[3], q2[1], r0, r2
|
||||
@ -680,11 +680,11 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeqr_v2i1(<2 x i64> %a, <2 x i64> %b, i64 %c
|
||||
; CHECK-NEXT: orrs r0, r1
|
||||
; CHECK-NEXT: vmov r1, s1
|
||||
; CHECK-NEXT: cset r0, eq
|
||||
; CHECK-NEXT: tst.w r0, #1
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: csetm r0, ne
|
||||
; CHECK-NEXT: orrs r1, r2
|
||||
; CHECK-NEXT: cset r1, eq
|
||||
; CHECK-NEXT: tst.w r1, #1
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: csetm r1, ne
|
||||
; CHECK-NEXT: vmov q3[2], q3[0], r1, r0
|
||||
; CHECK-NEXT: vmov q3[3], q3[1], r1, r0
|
||||
|
||||
@ -397,7 +397,7 @@ define arm_aapcs_vfpcc i2 @bitcast_from_v2i1(<2 x i64> %a) {
|
||||
; CHECK-LE-NEXT: cset r0, eq
|
||||
; CHECK-LE-NEXT: orrs r1, r2
|
||||
; CHECK-LE-NEXT: cset r1, eq
|
||||
; CHECK-LE-NEXT: ands r1, r1, #1
|
||||
; CHECK-LE-NEXT: cmp r1, #0
|
||||
; CHECK-LE-NEXT: it ne
|
||||
; CHECK-LE-NEXT: mvnne r1, #1
|
||||
; CHECK-LE-NEXT: bfi r1, r0, #0, #1
|
||||
@ -418,7 +418,7 @@ define arm_aapcs_vfpcc i2 @bitcast_from_v2i1(<2 x i64> %a) {
|
||||
; CHECK-BE-NEXT: cset r0, eq
|
||||
; CHECK-BE-NEXT: orrs r1, r2
|
||||
; CHECK-BE-NEXT: cset r1, eq
|
||||
; CHECK-BE-NEXT: ands r1, r1, #1
|
||||
; CHECK-BE-NEXT: cmp r1, #0
|
||||
; CHECK-BE-NEXT: it ne
|
||||
; CHECK-BE-NEXT: mvnne r1, #1
|
||||
; CHECK-BE-NEXT: bfi r1, r0, #0, #1
|
||||
|
||||
@ -8,7 +8,6 @@ define arm_aapcs_vfpcc <4 x i32> @build_var0_v4i1(i32 %s, i32 %t, <4 x i32> %a,
|
||||
; CHECK-NEXT: cmp r0, r1
|
||||
; CHECK-NEXT: mov.w r1, #0
|
||||
; CHECK-NEXT: cset r0, lo
|
||||
; CHECK-NEXT: and r0, r0, #1
|
||||
; CHECK-NEXT: rsbs r0, r0, #0
|
||||
; CHECK-NEXT: bfi r1, r0, #0, #4
|
||||
; CHECK-NEXT: vmsr p0, r1
|
||||
@ -27,7 +26,6 @@ define arm_aapcs_vfpcc <4 x i32> @build_var3_v4i1(i32 %s, i32 %t, <4 x i32> %a,
|
||||
; CHECK-NEXT: cmp r0, r1
|
||||
; CHECK-NEXT: mov.w r1, #0
|
||||
; CHECK-NEXT: cset r0, lo
|
||||
; CHECK-NEXT: and r0, r0, #1
|
||||
; CHECK-NEXT: rsbs r0, r0, #0
|
||||
; CHECK-NEXT: bfi r1, r0, #12, #4
|
||||
; CHECK-NEXT: vmsr p0, r1
|
||||
@ -45,7 +43,6 @@ define arm_aapcs_vfpcc <4 x i32> @build_varN_v4i1(i32 %s, i32 %t, <4 x i32> %a,
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: cmp r0, r1
|
||||
; CHECK-NEXT: cset r0, lo
|
||||
; CHECK-NEXT: and r0, r0, #1
|
||||
; CHECK-NEXT: rsbs r0, r0, #0
|
||||
; CHECK-NEXT: vmsr p0, r0
|
||||
; CHECK-NEXT: vpsel q0, q0, q1
|
||||
@ -65,7 +62,6 @@ define arm_aapcs_vfpcc <8 x i16> @build_var0_v8i1(i32 %s, i32 %t, <8 x i16> %a,
|
||||
; CHECK-NEXT: cmp r0, r1
|
||||
; CHECK-NEXT: mov.w r1, #0
|
||||
; CHECK-NEXT: cset r0, lo
|
||||
; CHECK-NEXT: and r0, r0, #1
|
||||
; CHECK-NEXT: rsbs r0, r0, #0
|
||||
; CHECK-NEXT: bfi r1, r0, #0, #2
|
||||
; CHECK-NEXT: vmsr p0, r1
|
||||
@ -84,7 +80,6 @@ define arm_aapcs_vfpcc <8 x i16> @build_var3_v8i1(i32 %s, i32 %t, <8 x i16> %a,
|
||||
; CHECK-NEXT: cmp r0, r1
|
||||
; CHECK-NEXT: mov.w r1, #0
|
||||
; CHECK-NEXT: cset r0, lo
|
||||
; CHECK-NEXT: and r0, r0, #1
|
||||
; CHECK-NEXT: rsbs r0, r0, #0
|
||||
; CHECK-NEXT: bfi r1, r0, #6, #2
|
||||
; CHECK-NEXT: vmsr p0, r1
|
||||
@ -102,7 +97,6 @@ define arm_aapcs_vfpcc <8 x i16> @build_varN_v8i1(i32 %s, i32 %t, <8 x i16> %a,
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: cmp r0, r1
|
||||
; CHECK-NEXT: cset r0, lo
|
||||
; CHECK-NEXT: and r0, r0, #1
|
||||
; CHECK-NEXT: rsbs r0, r0, #0
|
||||
; CHECK-NEXT: vmsr p0, r0
|
||||
; CHECK-NEXT: vpsel q0, q0, q1
|
||||
@ -122,7 +116,6 @@ define arm_aapcs_vfpcc <16 x i8> @build_var0_v16i1(i32 %s, i32 %t, <16 x i8> %a,
|
||||
; CHECK-NEXT: cmp r0, r1
|
||||
; CHECK-NEXT: mov.w r1, #0
|
||||
; CHECK-NEXT: cset r0, lo
|
||||
; CHECK-NEXT: and r0, r0, #1
|
||||
; CHECK-NEXT: rsbs r0, r0, #0
|
||||
; CHECK-NEXT: bfi r1, r0, #0, #1
|
||||
; CHECK-NEXT: vmsr p0, r1
|
||||
@ -141,7 +134,6 @@ define arm_aapcs_vfpcc <16 x i8> @build_var3_v16i1(i32 %s, i32 %t, <16 x i8> %a,
|
||||
; CHECK-NEXT: cmp r0, r1
|
||||
; CHECK-NEXT: mov.w r1, #0
|
||||
; CHECK-NEXT: cset r0, lo
|
||||
; CHECK-NEXT: and r0, r0, #1
|
||||
; CHECK-NEXT: rsbs r0, r0, #0
|
||||
; CHECK-NEXT: bfi r1, r0, #3, #1
|
||||
; CHECK-NEXT: vmsr p0, r1
|
||||
@ -159,7 +151,6 @@ define arm_aapcs_vfpcc <16 x i8> @build_varN_v16i1(i32 %s, i32 %t, <16 x i8> %a,
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: cmp r0, r1
|
||||
; CHECK-NEXT: cset r0, lo
|
||||
; CHECK-NEXT: and r0, r0, #1
|
||||
; CHECK-NEXT: rsbs r0, r0, #0
|
||||
; CHECK-NEXT: vmsr p0, r0
|
||||
; CHECK-NEXT: vpsel q0, q0, q1
|
||||
@ -178,7 +169,6 @@ define arm_aapcs_vfpcc <2 x i64> @build_var0_v2i1(i32 %s, i32 %t, <2 x i64> %a,
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: cmp r0, r1
|
||||
; CHECK-NEXT: cset r0, lo
|
||||
; CHECK-NEXT: and r0, r0, #1
|
||||
; CHECK-NEXT: rsbs r0, r0, #0
|
||||
; CHECK-NEXT: vmov s8, r0
|
||||
; CHECK-NEXT: vldr s10, .LCPI9_0
|
||||
@ -204,7 +194,6 @@ define arm_aapcs_vfpcc <2 x i64> @build_var1_v2i1(i32 %s, i32 %t, <2 x i64> %a,
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: cmp r0, r1
|
||||
; CHECK-NEXT: cset r0, lo
|
||||
; CHECK-NEXT: and r0, r0, #1
|
||||
; CHECK-NEXT: rsbs r0, r0, #0
|
||||
; CHECK-NEXT: vmov s10, r0
|
||||
; CHECK-NEXT: vldr s8, .LCPI10_0
|
||||
@ -230,7 +219,6 @@ define arm_aapcs_vfpcc <2 x i64> @build_varN_v2i1(i32 %s, i32 %t, <2 x i64> %a,
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: cmp r0, r1
|
||||
; CHECK-NEXT: cset r0, lo
|
||||
; CHECK-NEXT: and r0, r0, #1
|
||||
; CHECK-NEXT: rsbs r0, r0, #0
|
||||
; CHECK-NEXT: vdup.32 q2, r0
|
||||
; CHECK-NEXT: vbic q1, q1, q2
|
||||
|
||||
@ -326,7 +326,7 @@ define arm_aapcs_vfpcc void @store_v2i1(<2 x i1> *%dst, <2 x i64> %a) {
|
||||
; CHECK-LE-NEXT: cset r1, eq
|
||||
; CHECK-LE-NEXT: orrs r2, r3
|
||||
; CHECK-LE-NEXT: cset r2, eq
|
||||
; CHECK-LE-NEXT: ands r2, r2, #1
|
||||
; CHECK-LE-NEXT: cmp r2, #0
|
||||
; CHECK-LE-NEXT: it ne
|
||||
; CHECK-LE-NEXT: mvnne r2, #1
|
||||
; CHECK-LE-NEXT: bfi r2, r1, #0, #1
|
||||
@ -345,7 +345,7 @@ define arm_aapcs_vfpcc void @store_v2i1(<2 x i1> *%dst, <2 x i64> %a) {
|
||||
; CHECK-BE-NEXT: cset r1, eq
|
||||
; CHECK-BE-NEXT: orrs r2, r3
|
||||
; CHECK-BE-NEXT: cset r2, eq
|
||||
; CHECK-BE-NEXT: ands r2, r2, #1
|
||||
; CHECK-BE-NEXT: cmp r2, #0
|
||||
; CHECK-BE-NEXT: it ne
|
||||
; CHECK-BE-NEXT: mvnne r2, #1
|
||||
; CHECK-BE-NEXT: bfi r2, r1, #0, #1
|
||||
|
||||
@ -329,11 +329,11 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeqz_v2i1(<2 x i64> %a, <2 x i64> %b) {
|
||||
; CHECK-NEXT: orrs r0, r1
|
||||
; CHECK-NEXT: vmov r1, s1
|
||||
; CHECK-NEXT: cset r0, eq
|
||||
; CHECK-NEXT: tst.w r0, #1
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: csetm r0, ne
|
||||
; CHECK-NEXT: orrs r1, r2
|
||||
; CHECK-NEXT: cset r1, eq
|
||||
; CHECK-NEXT: tst.w r1, #1
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: csetm r1, ne
|
||||
; CHECK-NEXT: vmov q2[2], q2[0], r1, r0
|
||||
; CHECK-NEXT: vmov q2[3], q2[1], r1, r0
|
||||
@ -357,11 +357,11 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeq_v2i1(<2 x i64> %a, <2 x i64> %b, <2 x i6
|
||||
; CHECK-NEXT: orrs r0, r1
|
||||
; CHECK-NEXT: vmov r1, s1
|
||||
; CHECK-NEXT: cset r0, eq
|
||||
; CHECK-NEXT: tst.w r0, #1
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: csetm r0, ne
|
||||
; CHECK-NEXT: orrs r1, r2
|
||||
; CHECK-NEXT: cset r1, eq
|
||||
; CHECK-NEXT: tst.w r1, #1
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: csetm r1, ne
|
||||
; CHECK-NEXT: vmov q2[2], q2[0], r1, r0
|
||||
; CHECK-NEXT: vmov q2[3], q2[1], r1, r0
|
||||
|
||||
@ -383,12 +383,12 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeqz_v2i1(<2 x i64> %a, <2 x i64> %b) {
|
||||
; CHECK-NEXT: orrs r0, r1
|
||||
; CHECK-NEXT: vmov r1, s5
|
||||
; CHECK-NEXT: cset r0, eq
|
||||
; CHECK-NEXT: tst.w r0, #1
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: csetm r0, ne
|
||||
; CHECK-NEXT: orrs r1, r2
|
||||
; CHECK-NEXT: vmov r2, s0
|
||||
; CHECK-NEXT: cset r1, eq
|
||||
; CHECK-NEXT: tst.w r1, #1
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: csetm r1, ne
|
||||
; CHECK-NEXT: vmov q2[2], q2[0], r1, r0
|
||||
; CHECK-NEXT: vmov q2[3], q2[1], r1, r0
|
||||
@ -397,11 +397,11 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeqz_v2i1(<2 x i64> %a, <2 x i64> %b) {
|
||||
; CHECK-NEXT: orrs r0, r1
|
||||
; CHECK-NEXT: vmov r1, s1
|
||||
; CHECK-NEXT: cset r0, eq
|
||||
; CHECK-NEXT: tst.w r0, #1
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: csetm r0, ne
|
||||
; CHECK-NEXT: orrs r1, r2
|
||||
; CHECK-NEXT: cset r1, eq
|
||||
; CHECK-NEXT: tst.w r1, #1
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: csetm r1, ne
|
||||
; CHECK-NEXT: vmov q3[2], q3[0], r1, r0
|
||||
; CHECK-NEXT: vmov q3[3], q3[1], r1, r0
|
||||
@ -432,7 +432,7 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeq_v2i1(<2 x i64> %a, <2 x i64> %b, <2 x i6
|
||||
; CHECK-NEXT: orrs r0, r1
|
||||
; CHECK-NEXT: vmov r1, s9
|
||||
; CHECK-NEXT: cset r0, eq
|
||||
; CHECK-NEXT: tst.w r0, #1
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: csetm r0, ne
|
||||
; CHECK-NEXT: eors r1, r2
|
||||
; CHECK-NEXT: vmov r2, s8
|
||||
@ -440,7 +440,7 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeq_v2i1(<2 x i64> %a, <2 x i64> %b, <2 x i6
|
||||
; CHECK-NEXT: orrs r1, r2
|
||||
; CHECK-NEXT: vmov r2, s0
|
||||
; CHECK-NEXT: cset r1, eq
|
||||
; CHECK-NEXT: tst.w r1, #1
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: csetm r1, ne
|
||||
; CHECK-NEXT: vmov q2[2], q2[0], r1, r0
|
||||
; CHECK-NEXT: vmov q2[3], q2[1], r1, r0
|
||||
@ -449,11 +449,11 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeq_v2i1(<2 x i64> %a, <2 x i64> %b, <2 x i6
|
||||
; CHECK-NEXT: orrs r0, r1
|
||||
; CHECK-NEXT: vmov r1, s1
|
||||
; CHECK-NEXT: cset r0, eq
|
||||
; CHECK-NEXT: tst.w r0, #1
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: csetm r0, ne
|
||||
; CHECK-NEXT: orrs r1, r2
|
||||
; CHECK-NEXT: cset r1, eq
|
||||
; CHECK-NEXT: tst.w r1, #1
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: csetm r1, ne
|
||||
; CHECK-NEXT: vmov q3[2], q3[0], r1, r0
|
||||
; CHECK-NEXT: vmov q3[3], q3[1], r1, r0
|
||||
|
||||
@ -78,12 +78,12 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeqz_v2i1(<2 x i64> %a, <2 x i64> %b, <2 x i
|
||||
; CHECK-NEXT: orrs r0, r1
|
||||
; CHECK-NEXT: vmov r1, s9
|
||||
; CHECK-NEXT: cset r0, eq
|
||||
; CHECK-NEXT: tst.w r0, #1
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: csetm r0, ne
|
||||
; CHECK-NEXT: orrs r1, r2
|
||||
; CHECK-NEXT: vmov r2, s4
|
||||
; CHECK-NEXT: cset r1, eq
|
||||
; CHECK-NEXT: tst.w r1, #1
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: csetm r1, ne
|
||||
; CHECK-NEXT: vmov q2[2], q2[0], r1, r0
|
||||
; CHECK-NEXT: vmov q2[3], q2[1], r1, r0
|
||||
@ -92,12 +92,12 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeqz_v2i1(<2 x i64> %a, <2 x i64> %b, <2 x i
|
||||
; CHECK-NEXT: orrs r0, r1
|
||||
; CHECK-NEXT: vmov r1, s5
|
||||
; CHECK-NEXT: cset r0, eq
|
||||
; CHECK-NEXT: tst.w r0, #1
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: csetm r0, ne
|
||||
; CHECK-NEXT: orrs r1, r2
|
||||
; CHECK-NEXT: vmov r2, s0
|
||||
; CHECK-NEXT: cset r1, eq
|
||||
; CHECK-NEXT: tst.w r1, #1
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: csetm r1, ne
|
||||
; CHECK-NEXT: vmov q3[2], q3[0], r1, r0
|
||||
; CHECK-NEXT: vmov q3[3], q3[1], r1, r0
|
||||
@ -107,11 +107,11 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeqz_v2i1(<2 x i64> %a, <2 x i64> %b, <2 x i
|
||||
; CHECK-NEXT: orrs r0, r1
|
||||
; CHECK-NEXT: vmov r1, s1
|
||||
; CHECK-NEXT: cset r0, eq
|
||||
; CHECK-NEXT: tst.w r0, #1
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: csetm r0, ne
|
||||
; CHECK-NEXT: orrs r1, r2
|
||||
; CHECK-NEXT: cset r1, eq
|
||||
; CHECK-NEXT: tst.w r1, #1
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: csetm r1, ne
|
||||
; CHECK-NEXT: vmov q4[2], q4[0], r1, r0
|
||||
; CHECK-NEXT: vmov q4[3], q4[1], r1, r0
|
||||
@ -208,12 +208,12 @@ define arm_aapcs_vfpcc <2 x i64> @cmpnez_v2i1(<2 x i64> %a, <2 x i64> %b, <2 x i
|
||||
; CHECK-NEXT: orrs r0, r1
|
||||
; CHECK-NEXT: vmov r1, s9
|
||||
; CHECK-NEXT: cset r0, ne
|
||||
; CHECK-NEXT: tst.w r0, #1
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: csetm r0, ne
|
||||
; CHECK-NEXT: orrs r1, r2
|
||||
; CHECK-NEXT: vmov r2, s4
|
||||
; CHECK-NEXT: cset r1, ne
|
||||
; CHECK-NEXT: tst.w r1, #1
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: csetm r1, ne
|
||||
; CHECK-NEXT: vmov q2[2], q2[0], r1, r0
|
||||
; CHECK-NEXT: vmov q2[3], q2[1], r1, r0
|
||||
@ -222,12 +222,12 @@ define arm_aapcs_vfpcc <2 x i64> @cmpnez_v2i1(<2 x i64> %a, <2 x i64> %b, <2 x i
|
||||
; CHECK-NEXT: orrs r0, r1
|
||||
; CHECK-NEXT: vmov r1, s5
|
||||
; CHECK-NEXT: cset r0, ne
|
||||
; CHECK-NEXT: tst.w r0, #1
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: csetm r0, ne
|
||||
; CHECK-NEXT: orrs r1, r2
|
||||
; CHECK-NEXT: vmov r2, s0
|
||||
; CHECK-NEXT: cset r1, ne
|
||||
; CHECK-NEXT: tst.w r1, #1
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: csetm r1, ne
|
||||
; CHECK-NEXT: vmov q3[2], q3[0], r1, r0
|
||||
; CHECK-NEXT: vmov q3[3], q3[1], r1, r0
|
||||
@ -237,11 +237,11 @@ define arm_aapcs_vfpcc <2 x i64> @cmpnez_v2i1(<2 x i64> %a, <2 x i64> %b, <2 x i
|
||||
; CHECK-NEXT: orrs r0, r1
|
||||
; CHECK-NEXT: vmov r1, s1
|
||||
; CHECK-NEXT: cset r0, ne
|
||||
; CHECK-NEXT: tst.w r0, #1
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: csetm r0, ne
|
||||
; CHECK-NEXT: orrs r1, r2
|
||||
; CHECK-NEXT: cset r1, ne
|
||||
; CHECK-NEXT: tst.w r1, #1
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: csetm r1, ne
|
||||
; CHECK-NEXT: vmov q4[2], q4[0], r1, r0
|
||||
; CHECK-NEXT: vmov q4[3], q4[1], r1, r0
|
||||
@ -446,24 +446,24 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeqz_v2i1_i1(<2 x i64> %a, <2 x i64> %b, i64
|
||||
; CHECK-NEXT: orrs r2, r3
|
||||
; CHECK-NEXT: vmov r3, s4
|
||||
; CHECK-NEXT: cset r2, eq
|
||||
; CHECK-NEXT: tst.w r2, #1
|
||||
; CHECK-NEXT: cmp r2, #0
|
||||
; CHECK-NEXT: vmov r2, s5
|
||||
; CHECK-NEXT: csetm r12, ne
|
||||
; CHECK-NEXT: orrs r2, r3
|
||||
; CHECK-NEXT: vmov r3, s2
|
||||
; CHECK-NEXT: cset r2, eq
|
||||
; CHECK-NEXT: tst.w r2, #1
|
||||
; CHECK-NEXT: cmp r2, #0
|
||||
; CHECK-NEXT: vmov r2, s3
|
||||
; CHECK-NEXT: csetm r4, ne
|
||||
; CHECK-NEXT: orrs r2, r3
|
||||
; CHECK-NEXT: vmov r3, s0
|
||||
; CHECK-NEXT: cset r2, eq
|
||||
; CHECK-NEXT: tst.w r2, #1
|
||||
; CHECK-NEXT: cmp r2, #0
|
||||
; CHECK-NEXT: vmov r2, s1
|
||||
; CHECK-NEXT: csetm lr, ne
|
||||
; CHECK-NEXT: orrs r2, r3
|
||||
; CHECK-NEXT: cset r2, eq
|
||||
; CHECK-NEXT: tst.w r2, #1
|
||||
; CHECK-NEXT: cmp r2, #0
|
||||
; CHECK-NEXT: csetm r2, ne
|
||||
; CHECK-NEXT: orrs r0, r1
|
||||
; CHECK-NEXT: beq .LBB15_2
|
||||
|
||||
@ -463,12 +463,12 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeqz_v2i1(<2 x i64> %a, <2 x i64> %b) {
|
||||
; CHECK-NEXT: orrs r0, r1
|
||||
; CHECK-NEXT: vmov r1, s5
|
||||
; CHECK-NEXT: cset r0, eq
|
||||
; CHECK-NEXT: tst.w r0, #1
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: csetm r0, ne
|
||||
; CHECK-NEXT: orrs r1, r2
|
||||
; CHECK-NEXT: vmov r2, s0
|
||||
; CHECK-NEXT: cset r1, eq
|
||||
; CHECK-NEXT: tst.w r1, #1
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: csetm r1, ne
|
||||
; CHECK-NEXT: vmov q2[2], q2[0], r1, r0
|
||||
; CHECK-NEXT: vmov q2[3], q2[1], r1, r0
|
||||
@ -477,11 +477,11 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeqz_v2i1(<2 x i64> %a, <2 x i64> %b) {
|
||||
; CHECK-NEXT: orrs r0, r1
|
||||
; CHECK-NEXT: vmov r1, s1
|
||||
; CHECK-NEXT: cset r0, eq
|
||||
; CHECK-NEXT: tst.w r0, #1
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: csetm r0, ne
|
||||
; CHECK-NEXT: orrs r1, r2
|
||||
; CHECK-NEXT: cset r1, eq
|
||||
; CHECK-NEXT: tst.w r1, #1
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: csetm r1, ne
|
||||
; CHECK-NEXT: vmov q3[2], q3[0], r1, r0
|
||||
; CHECK-NEXT: vmov q3[3], q3[1], r1, r0
|
||||
@ -512,7 +512,7 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeq_v2i1(<2 x i64> %a, <2 x i64> %b, <2 x i6
|
||||
; CHECK-NEXT: orrs r0, r1
|
||||
; CHECK-NEXT: vmov r1, s9
|
||||
; CHECK-NEXT: cset r0, eq
|
||||
; CHECK-NEXT: tst.w r0, #1
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: csetm r0, ne
|
||||
; CHECK-NEXT: eors r1, r2
|
||||
; CHECK-NEXT: vmov r2, s8
|
||||
@ -520,7 +520,7 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeq_v2i1(<2 x i64> %a, <2 x i64> %b, <2 x i6
|
||||
; CHECK-NEXT: orrs r1, r2
|
||||
; CHECK-NEXT: vmov r2, s0
|
||||
; CHECK-NEXT: cset r1, eq
|
||||
; CHECK-NEXT: tst.w r1, #1
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: csetm r1, ne
|
||||
; CHECK-NEXT: vmov q2[2], q2[0], r1, r0
|
||||
; CHECK-NEXT: vmov q2[3], q2[1], r1, r0
|
||||
@ -529,11 +529,11 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeq_v2i1(<2 x i64> %a, <2 x i64> %b, <2 x i6
|
||||
; CHECK-NEXT: orrs r0, r1
|
||||
; CHECK-NEXT: vmov r1, s1
|
||||
; CHECK-NEXT: cset r0, eq
|
||||
; CHECK-NEXT: tst.w r0, #1
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: csetm r0, ne
|
||||
; CHECK-NEXT: orrs r1, r2
|
||||
; CHECK-NEXT: cset r1, eq
|
||||
; CHECK-NEXT: tst.w r1, #1
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: csetm r1, ne
|
||||
; CHECK-NEXT: vmov q3[2], q3[0], r1, r0
|
||||
; CHECK-NEXT: vmov q3[3], q3[1], r1, r0
|
||||
|
||||
@ -49,9 +49,9 @@ define arm_aapcs_vfpcc <2 x i64> @sadd_int64_t(<2 x i64> %src1, <2 x i64> %src2)
|
||||
; CHECK-NEXT: eors r1, r0
|
||||
; CHECK-NEXT: bic.w r1, r1, r12
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: cset r1, mi
|
||||
; CHECK-NEXT: ands r12, r1, #1
|
||||
; CHECK-NEXT: vmov r1, s1
|
||||
; CHECK-NEXT: cset r12, mi
|
||||
; CHECK-NEXT: cmp.w r12, #0
|
||||
; CHECK-NEXT: it ne
|
||||
; CHECK-NEXT: asrne r2, r0, #31
|
||||
; CHECK-NEXT: adds r4, r4, r5
|
||||
@ -62,19 +62,19 @@ define arm_aapcs_vfpcc <2 x i64> @sadd_int64_t(<2 x i64> %src1, <2 x i64> %src2)
|
||||
; CHECK-NEXT: bic.w r1, r1, lr
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: cset r1, mi
|
||||
; CHECK-NEXT: ands r1, r1, #1
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: it ne
|
||||
; CHECK-NEXT: asrne r4, r3, #31
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: vmov q0[2], q0[0], r4, r2
|
||||
; CHECK-NEXT: cset r2, mi
|
||||
; CHECK-NEXT: tst.w r2, #1
|
||||
; CHECK-NEXT: cmp r2, #0
|
||||
; CHECK-NEXT: cinv r2, r5, eq
|
||||
; CHECK-NEXT: cmp.w r12, #0
|
||||
; CHECK-NEXT: csel r0, r2, r0, ne
|
||||
; CHECK-NEXT: cmp r3, #0
|
||||
; CHECK-NEXT: cset r2, mi
|
||||
; CHECK-NEXT: tst.w r2, #1
|
||||
; CHECK-NEXT: cmp r2, #0
|
||||
; CHECK-NEXT: cinv r2, r5, eq
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: csel r1, r2, r3, ne
|
||||
@ -201,9 +201,9 @@ define arm_aapcs_vfpcc <2 x i64> @ssub_int64_t(<2 x i64> %src1, <2 x i64> %src2)
|
||||
; CHECK-NEXT: sbc.w r0, r1, r0
|
||||
; CHECK-NEXT: eors r1, r0
|
||||
; CHECK-NEXT: ands.w r1, r1, r12
|
||||
; CHECK-NEXT: cset r1, mi
|
||||
; CHECK-NEXT: ands r12, r1, #1
|
||||
; CHECK-NEXT: vmov r1, s1
|
||||
; CHECK-NEXT: cset r12, mi
|
||||
; CHECK-NEXT: cmp.w r12, #0
|
||||
; CHECK-NEXT: it ne
|
||||
; CHECK-NEXT: asrne r2, r0, #31
|
||||
; CHECK-NEXT: subs r4, r5, r4
|
||||
@ -213,19 +213,19 @@ define arm_aapcs_vfpcc <2 x i64> @ssub_int64_t(<2 x i64> %src1, <2 x i64> %src2)
|
||||
; CHECK-NEXT: eors r1, r3
|
||||
; CHECK-NEXT: ands.w r1, r1, lr
|
||||
; CHECK-NEXT: cset r1, mi
|
||||
; CHECK-NEXT: ands r1, r1, #1
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: it ne
|
||||
; CHECK-NEXT: asrne r4, r3, #31
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: vmov q0[2], q0[0], r4, r2
|
||||
; CHECK-NEXT: cset r2, mi
|
||||
; CHECK-NEXT: tst.w r2, #1
|
||||
; CHECK-NEXT: cmp r2, #0
|
||||
; CHECK-NEXT: cinv r2, r5, eq
|
||||
; CHECK-NEXT: cmp.w r12, #0
|
||||
; CHECK-NEXT: csel r0, r2, r0, ne
|
||||
; CHECK-NEXT: cmp r3, #0
|
||||
; CHECK-NEXT: cset r2, mi
|
||||
; CHECK-NEXT: tst.w r2, #1
|
||||
; CHECK-NEXT: cmp r2, #0
|
||||
; CHECK-NEXT: cinv r2, r5, eq
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: csel r1, r2, r3, ne
|
||||
|
||||
@ -218,7 +218,7 @@ define i32 @e() {
|
||||
; CHECK-NEXT: vadd.i32 q2, q2, q1
|
||||
; CHECK-NEXT: cmp r0, #8
|
||||
; CHECK-NEXT: cset r1, eq
|
||||
; CHECK-NEXT: tst.w r1, #1
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: csetm r1, ne
|
||||
; CHECK-NEXT: subs.w r2, r0, #8
|
||||
; CHECK-NEXT: vdup.32 q3, r1
|
||||
|
||||
@ -378,14 +378,14 @@ define arm_aapcs_vfpcc <2 x i64> @vcmp_eq_v2i64(<2 x i64> %src, <2 x i64> %srcb,
|
||||
; CHECK-NEXT: orrs r0, r1
|
||||
; CHECK-NEXT: vmov r1, s5
|
||||
; CHECK-NEXT: cset r0, eq
|
||||
; CHECK-NEXT: tst.w r0, #1
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: csetm r0, ne
|
||||
; CHECK-NEXT: eors r1, r2
|
||||
; CHECK-NEXT: vmov r2, s4
|
||||
; CHECK-NEXT: eors r2, r3
|
||||
; CHECK-NEXT: orrs r1, r2
|
||||
; CHECK-NEXT: cset r1, eq
|
||||
; CHECK-NEXT: tst.w r1, #1
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: csetm r1, ne
|
||||
; CHECK-NEXT: vmov q0[2], q0[0], r1, r0
|
||||
; CHECK-NEXT: vmov q0[3], q0[1], r1, r0
|
||||
@ -413,14 +413,14 @@ define arm_aapcs_vfpcc <2 x i32> @vcmp_eq_v2i32(<2 x i64> %src, <2 x i64> %srcb,
|
||||
; CHECK-NEXT: orrs r0, r1
|
||||
; CHECK-NEXT: vmov r1, s5
|
||||
; CHECK-NEXT: cset r0, eq
|
||||
; CHECK-NEXT: tst.w r0, #1
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: csetm r0, ne
|
||||
; CHECK-NEXT: eors r1, r2
|
||||
; CHECK-NEXT: vmov r2, s4
|
||||
; CHECK-NEXT: eors r2, r3
|
||||
; CHECK-NEXT: orrs r1, r2
|
||||
; CHECK-NEXT: cset r1, eq
|
||||
; CHECK-NEXT: tst.w r1, #1
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: csetm r1, ne
|
||||
; CHECK-NEXT: vmov q0[2], q0[0], r1, r0
|
||||
; CHECK-NEXT: vmov q0[3], q0[1], r1, r0
|
||||
@ -448,12 +448,12 @@ define arm_aapcs_vfpcc <2 x i32> @vcmp_multi_v2i32(<2 x i64> %a, <2 x i32> %b, <
|
||||
; CHECK-NEXT: orrs r0, r1
|
||||
; CHECK-NEXT: vmov r1, s1
|
||||
; CHECK-NEXT: cset r0, eq
|
||||
; CHECK-NEXT: tst.w r0, #1
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: csetm r0, ne
|
||||
; CHECK-NEXT: orrs r1, r2
|
||||
; CHECK-NEXT: vmov r2, s10
|
||||
; CHECK-NEXT: cset r1, eq
|
||||
; CHECK-NEXT: tst.w r1, #1
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: csetm r1, ne
|
||||
; CHECK-NEXT: vmov q0[2], q0[0], r1, r0
|
||||
; CHECK-NEXT: vmov q0[3], q0[1], r1, r0
|
||||
@ -479,12 +479,12 @@ define arm_aapcs_vfpcc <2 x i32> @vcmp_multi_v2i32(<2 x i64> %a, <2 x i32> %b, <
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: cset r0, ne
|
||||
; CHECK-NEXT: vmov q3[2], q3[0], r1, lr
|
||||
; CHECK-NEXT: tst.w r0, #1
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: vmov q3[3], q3[1], r1, lr
|
||||
; CHECK-NEXT: csetm r0, ne
|
||||
; CHECK-NEXT: cmp r2, #0
|
||||
; CHECK-NEXT: cset r1, ne
|
||||
; CHECK-NEXT: tst.w r1, #1
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: csetm r1, ne
|
||||
; CHECK-NEXT: vmov q4[2], q4[0], r1, r0
|
||||
; CHECK-NEXT: vmov q4[3], q4[1], r1, r0
|
||||
@ -492,11 +492,11 @@ define arm_aapcs_vfpcc <2 x i32> @vcmp_multi_v2i32(<2 x i64> %a, <2 x i32> %b, <
|
||||
; CHECK-NEXT: vmov r1, s4
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: cset r0, ne
|
||||
; CHECK-NEXT: tst.w r0, #1
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: csetm r0, ne
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: cset r1, ne
|
||||
; CHECK-NEXT: tst.w r1, #1
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: csetm r1, ne
|
||||
; CHECK-NEXT: vmov q1[2], q1[0], r1, r0
|
||||
; CHECK-NEXT: vmov q1[3], q1[1], r1, r0
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -440,14 +440,14 @@ define arm_aapcs_vfpcc <2 x i64> @vcmp_eq_v2i64(<2 x i64> %src, i64 %src2, <2 x
|
||||
; CHECK-NEXT: orrs r2, r3
|
||||
; CHECK-NEXT: vmov r3, s1
|
||||
; CHECK-NEXT: cset r2, eq
|
||||
; CHECK-NEXT: tst.w r2, #1
|
||||
; CHECK-NEXT: cmp r2, #0
|
||||
; CHECK-NEXT: csetm r2, ne
|
||||
; CHECK-NEXT: eors r1, r3
|
||||
; CHECK-NEXT: vmov r3, s0
|
||||
; CHECK-NEXT: eors r0, r3
|
||||
; CHECK-NEXT: orrs r0, r1
|
||||
; CHECK-NEXT: cset r0, eq
|
||||
; CHECK-NEXT: tst.w r0, #1
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: csetm r0, ne
|
||||
; CHECK-NEXT: vmov q0[2], q0[0], r0, r2
|
||||
; CHECK-NEXT: vmov q0[3], q0[1], r0, r2
|
||||
@ -473,14 +473,14 @@ define arm_aapcs_vfpcc <2 x i32> @vcmp_eq_v2i32(<2 x i64> %src, i64 %src2, <2 x
|
||||
; CHECK-NEXT: orrs r2, r3
|
||||
; CHECK-NEXT: vmov r3, s1
|
||||
; CHECK-NEXT: cset r2, eq
|
||||
; CHECK-NEXT: tst.w r2, #1
|
||||
; CHECK-NEXT: cmp r2, #0
|
||||
; CHECK-NEXT: csetm r2, ne
|
||||
; CHECK-NEXT: eors r1, r3
|
||||
; CHECK-NEXT: vmov r3, s0
|
||||
; CHECK-NEXT: eors r0, r3
|
||||
; CHECK-NEXT: orrs r0, r1
|
||||
; CHECK-NEXT: cset r0, eq
|
||||
; CHECK-NEXT: tst.w r0, #1
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: csetm r0, ne
|
||||
; CHECK-NEXT: vmov q0[2], q0[0], r0, r2
|
||||
; CHECK-NEXT: vmov q0[3], q0[1], r0, r2
|
||||
@ -510,12 +510,12 @@ define arm_aapcs_vfpcc <2 x i32> @vcmp_multi_v2i32(<2 x i64> %a, <2 x i32> %b, <
|
||||
; CHECK-NEXT: orrs r0, r1
|
||||
; CHECK-NEXT: vmov r1, s1
|
||||
; CHECK-NEXT: cset r0, eq
|
||||
; CHECK-NEXT: tst.w r0, #1
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: csetm r0, ne
|
||||
; CHECK-NEXT: orrs r1, r2
|
||||
; CHECK-NEXT: vmov r2, s10
|
||||
; CHECK-NEXT: cset r1, eq
|
||||
; CHECK-NEXT: tst.w r1, #1
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: csetm r1, ne
|
||||
; CHECK-NEXT: vmov q0[2], q0[0], r1, r0
|
||||
; CHECK-NEXT: vmov q0[3], q0[1], r1, r0
|
||||
@ -541,12 +541,12 @@ define arm_aapcs_vfpcc <2 x i32> @vcmp_multi_v2i32(<2 x i64> %a, <2 x i32> %b, <
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: cset r0, ne
|
||||
; CHECK-NEXT: vmov q3[2], q3[0], r1, lr
|
||||
; CHECK-NEXT: tst.w r0, #1
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: vmov q3[3], q3[1], r1, lr
|
||||
; CHECK-NEXT: csetm r0, ne
|
||||
; CHECK-NEXT: cmp r2, #0
|
||||
; CHECK-NEXT: cset r1, ne
|
||||
; CHECK-NEXT: tst.w r1, #1
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: csetm r1, ne
|
||||
; CHECK-NEXT: vmov q4[2], q4[0], r1, r0
|
||||
; CHECK-NEXT: vmov q4[3], q4[1], r1, r0
|
||||
@ -554,11 +554,11 @@ define arm_aapcs_vfpcc <2 x i32> @vcmp_multi_v2i32(<2 x i64> %a, <2 x i32> %b, <
|
||||
; CHECK-NEXT: vmov r1, s4
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: cset r0, ne
|
||||
; CHECK-NEXT: tst.w r0, #1
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: csetm r0, ne
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: cset r1, ne
|
||||
; CHECK-NEXT: tst.w r1, #1
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: csetm r1, ne
|
||||
; CHECK-NEXT: vmov q1[2], q1[0], r1, r0
|
||||
; CHECK-NEXT: vmov q1[3], q1[1], r1, r0
|
||||
@ -1021,14 +1021,14 @@ define arm_aapcs_vfpcc <2 x i64> @vcmp_r_eq_v2i64(<2 x i64> %src, i64 %src2, <2
|
||||
; CHECK-NEXT: orrs r2, r3
|
||||
; CHECK-NEXT: vmov r3, s1
|
||||
; CHECK-NEXT: cset r2, eq
|
||||
; CHECK-NEXT: tst.w r2, #1
|
||||
; CHECK-NEXT: cmp r2, #0
|
||||
; CHECK-NEXT: csetm r2, ne
|
||||
; CHECK-NEXT: eors r1, r3
|
||||
; CHECK-NEXT: vmov r3, s0
|
||||
; CHECK-NEXT: eors r0, r3
|
||||
; CHECK-NEXT: orrs r0, r1
|
||||
; CHECK-NEXT: cset r0, eq
|
||||
; CHECK-NEXT: tst.w r0, #1
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: csetm r0, ne
|
||||
; CHECK-NEXT: vmov q0[2], q0[0], r0, r2
|
||||
; CHECK-NEXT: vmov q0[3], q0[1], r0, r2
|
||||
@ -1054,14 +1054,14 @@ define arm_aapcs_vfpcc <2 x i32> @vcmp_r_eq_v2i32(<2 x i64> %src, i64 %src2, <2
|
||||
; CHECK-NEXT: orrs r2, r3
|
||||
; CHECK-NEXT: vmov r3, s1
|
||||
; CHECK-NEXT: cset r2, eq
|
||||
; CHECK-NEXT: tst.w r2, #1
|
||||
; CHECK-NEXT: cmp r2, #0
|
||||
; CHECK-NEXT: csetm r2, ne
|
||||
; CHECK-NEXT: eors r1, r3
|
||||
; CHECK-NEXT: vmov r3, s0
|
||||
; CHECK-NEXT: eors r0, r3
|
||||
; CHECK-NEXT: orrs r0, r1
|
||||
; CHECK-NEXT: cset r0, eq
|
||||
; CHECK-NEXT: tst.w r0, #1
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: csetm r0, ne
|
||||
; CHECK-NEXT: vmov q0[2], q0[0], r0, r2
|
||||
; CHECK-NEXT: vmov q0[3], q0[1], r0, r2
|
||||
@ -1091,12 +1091,12 @@ define arm_aapcs_vfpcc <2 x i32> @vcmp_r_multi_v2i32(<2 x i64> %a, <2 x i32> %b,
|
||||
; CHECK-NEXT: orrs r0, r1
|
||||
; CHECK-NEXT: vmov r1, s1
|
||||
; CHECK-NEXT: cset r0, eq
|
||||
; CHECK-NEXT: tst.w r0, #1
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: csetm r0, ne
|
||||
; CHECK-NEXT: orrs r1, r2
|
||||
; CHECK-NEXT: vmov r2, s10
|
||||
; CHECK-NEXT: cset r1, eq
|
||||
; CHECK-NEXT: tst.w r1, #1
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: csetm r1, ne
|
||||
; CHECK-NEXT: vmov q0[2], q0[0], r1, r0
|
||||
; CHECK-NEXT: vmov q0[3], q0[1], r1, r0
|
||||
@ -1122,12 +1122,12 @@ define arm_aapcs_vfpcc <2 x i32> @vcmp_r_multi_v2i32(<2 x i64> %a, <2 x i32> %b,
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: cset r0, ne
|
||||
; CHECK-NEXT: vmov q3[2], q3[0], r1, lr
|
||||
; CHECK-NEXT: tst.w r0, #1
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: vmov q3[3], q3[1], r1, lr
|
||||
; CHECK-NEXT: csetm r0, ne
|
||||
; CHECK-NEXT: cmp r2, #0
|
||||
; CHECK-NEXT: cset r1, ne
|
||||
; CHECK-NEXT: tst.w r1, #1
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: csetm r1, ne
|
||||
; CHECK-NEXT: vmov q4[2], q4[0], r1, r0
|
||||
; CHECK-NEXT: vmov q4[3], q4[1], r1, r0
|
||||
@ -1135,11 +1135,11 @@ define arm_aapcs_vfpcc <2 x i32> @vcmp_r_multi_v2i32(<2 x i64> %a, <2 x i32> %b,
|
||||
; CHECK-NEXT: vmov r1, s4
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: cset r0, ne
|
||||
; CHECK-NEXT: tst.w r0, #1
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: csetm r0, ne
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: cset r1, ne
|
||||
; CHECK-NEXT: tst.w r1, #1
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: csetm r1, ne
|
||||
; CHECK-NEXT: vmov q1[2], q1[0], r1, r0
|
||||
; CHECK-NEXT: vmov q1[3], q1[1], r1, r0
|
||||
|
||||
@ -367,11 +367,11 @@ define arm_aapcs_vfpcc <2 x i64> @vcmp_eqz_v2i64(<2 x i64> %src, <2 x i64> %a, <
|
||||
; CHECK-NEXT: orrs r0, r1
|
||||
; CHECK-NEXT: vmov r1, s1
|
||||
; CHECK-NEXT: cset r0, eq
|
||||
; CHECK-NEXT: tst.w r0, #1
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: csetm r0, ne
|
||||
; CHECK-NEXT: orrs r1, r2
|
||||
; CHECK-NEXT: cset r1, eq
|
||||
; CHECK-NEXT: tst.w r1, #1
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: csetm r1, ne
|
||||
; CHECK-NEXT: vmov q0[2], q0[0], r1, r0
|
||||
; CHECK-NEXT: vmov q0[3], q0[1], r1, r0
|
||||
@ -394,11 +394,11 @@ define arm_aapcs_vfpcc <2 x i32> @vcmp_eqz_v2i32(<2 x i64> %src, <2 x i32> %a, <
|
||||
; CHECK-NEXT: orrs r0, r1
|
||||
; CHECK-NEXT: vmov r1, s1
|
||||
; CHECK-NEXT: cset r0, eq
|
||||
; CHECK-NEXT: tst.w r0, #1
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: csetm r0, ne
|
||||
; CHECK-NEXT: orrs r1, r2
|
||||
; CHECK-NEXT: cset r1, eq
|
||||
; CHECK-NEXT: tst.w r1, #1
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: csetm r1, ne
|
||||
; CHECK-NEXT: vmov q0[2], q0[0], r1, r0
|
||||
; CHECK-NEXT: vmov q0[3], q0[1], r1, r0
|
||||
@ -781,11 +781,11 @@ define arm_aapcs_vfpcc <2 x i64> @vcmp_r_eqz_v2i64(<2 x i64> %src, <2 x i64> %a,
|
||||
; CHECK-NEXT: orrs r0, r1
|
||||
; CHECK-NEXT: vmov r1, s1
|
||||
; CHECK-NEXT: cset r0, eq
|
||||
; CHECK-NEXT: tst.w r0, #1
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: csetm r0, ne
|
||||
; CHECK-NEXT: orrs r1, r2
|
||||
; CHECK-NEXT: cset r1, eq
|
||||
; CHECK-NEXT: tst.w r1, #1
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: csetm r1, ne
|
||||
; CHECK-NEXT: vmov q0[2], q0[0], r1, r0
|
||||
; CHECK-NEXT: vmov q0[3], q0[1], r1, r0
|
||||
@ -808,11 +808,11 @@ define arm_aapcs_vfpcc <2 x i32> @vcmp_r_eqz_v2i32(<2 x i64> %src, <2 x i32> %a,
|
||||
; CHECK-NEXT: orrs r0, r1
|
||||
; CHECK-NEXT: vmov r1, s1
|
||||
; CHECK-NEXT: cset r0, eq
|
||||
; CHECK-NEXT: tst.w r0, #1
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: csetm r0, ne
|
||||
; CHECK-NEXT: orrs r1, r2
|
||||
; CHECK-NEXT: cset r1, eq
|
||||
; CHECK-NEXT: tst.w r1, #1
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: csetm r1, ne
|
||||
; CHECK-NEXT: vmov q0[2], q0[0], r1, r0
|
||||
; CHECK-NEXT: vmov q0[3], q0[1], r1, r0
|
||||
|
||||
@ -51,11 +51,11 @@ define arm_aapcs_vfpcc i64 @add_v2i32_v2i64_zext(<2 x i32> %x, <2 x i32> %b) {
|
||||
; CHECK-NEXT: vand q0, q0, q2
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: cset r0, eq
|
||||
; CHECK-NEXT: tst.w r0, #1
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: csetm r0, ne
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: cset r1, eq
|
||||
; CHECK-NEXT: tst.w r1, #1
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: csetm r1, ne
|
||||
; CHECK-NEXT: vmov q1[2], q1[0], r1, r0
|
||||
; CHECK-NEXT: vmov q1[3], q1[1], r1, r0
|
||||
@ -88,11 +88,11 @@ define arm_aapcs_vfpcc i64 @add_v2i32_v2i64_sext(<2 x i32> %x, <2 x i32> %b) {
|
||||
; CHECK-NEXT: vmov r1, s4
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: cset r0, eq
|
||||
; CHECK-NEXT: tst.w r0, #1
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: csetm r0, ne
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: cset r1, eq
|
||||
; CHECK-NEXT: tst.w r1, #1
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: csetm r1, ne
|
||||
; CHECK-NEXT: vmov q1[2], q1[0], r1, r0
|
||||
; CHECK-NEXT: vmov q1[3], q1[1], r1, r0
|
||||
@ -452,11 +452,11 @@ define arm_aapcs_vfpcc i64 @add_v2i16_v2i64_zext(<2 x i16> %x, <2 x i16> %b) {
|
||||
; CHECK-NEXT: vmov r1, s4
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: cset r0, eq
|
||||
; CHECK-NEXT: tst.w r0, #1
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: csetm r0, ne
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: cset r1, eq
|
||||
; CHECK-NEXT: tst.w r1, #1
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: csetm r1, ne
|
||||
; CHECK-NEXT: vmov q1[2], q1[0], r1, r0
|
||||
; CHECK-NEXT: vmov q1[3], q1[1], r1, r0
|
||||
@ -485,11 +485,11 @@ define arm_aapcs_vfpcc i64 @add_v2i16_v2i64_sext(<2 x i16> %x, <2 x i16> %b) {
|
||||
; CHECK-NEXT: vmov r1, s4
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: cset r0, eq
|
||||
; CHECK-NEXT: tst.w r0, #1
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: csetm r0, ne
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: cset r1, eq
|
||||
; CHECK-NEXT: tst.w r1, #1
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: csetm r1, ne
|
||||
; CHECK-NEXT: vmov q1[2], q1[0], r1, r0
|
||||
; CHECK-NEXT: vmov q1[3], q1[1], r1, r0
|
||||
@ -1534,11 +1534,11 @@ define arm_aapcs_vfpcc i64 @add_v2i8_v2i64_zext(<2 x i8> %x, <2 x i8> %b) {
|
||||
; CHECK-NEXT: vmov r1, s4
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: cset r0, eq
|
||||
; CHECK-NEXT: tst.w r0, #1
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: csetm r0, ne
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: cset r1, eq
|
||||
; CHECK-NEXT: tst.w r1, #1
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: csetm r1, ne
|
||||
; CHECK-NEXT: vmov q1[2], q1[0], r1, r0
|
||||
; CHECK-NEXT: vmov q1[3], q1[1], r1, r0
|
||||
@ -1567,11 +1567,11 @@ define arm_aapcs_vfpcc i64 @add_v2i8_v2i64_sext(<2 x i8> %x, <2 x i8> %b) {
|
||||
; CHECK-NEXT: vmov r1, s4
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: cset r0, eq
|
||||
; CHECK-NEXT: tst.w r0, #1
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: csetm r0, ne
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: cset r1, eq
|
||||
; CHECK-NEXT: tst.w r1, #1
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: csetm r1, ne
|
||||
; CHECK-NEXT: vmov q1[2], q1[0], r1, r0
|
||||
; CHECK-NEXT: vmov q1[3], q1[1], r1, r0
|
||||
@ -1608,11 +1608,11 @@ define arm_aapcs_vfpcc i64 @add_v2i64_v2i64(<2 x i64> %x, <2 x i64> %b) {
|
||||
; CHECK-NEXT: orrs r0, r1
|
||||
; CHECK-NEXT: vmov r1, s5
|
||||
; CHECK-NEXT: cset r0, eq
|
||||
; CHECK-NEXT: tst.w r0, #1
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: csetm r0, ne
|
||||
; CHECK-NEXT: orrs r1, r2
|
||||
; CHECK-NEXT: cset r1, eq
|
||||
; CHECK-NEXT: tst.w r1, #1
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: csetm r1, ne
|
||||
; CHECK-NEXT: vmov q1[2], q1[0], r1, r0
|
||||
; CHECK-NEXT: vmov q1[3], q1[1], r1, r0
|
||||
@ -1686,11 +1686,11 @@ define arm_aapcs_vfpcc i64 @add_v2i32_v2i64_acc_zext(<2 x i32> %x, <2 x i32> %b,
|
||||
; CHECK-NEXT: vand q0, q0, q2
|
||||
; CHECK-NEXT: cmp r2, #0
|
||||
; CHECK-NEXT: cset r2, eq
|
||||
; CHECK-NEXT: tst.w r2, #1
|
||||
; CHECK-NEXT: cmp r2, #0
|
||||
; CHECK-NEXT: csetm r2, ne
|
||||
; CHECK-NEXT: cmp r3, #0
|
||||
; CHECK-NEXT: cset r3, eq
|
||||
; CHECK-NEXT: tst.w r3, #1
|
||||
; CHECK-NEXT: cmp r3, #0
|
||||
; CHECK-NEXT: csetm r3, ne
|
||||
; CHECK-NEXT: vmov q1[2], q1[0], r3, r2
|
||||
; CHECK-NEXT: vmov q1[3], q1[1], r3, r2
|
||||
@ -1728,11 +1728,11 @@ define arm_aapcs_vfpcc i64 @add_v2i32_v2i64_acc_sext(<2 x i32> %x, <2 x i32> %b,
|
||||
; CHECK-NEXT: vmov r3, s4
|
||||
; CHECK-NEXT: cmp r2, #0
|
||||
; CHECK-NEXT: cset r2, eq
|
||||
; CHECK-NEXT: tst.w r2, #1
|
||||
; CHECK-NEXT: cmp r2, #0
|
||||
; CHECK-NEXT: csetm r2, ne
|
||||
; CHECK-NEXT: cmp r3, #0
|
||||
; CHECK-NEXT: cset r3, eq
|
||||
; CHECK-NEXT: tst.w r3, #1
|
||||
; CHECK-NEXT: cmp r3, #0
|
||||
; CHECK-NEXT: csetm r3, ne
|
||||
; CHECK-NEXT: vmov q1[2], q1[0], r3, r2
|
||||
; CHECK-NEXT: vmov q1[3], q1[1], r3, r2
|
||||
@ -2078,11 +2078,11 @@ define arm_aapcs_vfpcc i64 @add_v2i16_v2i64_acc_zext(<2 x i16> %x, <2 x i16> %b,
|
||||
; CHECK-NEXT: vmov r3, s4
|
||||
; CHECK-NEXT: cmp r2, #0
|
||||
; CHECK-NEXT: cset r2, eq
|
||||
; CHECK-NEXT: tst.w r2, #1
|
||||
; CHECK-NEXT: cmp r2, #0
|
||||
; CHECK-NEXT: csetm r2, ne
|
||||
; CHECK-NEXT: cmp r3, #0
|
||||
; CHECK-NEXT: cset r3, eq
|
||||
; CHECK-NEXT: tst.w r3, #1
|
||||
; CHECK-NEXT: cmp r3, #0
|
||||
; CHECK-NEXT: csetm r3, ne
|
||||
; CHECK-NEXT: vmov q1[2], q1[0], r3, r2
|
||||
; CHECK-NEXT: vmov q1[3], q1[1], r3, r2
|
||||
@ -2116,11 +2116,11 @@ define arm_aapcs_vfpcc i64 @add_v2i16_v2i64_acc_sext(<2 x i16> %x, <2 x i16> %b,
|
||||
; CHECK-NEXT: vmov r3, s4
|
||||
; CHECK-NEXT: cmp r2, #0
|
||||
; CHECK-NEXT: cset r2, eq
|
||||
; CHECK-NEXT: tst.w r2, #1
|
||||
; CHECK-NEXT: cmp r2, #0
|
||||
; CHECK-NEXT: csetm r2, ne
|
||||
; CHECK-NEXT: cmp r3, #0
|
||||
; CHECK-NEXT: cset r3, eq
|
||||
; CHECK-NEXT: tst.w r3, #1
|
||||
; CHECK-NEXT: cmp r3, #0
|
||||
; CHECK-NEXT: csetm r3, ne
|
||||
; CHECK-NEXT: vmov q1[2], q1[0], r3, r2
|
||||
; CHECK-NEXT: vmov q1[3], q1[1], r3, r2
|
||||
@ -2812,11 +2812,11 @@ define arm_aapcs_vfpcc i64 @add_v2i8_v2i64_acc_zext(<2 x i8> %x, <2 x i8> %b, i6
|
||||
; CHECK-NEXT: vmov r3, s4
|
||||
; CHECK-NEXT: cmp r2, #0
|
||||
; CHECK-NEXT: cset r2, eq
|
||||
; CHECK-NEXT: tst.w r2, #1
|
||||
; CHECK-NEXT: cmp r2, #0
|
||||
; CHECK-NEXT: csetm r2, ne
|
||||
; CHECK-NEXT: cmp r3, #0
|
||||
; CHECK-NEXT: cset r3, eq
|
||||
; CHECK-NEXT: tst.w r3, #1
|
||||
; CHECK-NEXT: cmp r3, #0
|
||||
; CHECK-NEXT: csetm r3, ne
|
||||
; CHECK-NEXT: vmov q1[2], q1[0], r3, r2
|
||||
; CHECK-NEXT: vmov q1[3], q1[1], r3, r2
|
||||
@ -2850,11 +2850,11 @@ define arm_aapcs_vfpcc i64 @add_v2i8_v2i64_acc_sext(<2 x i8> %x, <2 x i8> %b, i6
|
||||
; CHECK-NEXT: vmov r3, s4
|
||||
; CHECK-NEXT: cmp r2, #0
|
||||
; CHECK-NEXT: cset r2, eq
|
||||
; CHECK-NEXT: tst.w r2, #1
|
||||
; CHECK-NEXT: cmp r2, #0
|
||||
; CHECK-NEXT: csetm r2, ne
|
||||
; CHECK-NEXT: cmp r3, #0
|
||||
; CHECK-NEXT: cset r3, eq
|
||||
; CHECK-NEXT: tst.w r3, #1
|
||||
; CHECK-NEXT: cmp r3, #0
|
||||
; CHECK-NEXT: csetm r3, ne
|
||||
; CHECK-NEXT: vmov q1[2], q1[0], r3, r2
|
||||
; CHECK-NEXT: vmov q1[3], q1[1], r3, r2
|
||||
@ -2896,11 +2896,11 @@ define arm_aapcs_vfpcc i64 @add_v2i64_v2i64_acc(<2 x i64> %x, <2 x i64> %b, i64
|
||||
; CHECK-NEXT: orrs r2, r3
|
||||
; CHECK-NEXT: vmov r3, s4
|
||||
; CHECK-NEXT: cset r2, eq
|
||||
; CHECK-NEXT: tst.w r2, #1
|
||||
; CHECK-NEXT: cmp r2, #0
|
||||
; CHECK-NEXT: csetm r2, ne
|
||||
; CHECK-NEXT: orrs.w r3, r3, r12
|
||||
; CHECK-NEXT: cset r3, eq
|
||||
; CHECK-NEXT: tst.w r3, #1
|
||||
; CHECK-NEXT: cmp r3, #0
|
||||
; CHECK-NEXT: csetm r3, ne
|
||||
; CHECK-NEXT: vmov q1[2], q1[0], r3, r2
|
||||
; CHECK-NEXT: vmov q1[3], q1[1], r3, r2
|
||||
|
||||
@ -55,11 +55,11 @@ define arm_aapcs_vfpcc i64 @add_v2i32_v2i64_zext(<2 x i32> %x, <2 x i32> %y, <2
|
||||
; CHECK-NEXT: vmov r1, s8
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: cset r0, eq
|
||||
; CHECK-NEXT: tst.w r0, #1
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: csetm r0, ne
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: cset r1, eq
|
||||
; CHECK-NEXT: tst.w r1, #1
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: csetm r1, ne
|
||||
; CHECK-NEXT: vmov q0[2], q0[0], r1, r0
|
||||
; CHECK-NEXT: vmov q0[3], q0[1], r1, r0
|
||||
@ -89,11 +89,11 @@ define arm_aapcs_vfpcc i64 @add_v2i32_v2i64_sext(<2 x i32> %x, <2 x i32> %y, <2
|
||||
; CHECK-NEXT: vmov r1, s8
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: cset r0, eq
|
||||
; CHECK-NEXT: tst.w r0, #1
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: csetm r0, ne
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: cset r1, eq
|
||||
; CHECK-NEXT: tst.w r1, #1
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: csetm r1, ne
|
||||
; CHECK-NEXT: vmov q0[2], q0[0], r1, r0
|
||||
; CHECK-NEXT: vmov q0[3], q0[1], r1, r0
|
||||
@ -339,11 +339,11 @@ define arm_aapcs_vfpcc i64 @add_v2i16_v2i64_zext(<2 x i16> %x, <2 x i16> %y, <2
|
||||
; CHECK-NEXT: vmov r1, s4
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: cset r0, eq
|
||||
; CHECK-NEXT: tst.w r0, #1
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: csetm r0, ne
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: cset r1, eq
|
||||
; CHECK-NEXT: tst.w r1, #1
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: csetm r1, ne
|
||||
; CHECK-NEXT: vmov q1[2], q1[0], r1, r0
|
||||
; CHECK-NEXT: vmov q1[3], q1[1], r1, r0
|
||||
@ -379,11 +379,11 @@ define arm_aapcs_vfpcc i64 @add_v2i16_v2i64_sext(<2 x i16> %x, <2 x i16> %y, <2
|
||||
; CHECK-NEXT: sxth r3, r3
|
||||
; CHECK-NEXT: cset r0, eq
|
||||
; CHECK-NEXT: smull r2, r3, r3, r2
|
||||
; CHECK-NEXT: tst.w r0, #1
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: csetm r0, ne
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: cset r1, eq
|
||||
; CHECK-NEXT: tst.w r1, #1
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: csetm r1, ne
|
||||
; CHECK-NEXT: vmov q2[2], q2[0], r1, r0
|
||||
; CHECK-NEXT: vmov q2[3], q2[1], r1, r0
|
||||
@ -1489,11 +1489,11 @@ define arm_aapcs_vfpcc i64 @add_v2i8_v2i64_zext(<2 x i8> %x, <2 x i8> %y, <2 x i
|
||||
; CHECK-NEXT: vmov r1, s4
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: cset r0, eq
|
||||
; CHECK-NEXT: tst.w r0, #1
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: csetm r0, ne
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: cset r1, eq
|
||||
; CHECK-NEXT: tst.w r1, #1
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: csetm r1, ne
|
||||
; CHECK-NEXT: vmov q1[2], q1[0], r1, r0
|
||||
; CHECK-NEXT: vmov q1[3], q1[1], r1, r0
|
||||
@ -1529,11 +1529,11 @@ define arm_aapcs_vfpcc i64 @add_v2i8_v2i64_sext(<2 x i8> %x, <2 x i8> %y, <2 x i
|
||||
; CHECK-NEXT: sxtb r3, r3
|
||||
; CHECK-NEXT: cset r0, eq
|
||||
; CHECK-NEXT: smull r2, r3, r3, r2
|
||||
; CHECK-NEXT: tst.w r0, #1
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: csetm r0, ne
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: cset r1, eq
|
||||
; CHECK-NEXT: tst.w r1, #1
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: csetm r1, ne
|
||||
; CHECK-NEXT: vmov q2[2], q2[0], r1, r0
|
||||
; CHECK-NEXT: vmov q2[3], q2[1], r1, r0
|
||||
@ -1589,11 +1589,11 @@ define arm_aapcs_vfpcc i64 @add_v2i64_v2i64(<2 x i64> %x, <2 x i64> %y, <2 x i64
|
||||
; CHECK-NEXT: orrs r0, r1
|
||||
; CHECK-NEXT: vmov r1, s9
|
||||
; CHECK-NEXT: cset r0, eq
|
||||
; CHECK-NEXT: tst.w r0, #1
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: csetm r0, ne
|
||||
; CHECK-NEXT: orrs r1, r2
|
||||
; CHECK-NEXT: cset r1, eq
|
||||
; CHECK-NEXT: tst.w r1, #1
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: csetm r1, ne
|
||||
; CHECK-NEXT: vmov q0[2], q0[0], r1, r0
|
||||
; CHECK-NEXT: vmov q0[3], q0[1], r1, r0
|
||||
@ -1672,11 +1672,11 @@ define arm_aapcs_vfpcc i64 @add_v2i32_v2i64_acc_zext(<2 x i32> %x, <2 x i32> %y,
|
||||
; CHECK-NEXT: vmov r3, s8
|
||||
; CHECK-NEXT: cmp r2, #0
|
||||
; CHECK-NEXT: cset r2, eq
|
||||
; CHECK-NEXT: tst.w r2, #1
|
||||
; CHECK-NEXT: cmp r2, #0
|
||||
; CHECK-NEXT: csetm r2, ne
|
||||
; CHECK-NEXT: cmp r3, #0
|
||||
; CHECK-NEXT: cset r3, eq
|
||||
; CHECK-NEXT: tst.w r3, #1
|
||||
; CHECK-NEXT: cmp r3, #0
|
||||
; CHECK-NEXT: csetm r3, ne
|
||||
; CHECK-NEXT: vmov q0[2], q0[0], r3, r2
|
||||
; CHECK-NEXT: vmov q0[3], q0[1], r3, r2
|
||||
@ -1711,11 +1711,11 @@ define arm_aapcs_vfpcc i64 @add_v2i32_v2i64_acc_sext(<2 x i32> %x, <2 x i32> %y,
|
||||
; CHECK-NEXT: vmov r3, s8
|
||||
; CHECK-NEXT: cmp r2, #0
|
||||
; CHECK-NEXT: cset r2, eq
|
||||
; CHECK-NEXT: tst.w r2, #1
|
||||
; CHECK-NEXT: cmp r2, #0
|
||||
; CHECK-NEXT: csetm r2, ne
|
||||
; CHECK-NEXT: cmp r3, #0
|
||||
; CHECK-NEXT: cset r3, eq
|
||||
; CHECK-NEXT: tst.w r3, #1
|
||||
; CHECK-NEXT: cmp r3, #0
|
||||
; CHECK-NEXT: csetm r3, ne
|
||||
; CHECK-NEXT: vmov q0[2], q0[0], r3, r2
|
||||
; CHECK-NEXT: vmov q0[3], q0[1], r3, r2
|
||||
@ -1938,11 +1938,11 @@ define arm_aapcs_vfpcc i64 @add_v2i16_v2i64_acc_zext(<2 x i16> %x, <2 x i16> %y,
|
||||
; CHECK-NEXT: vmov r3, s4
|
||||
; CHECK-NEXT: cmp r2, #0
|
||||
; CHECK-NEXT: cset r2, eq
|
||||
; CHECK-NEXT: tst.w r2, #1
|
||||
; CHECK-NEXT: cmp r2, #0
|
||||
; CHECK-NEXT: csetm r2, ne
|
||||
; CHECK-NEXT: cmp r3, #0
|
||||
; CHECK-NEXT: cset r3, eq
|
||||
; CHECK-NEXT: tst.w r3, #1
|
||||
; CHECK-NEXT: cmp r3, #0
|
||||
; CHECK-NEXT: csetm r3, ne
|
||||
; CHECK-NEXT: vmov q1[2], q1[0], r3, r2
|
||||
; CHECK-NEXT: vmov q1[3], q1[1], r3, r2
|
||||
@ -1978,11 +1978,11 @@ define arm_aapcs_vfpcc i64 @add_v2i16_v2i64_acc_sext(<2 x i16> %x, <2 x i16> %y,
|
||||
; CHECK-NEXT: vmov r3, s8
|
||||
; CHECK-NEXT: cmp r2, #0
|
||||
; CHECK-NEXT: cset r2, eq
|
||||
; CHECK-NEXT: tst.w r2, #1
|
||||
; CHECK-NEXT: cmp r2, #0
|
||||
; CHECK-NEXT: csetm r2, ne
|
||||
; CHECK-NEXT: cmp r3, #0
|
||||
; CHECK-NEXT: cset r3, eq
|
||||
; CHECK-NEXT: tst.w r3, #1
|
||||
; CHECK-NEXT: cmp r3, #0
|
||||
; CHECK-NEXT: csetm r3, ne
|
||||
; CHECK-NEXT: vmov q2[2], q2[0], r3, r2
|
||||
; CHECK-NEXT: vmov q2[3], q2[1], r3, r2
|
||||
@ -2892,11 +2892,11 @@ define arm_aapcs_vfpcc i64 @add_v2i8_v2i64_acc_zext(<2 x i8> %x, <2 x i8> %y, <2
|
||||
; CHECK-NEXT: vmov r3, s4
|
||||
; CHECK-NEXT: cmp r2, #0
|
||||
; CHECK-NEXT: cset r2, eq
|
||||
; CHECK-NEXT: tst.w r2, #1
|
||||
; CHECK-NEXT: cmp r2, #0
|
||||
; CHECK-NEXT: csetm r2, ne
|
||||
; CHECK-NEXT: cmp r3, #0
|
||||
; CHECK-NEXT: cset r3, eq
|
||||
; CHECK-NEXT: tst.w r3, #1
|
||||
; CHECK-NEXT: cmp r3, #0
|
||||
; CHECK-NEXT: csetm r3, ne
|
||||
; CHECK-NEXT: vmov q1[2], q1[0], r3, r2
|
||||
; CHECK-NEXT: vmov q1[3], q1[1], r3, r2
|
||||
@ -2932,11 +2932,11 @@ define arm_aapcs_vfpcc i64 @add_v2i8_v2i64_acc_sext(<2 x i8> %x, <2 x i8> %y, <2
|
||||
; CHECK-NEXT: vmov r3, s8
|
||||
; CHECK-NEXT: cmp r2, #0
|
||||
; CHECK-NEXT: cset r2, eq
|
||||
; CHECK-NEXT: tst.w r2, #1
|
||||
; CHECK-NEXT: cmp r2, #0
|
||||
; CHECK-NEXT: csetm r2, ne
|
||||
; CHECK-NEXT: cmp r3, #0
|
||||
; CHECK-NEXT: cset r3, eq
|
||||
; CHECK-NEXT: tst.w r3, #1
|
||||
; CHECK-NEXT: cmp r3, #0
|
||||
; CHECK-NEXT: csetm r3, ne
|
||||
; CHECK-NEXT: vmov q2[2], q2[0], r3, r2
|
||||
; CHECK-NEXT: vmov q2[3], q2[1], r3, r2
|
||||
@ -3000,11 +3000,11 @@ define arm_aapcs_vfpcc i64 @add_v2i64_v2i64_acc(<2 x i64> %x, <2 x i64> %y, <2 x
|
||||
; CHECK-NEXT: orrs r2, r3
|
||||
; CHECK-NEXT: vmov r3, s9
|
||||
; CHECK-NEXT: cset r2, eq
|
||||
; CHECK-NEXT: tst.w r2, #1
|
||||
; CHECK-NEXT: cmp r2, #0
|
||||
; CHECK-NEXT: csetm r2, ne
|
||||
; CHECK-NEXT: orrs r3, r7
|
||||
; CHECK-NEXT: cset r3, eq
|
||||
; CHECK-NEXT: tst.w r3, #1
|
||||
; CHECK-NEXT: cmp r3, #0
|
||||
; CHECK-NEXT: csetm r3, ne
|
||||
; CHECK-NEXT: vmov q0[2], q0[0], r3, r2
|
||||
; CHECK-NEXT: vmov q0[3], q0[1], r3, r2
|
||||
|
||||
@ -521,7 +521,6 @@ define arm_aapcs_vfpcc <4 x i32> @i1and_vmov(<4 x i32> %a, <4 x i32> %b, i32 %c)
|
||||
; CHECKLE-NEXT: cmp r0, #0
|
||||
; CHECKLE-NEXT: mov.w r1, #15
|
||||
; CHECKLE-NEXT: cset r0, eq
|
||||
; CHECKLE-NEXT: and r0, r0, #1
|
||||
; CHECKLE-NEXT: rsbs r0, r0, #0
|
||||
; CHECKLE-NEXT: ands r0, r1
|
||||
; CHECKLE-NEXT: vmsr p0, r0
|
||||
@ -534,9 +533,8 @@ define arm_aapcs_vfpcc <4 x i32> @i1and_vmov(<4 x i32> %a, <4 x i32> %b, i32 %c)
|
||||
; CHECKBE-NEXT: mov.w r1, #15
|
||||
; CHECKBE-NEXT: cset r0, eq
|
||||
; CHECKBE-NEXT: vrev64.32 q2, q1
|
||||
; CHECKBE-NEXT: and r0, r0, #1
|
||||
; CHECKBE-NEXT: vrev64.32 q1, q0
|
||||
; CHECKBE-NEXT: rsbs r0, r0, #0
|
||||
; CHECKBE-NEXT: vrev64.32 q1, q0
|
||||
; CHECKBE-NEXT: ands r0, r1
|
||||
; CHECKBE-NEXT: vmsr p0, r0
|
||||
; CHECKBE-NEXT: vpsel q1, q1, q2
|
||||
@ -557,7 +555,6 @@ define arm_aapcs_vfpcc <4 x i32> @i1or_vmov(<4 x i32> %a, <4 x i32> %b, i32 %c)
|
||||
; CHECKLE-NEXT: cmp r0, #0
|
||||
; CHECKLE-NEXT: mov.w r1, #15
|
||||
; CHECKLE-NEXT: cset r0, eq
|
||||
; CHECKLE-NEXT: and r0, r0, #1
|
||||
; CHECKLE-NEXT: rsbs r0, r0, #0
|
||||
; CHECKLE-NEXT: orrs r0, r1
|
||||
; CHECKLE-NEXT: vmsr p0, r0
|
||||
@ -570,9 +567,8 @@ define arm_aapcs_vfpcc <4 x i32> @i1or_vmov(<4 x i32> %a, <4 x i32> %b, i32 %c)
|
||||
; CHECKBE-NEXT: mov.w r1, #15
|
||||
; CHECKBE-NEXT: cset r0, eq
|
||||
; CHECKBE-NEXT: vrev64.32 q2, q1
|
||||
; CHECKBE-NEXT: and r0, r0, #1
|
||||
; CHECKBE-NEXT: vrev64.32 q1, q0
|
||||
; CHECKBE-NEXT: rsbs r0, r0, #0
|
||||
; CHECKBE-NEXT: vrev64.32 q1, q0
|
||||
; CHECKBE-NEXT: orrs r0, r1
|
||||
; CHECKBE-NEXT: vmsr p0, r0
|
||||
; CHECKBE-NEXT: vpsel q1, q1, q2
|
||||
|
||||
150
unittests/Target/ARM/ARMSelectionDAGTest.cpp
Normal file
150
unittests/Target/ARM/ARMSelectionDAGTest.cpp
Normal file
@ -0,0 +1,150 @@
|
||||
//===- llvm/unittest/Target/ARM/ARMSelectionDAGTest.cpp -------------------===//
|
||||
//
|
||||
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
|
||||
// See https://llvm.org/LICENSE.txt for license information.
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#include "ARMISelLowering.h"
|
||||
#include "llvm/Analysis/OptimizationRemarkEmitter.h"
|
||||
#include "llvm/AsmParser/Parser.h"
|
||||
#include "llvm/CodeGen/MachineModuleInfo.h"
|
||||
#include "llvm/CodeGen/SelectionDAG.h"
|
||||
#include "llvm/CodeGen/TargetLowering.h"
|
||||
#include "llvm/Support/KnownBits.h"
|
||||
#include "llvm/Support/SourceMgr.h"
|
||||
#include "llvm/Support/TargetRegistry.h"
|
||||
#include "llvm/Support/TargetSelect.h"
|
||||
#include "llvm/Target/TargetMachine.h"
|
||||
#include "gtest/gtest.h"
|
||||
|
||||
namespace llvm {
|
||||
|
||||
class ARMSelectionDAGTest : public testing::Test {
|
||||
protected:
|
||||
static void SetUpTestCase() {
|
||||
InitializeAllTargets();
|
||||
InitializeAllTargetMCs();
|
||||
}
|
||||
|
||||
void SetUp() override {
|
||||
StringRef Assembly = "define void @f() { ret void }";
|
||||
|
||||
Triple TargetTriple("thumbv8.1m.main-none-eabi");
|
||||
std::string Error;
|
||||
const Target *T = TargetRegistry::lookupTarget("", TargetTriple, Error);
|
||||
if (!T)
|
||||
return;
|
||||
|
||||
TargetOptions Options;
|
||||
TM = std::unique_ptr<LLVMTargetMachine>(static_cast<LLVMTargetMachine *>(
|
||||
T->createTargetMachine("ARM", "", "+mve.fp", Options, None, None,
|
||||
CodeGenOpt::Aggressive)));
|
||||
if (!TM)
|
||||
return;
|
||||
|
||||
SMDiagnostic SMError;
|
||||
M = parseAssemblyString(Assembly, SMError, Context);
|
||||
if (!M)
|
||||
report_fatal_error(SMError.getMessage());
|
||||
M->setDataLayout(TM->createDataLayout());
|
||||
|
||||
F = M->getFunction("f");
|
||||
if (!F)
|
||||
report_fatal_error("F?");
|
||||
|
||||
MachineModuleInfo MMI(TM.get());
|
||||
|
||||
MF = std::make_unique<MachineFunction>(*F, *TM, *TM->getSubtargetImpl(*F),
|
||||
0, MMI);
|
||||
|
||||
DAG = std::make_unique<SelectionDAG>(*TM, CodeGenOpt::None);
|
||||
if (!DAG)
|
||||
report_fatal_error("DAG?");
|
||||
OptimizationRemarkEmitter ORE(F);
|
||||
DAG->init(*MF, ORE, nullptr, nullptr, nullptr, nullptr, nullptr);
|
||||
}
|
||||
|
||||
TargetLoweringBase::LegalizeTypeAction getTypeAction(EVT VT) {
|
||||
return DAG->getTargetLoweringInfo().getTypeAction(Context, VT);
|
||||
}
|
||||
|
||||
EVT getTypeToTransformTo(EVT VT) {
|
||||
return DAG->getTargetLoweringInfo().getTypeToTransformTo(Context, VT);
|
||||
}
|
||||
|
||||
LLVMContext Context;
|
||||
std::unique_ptr<LLVMTargetMachine> TM;
|
||||
std::unique_ptr<Module> M;
|
||||
Function *F;
|
||||
std::unique_ptr<MachineFunction> MF;
|
||||
std::unique_ptr<SelectionDAG> DAG;
|
||||
};
|
||||
|
||||
TEST_F(ARMSelectionDAGTest, computeKnownBits_CSINC) {
|
||||
if (!TM)
|
||||
return;
|
||||
SDLoc DL;
|
||||
SDValue Zero = DAG->getConstant(0, DL, MVT::i32);
|
||||
SDValue One = DAG->getConstant(1, DL, MVT::i32);
|
||||
SDValue ARMcc = DAG->getConstant(8, DL, MVT::i32);
|
||||
SDValue Cmp = DAG->getNode(ARMISD::CMP, DL, MVT::Glue, Zero, One);
|
||||
|
||||
SDValue Op0 =
|
||||
DAG->getNode(ARMISD::CSINC, DL, MVT::i32, Zero, Zero, ARMcc, Cmp);
|
||||
KnownBits Known = DAG->computeKnownBits(Op0);
|
||||
EXPECT_EQ(Known.Zero, 0xfffffffe);
|
||||
EXPECT_EQ(Known.One, 0x0);
|
||||
|
||||
SDValue Op1 = DAG->getNode(ARMISD::CSINC, DL, MVT::i32, One, One, ARMcc, Cmp);
|
||||
Known = DAG->computeKnownBits(Op1);
|
||||
EXPECT_EQ(Known.Zero, 0xfffffffc);
|
||||
EXPECT_EQ(Known.One, 0x0);
|
||||
}
|
||||
|
||||
TEST_F(ARMSelectionDAGTest, computeKnownBits_CSINV) {
|
||||
if (!TM)
|
||||
return;
|
||||
SDLoc DL;
|
||||
SDValue Zero = DAG->getConstant(0, DL, MVT::i32);
|
||||
SDValue One = DAG->getConstant(1, DL, MVT::i32);
|
||||
SDValue ARMcc = DAG->getConstant(8, DL, MVT::i32);
|
||||
SDValue Cmp = DAG->getNode(ARMISD::CMP, DL, MVT::Glue, Zero, One);
|
||||
|
||||
SDValue Op0 =
|
||||
DAG->getNode(ARMISD::CSINV, DL, MVT::i32, Zero, Zero, ARMcc, Cmp);
|
||||
KnownBits Known = DAG->computeKnownBits(Op0);
|
||||
EXPECT_EQ(Known.Zero, 0x0);
|
||||
EXPECT_EQ(Known.One, 0x0);
|
||||
|
||||
SDValue Op1 =
|
||||
DAG->getNode(ARMISD::CSINV, DL, MVT::i32, Zero, One, ARMcc, Cmp);
|
||||
Known = DAG->computeKnownBits(Op1);
|
||||
EXPECT_EQ(Known.Zero, 0x1);
|
||||
EXPECT_EQ(Known.One, 0x0);
|
||||
}
|
||||
|
||||
TEST_F(ARMSelectionDAGTest, computeKnownBits_CSNEG) {
|
||||
if (!TM)
|
||||
return;
|
||||
SDLoc DL;
|
||||
SDValue Zero = DAG->getConstant(0, DL, MVT::i32);
|
||||
SDValue One = DAG->getConstant(1, DL, MVT::i32);
|
||||
SDValue ARMcc = DAG->getConstant(8, DL, MVT::i32);
|
||||
SDValue Cmp = DAG->getNode(ARMISD::CMP, DL, MVT::Glue, Zero, One);
|
||||
|
||||
SDValue Op0 =
|
||||
DAG->getNode(ARMISD::CSNEG, DL, MVT::i32, Zero, Zero, ARMcc, Cmp);
|
||||
KnownBits Known = DAG->computeKnownBits(Op0);
|
||||
EXPECT_EQ(Known.Zero, 0xffffffff);
|
||||
EXPECT_EQ(Known.One, 0x0);
|
||||
|
||||
SDValue Op1 =
|
||||
DAG->getNode(ARMISD::CSNEG, DL, MVT::i32, One, Zero, ARMcc, Cmp);
|
||||
Known = DAG->computeKnownBits(Op1);
|
||||
EXPECT_EQ(Known.Zero, 0xfffffffe);
|
||||
EXPECT_EQ(Known.One, 0x0);
|
||||
}
|
||||
|
||||
} // end namespace llvm
|
||||
@ -4,6 +4,7 @@ include_directories(
|
||||
)
|
||||
|
||||
set(LLVM_LINK_COMPONENTS
|
||||
${LLVM_TARGETS_TO_BUILD}
|
||||
ARMCodeGen
|
||||
ARMDesc
|
||||
ARMInfo
|
||||
@ -16,5 +17,6 @@ set(LLVM_LINK_COMPONENTS
|
||||
)
|
||||
|
||||
add_llvm_target_unittest(ARMTests
|
||||
ARMSelectionDAGTest.cpp
|
||||
MachineInstrTest.cpp
|
||||
)
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user