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[RISCV] Fix inaccurate annotations on PseudoBRIND

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PseudoBRIND had seemingly inherited incorrect annotations denoting it as
a call instruction and that it defines X1/ra. This caused excess
save/restore code to be emitted for ra.

Differential Revision: https://reviews.llvm.org/D86286
This commit is contained in:
lewis-revill 2020-08-21 10:47:54 +01:00
parent afddfeaf4a
commit fd94b72c2e
4 changed files with 6 additions and 23 deletions
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1
lib/Target/RISCV/RISCVInstrInfo.td
View File

@ -946,7 +946,6 @@ let isBarrier = 1, isBranch = 1, isTerminator = 1 in
def PseudoBR : Pseudo<(outs), (ins simm21_lsb0_jal:$imm20), [(br bb:$imm20)]>,
PseudoInstExpansion<(JAL X0, simm21_lsb0_jal:$imm20)>;
let isCall = 1, Defs=[X1] in
let isBarrier = 1, isBranch = 1, isIndirectBranch = 1, isTerminator = 1 in
def PseudoBRIND : Pseudo<(outs), (ins GPR:$rs1, simm12:$imm12), []>,
PseudoInstExpansion<(JALR X0, GPR:$rs1, simm12:$imm12)>;

4
test/CodeGen/RISCV/blockaddress.ll
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@ -7,8 +7,6 @@
define void @test_blockaddress() nounwind {
; RV32I-LABEL: test_blockaddress:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: lui a0, %hi(addr)
; RV32I-NEXT: lui a1, %hi(.Ltmp0)
; RV32I-NEXT: addi a1, a1, %lo(.Ltmp0)
@ -17,8 +15,6 @@ define void @test_blockaddress() nounwind {
; RV32I-NEXT: jr a0
; RV32I-NEXT: .Ltmp0: # Block address taken
; RV32I-NEXT: .LBB0_1: # %block
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
store volatile i8* blockaddress(@test_blockaddress, %block), i8** @addr
%val = load volatile i8*, i8** @addr

16
test/CodeGen/RISCV/codemodel-lowering.ll
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@ -58,7 +58,6 @@ define signext i32 @lower_blockaddress_displ(i32 signext %w) nounwind {
; RV32I-SMALL-LABEL: lower_blockaddress_displ:
; RV32I-SMALL: # %bb.0: # %entry
; RV32I-SMALL-NEXT: addi sp, sp, -16
; RV32I-SMALL-NEXT: sw ra, 12(sp)
; RV32I-SMALL-NEXT: lui a1, %hi(.Ltmp0)
; RV32I-SMALL-NEXT: addi a1, a1, %lo(.Ltmp0)
; RV32I-SMALL-NEXT: addi a2, zero, 101
@ -70,22 +69,20 @@ define signext i32 @lower_blockaddress_displ(i32 signext %w) nounwind {
; RV32I-SMALL-NEXT: .Ltmp0: # Block address taken
; RV32I-SMALL-NEXT: .LBB2_2: # %return
; RV32I-SMALL-NEXT: addi a0, zero, 4
; RV32I-SMALL-NEXT: j .LBB2_4
; RV32I-SMALL-NEXT: addi sp, sp, 16
; RV32I-SMALL-NEXT: ret
; RV32I-SMALL-NEXT: .LBB2_3: # %return.clone
; RV32I-SMALL-NEXT: addi a0, zero, 3
; RV32I-SMALL-NEXT: .LBB2_4: # %.split
; RV32I-SMALL-NEXT: lw ra, 12(sp)
; RV32I-SMALL-NEXT: addi sp, sp, 16
; RV32I-SMALL-NEXT: ret
;
; RV32I-MEDIUM-LABEL: lower_blockaddress_displ:
; RV32I-MEDIUM: # %bb.0: # %entry
; RV32I-MEDIUM-NEXT: addi sp, sp, -16
; RV32I-MEDIUM-NEXT: sw ra, 12(sp)
; RV32I-MEDIUM-NEXT: .LBB2_5: # %entry
; RV32I-MEDIUM-NEXT: .LBB2_4: # %entry
; RV32I-MEDIUM-NEXT: # Label of block must be emitted
; RV32I-MEDIUM-NEXT: auipc a1, %pcrel_hi(.Ltmp0)
; RV32I-MEDIUM-NEXT: addi a1, a1, %pcrel_lo(.LBB2_5)
; RV32I-MEDIUM-NEXT: addi a1, a1, %pcrel_lo(.LBB2_4)
; RV32I-MEDIUM-NEXT: addi a2, zero, 101
; RV32I-MEDIUM-NEXT: sw a1, 8(sp)
; RV32I-MEDIUM-NEXT: blt a0, a2, .LBB2_3
@ -95,11 +92,10 @@ define signext i32 @lower_blockaddress_displ(i32 signext %w) nounwind {
; RV32I-MEDIUM-NEXT: .Ltmp0: # Block address taken
; RV32I-MEDIUM-NEXT: .LBB2_2: # %return
; RV32I-MEDIUM-NEXT: addi a0, zero, 4
; RV32I-MEDIUM-NEXT: j .LBB2_4
; RV32I-MEDIUM-NEXT: addi sp, sp, 16
; RV32I-MEDIUM-NEXT: ret
; RV32I-MEDIUM-NEXT: .LBB2_3: # %return.clone
; RV32I-MEDIUM-NEXT: addi a0, zero, 3
; RV32I-MEDIUM-NEXT: .LBB2_4: # %.split
; RV32I-MEDIUM-NEXT: lw ra, 12(sp)
; RV32I-MEDIUM-NEXT: addi sp, sp, 16
; RV32I-MEDIUM-NEXT: ret
entry:

8
test/CodeGen/RISCV/indirectbr.ll
View File

@ -5,13 +5,9 @@
define i32 @indirectbr(i8* %target) nounwind {
; RV32I-LABEL: indirectbr:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: jr a0
; RV32I-NEXT: .LBB0_1: # %test_label
; RV32I-NEXT: mv a0, zero
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
indirectbr i8* %target, [label %test_label]
test_label:
@ -23,13 +19,9 @@ ret:
define i32 @indirectbr_with_offset(i8* %a) nounwind {
; RV32I-LABEL: indirectbr_with_offset:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: jr 1380(a0)
; RV32I-NEXT: .LBB1_1: # %test_label
; RV32I-NEXT: mv a0, zero
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%target = getelementptr inbounds i8, i8* %a, i32 1380
indirectbr i8* %target, [label %test_label]