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[X86] Make one of the FMA3 commuting methods static. Remove a call to isFMA3 just to get the IsIntrisic flag, instead get it during the first call and pass it along. NFC
llvm-svn: 276520
This commit is contained in:
Craig Topper
parent
c04f0812ca
commit
fdc847eeff
@ -3154,9 +3154,8 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
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/// the function. It is set to true if the given instruction has FMA3 opcode
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/// that is used for lowering of scalar FMA intrinsics, and it is set to false
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/// otherwise.
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static bool isFMA3(unsigned Opcode, bool *IsIntrinsic = nullptr) {
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if (IsIntrinsic)
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*IsIntrinsic = false;
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static bool isFMA3(unsigned Opcode, bool &IsIntrinsic) {
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IsIntrinsic = false;
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switch (Opcode) {
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case X86::VFMADDSDr132r: case X86::VFMADDSDr132m:
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@ -3291,8 +3290,7 @@ static bool isFMA3(unsigned Opcode, bool *IsIntrinsic = nullptr) {
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case X86::VFNMADDSSr231r_Int: case X86::VFNMADDSSr231m_Int:
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case X86::VFNMSUBSDr231r_Int: case X86::VFNMSUBSDr231m_Int:
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case X86::VFNMSUBSSr231r_Int: case X86::VFNMSUBSSr231m_Int:
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if (IsIntrinsic)
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*IsIntrinsic = true;
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IsIntrinsic = true;
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return true;
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default:
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return false;
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@ -3300,6 +3298,201 @@ static bool isFMA3(unsigned Opcode, bool *IsIntrinsic = nullptr) {
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llvm_unreachable("Opcode not handled by the switch");
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}
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/// Returns an adjusted FMA opcode that must be used in FMA instruction that
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/// performs the same computations as the given MI but which has the operands
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/// \p SrcOpIdx1 and \p SrcOpIdx2 commuted.
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/// It may return 0 if it is unsafe to commute the operands.
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///
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/// The returned FMA opcode may differ from the opcode in the given \p MI.
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/// For example, commuting the operands #1 and #3 in the following FMA
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/// FMA213 #1, #2, #3
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/// results into instruction with adjusted opcode:
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/// FMA231 #3, #2, #1
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static unsigned getFMA3OpcodeToCommuteOperands(unsigned Opc,
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bool IsIntrinOpcode,
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unsigned SrcOpIdx1,
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unsigned SrcOpIdx2) {
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// Define the array that holds FMA opcodes in groups
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// of 3 opcodes(132, 213, 231) in each group.
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static const uint16_t RegularOpcodeGroups[][3] = {
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{ X86::VFMADDSSr132r, X86::VFMADDSSr213r, X86::VFMADDSSr231r },
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{ X86::VFMADDSDr132r, X86::VFMADDSDr213r, X86::VFMADDSDr231r },
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{ X86::VFMADDPSr132r, X86::VFMADDPSr213r, X86::VFMADDPSr231r },
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{ X86::VFMADDPDr132r, X86::VFMADDPDr213r, X86::VFMADDPDr231r },
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{ X86::VFMADDPSr132rY, X86::VFMADDPSr213rY, X86::VFMADDPSr231rY },
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{ X86::VFMADDPDr132rY, X86::VFMADDPDr213rY, X86::VFMADDPDr231rY },
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{ X86::VFMADDSSr132m, X86::VFMADDSSr213m, X86::VFMADDSSr231m },
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{ X86::VFMADDSDr132m, X86::VFMADDSDr213m, X86::VFMADDSDr231m },
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{ X86::VFMADDPSr132m, X86::VFMADDPSr213m, X86::VFMADDPSr231m },
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{ X86::VFMADDPDr132m, X86::VFMADDPDr213m, X86::VFMADDPDr231m },
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{ X86::VFMADDPSr132mY, X86::VFMADDPSr213mY, X86::VFMADDPSr231mY },
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{ X86::VFMADDPDr132mY, X86::VFMADDPDr213mY, X86::VFMADDPDr231mY },
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{ X86::VFMSUBSSr132r, X86::VFMSUBSSr213r, X86::VFMSUBSSr231r },
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{ X86::VFMSUBSDr132r, X86::VFMSUBSDr213r, X86::VFMSUBSDr231r },
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{ X86::VFMSUBPSr132r, X86::VFMSUBPSr213r, X86::VFMSUBPSr231r },
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{ X86::VFMSUBPDr132r, X86::VFMSUBPDr213r, X86::VFMSUBPDr231r },
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{ X86::VFMSUBPSr132rY, X86::VFMSUBPSr213rY, X86::VFMSUBPSr231rY },
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{ X86::VFMSUBPDr132rY, X86::VFMSUBPDr213rY, X86::VFMSUBPDr231rY },
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{ X86::VFMSUBSSr132m, X86::VFMSUBSSr213m, X86::VFMSUBSSr231m },
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{ X86::VFMSUBSDr132m, X86::VFMSUBSDr213m, X86::VFMSUBSDr231m },
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{ X86::VFMSUBPSr132m, X86::VFMSUBPSr213m, X86::VFMSUBPSr231m },
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{ X86::VFMSUBPDr132m, X86::VFMSUBPDr213m, X86::VFMSUBPDr231m },
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{ X86::VFMSUBPSr132mY, X86::VFMSUBPSr213mY, X86::VFMSUBPSr231mY },
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{ X86::VFMSUBPDr132mY, X86::VFMSUBPDr213mY, X86::VFMSUBPDr231mY },
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{ X86::VFNMADDSSr132r, X86::VFNMADDSSr213r, X86::VFNMADDSSr231r },
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{ X86::VFNMADDSDr132r, X86::VFNMADDSDr213r, X86::VFNMADDSDr231r },
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{ X86::VFNMADDPSr132r, X86::VFNMADDPSr213r, X86::VFNMADDPSr231r },
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{ X86::VFNMADDPDr132r, X86::VFNMADDPDr213r, X86::VFNMADDPDr231r },
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{ X86::VFNMADDPSr132rY, X86::VFNMADDPSr213rY, X86::VFNMADDPSr231rY },
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{ X86::VFNMADDPDr132rY, X86::VFNMADDPDr213rY, X86::VFNMADDPDr231rY },
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{ X86::VFNMADDSSr132m, X86::VFNMADDSSr213m, X86::VFNMADDSSr231m },
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{ X86::VFNMADDSDr132m, X86::VFNMADDSDr213m, X86::VFNMADDSDr231m },
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{ X86::VFNMADDPSr132m, X86::VFNMADDPSr213m, X86::VFNMADDPSr231m },
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{ X86::VFNMADDPDr132m, X86::VFNMADDPDr213m, X86::VFNMADDPDr231m },
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{ X86::VFNMADDPSr132mY, X86::VFNMADDPSr213mY, X86::VFNMADDPSr231mY },
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{ X86::VFNMADDPDr132mY, X86::VFNMADDPDr213mY, X86::VFNMADDPDr231mY },
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{ X86::VFNMSUBSSr132r, X86::VFNMSUBSSr213r, X86::VFNMSUBSSr231r },
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{ X86::VFNMSUBSDr132r, X86::VFNMSUBSDr213r, X86::VFNMSUBSDr231r },
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{ X86::VFNMSUBPSr132r, X86::VFNMSUBPSr213r, X86::VFNMSUBPSr231r },
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{ X86::VFNMSUBPDr132r, X86::VFNMSUBPDr213r, X86::VFNMSUBPDr231r },
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{ X86::VFNMSUBPSr132rY, X86::VFNMSUBPSr213rY, X86::VFNMSUBPSr231rY },
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{ X86::VFNMSUBPDr132rY, X86::VFNMSUBPDr213rY, X86::VFNMSUBPDr231rY },
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{ X86::VFNMSUBSSr132m, X86::VFNMSUBSSr213m, X86::VFNMSUBSSr231m },
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{ X86::VFNMSUBSDr132m, X86::VFNMSUBSDr213m, X86::VFNMSUBSDr231m },
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{ X86::VFNMSUBPSr132m, X86::VFNMSUBPSr213m, X86::VFNMSUBPSr231m },
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{ X86::VFNMSUBPDr132m, X86::VFNMSUBPDr213m, X86::VFNMSUBPDr231m },
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{ X86::VFNMSUBPSr132mY, X86::VFNMSUBPSr213mY, X86::VFNMSUBPSr231mY },
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{ X86::VFNMSUBPDr132mY, X86::VFNMSUBPDr213mY, X86::VFNMSUBPDr231mY },
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{ X86::VFMADDSUBPSr132r, X86::VFMADDSUBPSr213r, X86::VFMADDSUBPSr231r },
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{ X86::VFMADDSUBPDr132r, X86::VFMADDSUBPDr213r, X86::VFMADDSUBPDr231r },
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{ X86::VFMADDSUBPSr132rY, X86::VFMADDSUBPSr213rY, X86::VFMADDSUBPSr231rY },
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{ X86::VFMADDSUBPDr132rY, X86::VFMADDSUBPDr213rY, X86::VFMADDSUBPDr231rY },
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{ X86::VFMADDSUBPSr132m, X86::VFMADDSUBPSr213m, X86::VFMADDSUBPSr231m },
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{ X86::VFMADDSUBPDr132m, X86::VFMADDSUBPDr213m, X86::VFMADDSUBPDr231m },
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{ X86::VFMADDSUBPSr132mY, X86::VFMADDSUBPSr213mY, X86::VFMADDSUBPSr231mY },
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{ X86::VFMADDSUBPDr132mY, X86::VFMADDSUBPDr213mY, X86::VFMADDSUBPDr231mY },
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{ X86::VFMSUBADDPSr132r, X86::VFMSUBADDPSr213r, X86::VFMSUBADDPSr231r },
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{ X86::VFMSUBADDPDr132r, X86::VFMSUBADDPDr213r, X86::VFMSUBADDPDr231r },
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{ X86::VFMSUBADDPSr132rY, X86::VFMSUBADDPSr213rY, X86::VFMSUBADDPSr231rY },
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{ X86::VFMSUBADDPDr132rY, X86::VFMSUBADDPDr213rY, X86::VFMSUBADDPDr231rY },
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{ X86::VFMSUBADDPSr132m, X86::VFMSUBADDPSr213m, X86::VFMSUBADDPSr231m },
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{ X86::VFMSUBADDPDr132m, X86::VFMSUBADDPDr213m, X86::VFMSUBADDPDr231m },
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{ X86::VFMSUBADDPSr132mY, X86::VFMSUBADDPSr213mY, X86::VFMSUBADDPSr231mY },
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{ X86::VFMSUBADDPDr132mY, X86::VFMSUBADDPDr213mY, X86::VFMSUBADDPDr231mY }
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};
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// Define the array that holds FMA*_Int opcodes in groups
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// of 3 opcodes(132, 213, 231) in each group.
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static const uint16_t IntrinOpcodeGroups[][3] = {
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{ X86::VFMADDSSr132r_Int, X86::VFMADDSSr213r_Int, X86::VFMADDSSr231r_Int },
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{ X86::VFMADDSDr132r_Int, X86::VFMADDSDr213r_Int, X86::VFMADDSDr231r_Int },
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{ X86::VFMADDSSr132m_Int, X86::VFMADDSSr213m_Int, X86::VFMADDSSr231m_Int },
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{ X86::VFMADDSDr132m_Int, X86::VFMADDSDr213m_Int, X86::VFMADDSDr231m_Int },
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{ X86::VFMSUBSSr132r_Int, X86::VFMSUBSSr213r_Int, X86::VFMSUBSSr231r_Int },
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{ X86::VFMSUBSDr132r_Int, X86::VFMSUBSDr213r_Int, X86::VFMSUBSDr231r_Int },
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{ X86::VFMSUBSSr132m_Int, X86::VFMSUBSSr213m_Int, X86::VFMSUBSSr231m_Int },
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{ X86::VFMSUBSDr132m_Int, X86::VFMSUBSDr213m_Int, X86::VFMSUBSDr231m_Int },
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{ X86::VFNMADDSSr132r_Int, X86::VFNMADDSSr213r_Int, X86::VFNMADDSSr231r_Int },
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{ X86::VFNMADDSDr132r_Int, X86::VFNMADDSDr213r_Int, X86::VFNMADDSDr231r_Int },
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{ X86::VFNMADDSSr132m_Int, X86::VFNMADDSSr213m_Int, X86::VFNMADDSSr231m_Int },
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{ X86::VFNMADDSDr132m_Int, X86::VFNMADDSDr213m_Int, X86::VFNMADDSDr231m_Int },
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{ X86::VFNMSUBSSr132r_Int, X86::VFNMSUBSSr213r_Int, X86::VFNMSUBSSr231r_Int },
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{ X86::VFNMSUBSDr132r_Int, X86::VFNMSUBSDr213r_Int, X86::VFNMSUBSDr231r_Int },
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{ X86::VFNMSUBSSr132m_Int, X86::VFNMSUBSSr213m_Int, X86::VFNMSUBSSr231m_Int },
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{ X86::VFNMSUBSDr132m_Int, X86::VFNMSUBSDr213m_Int, X86::VFNMSUBSDr231m_Int },
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};
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const unsigned Form132Index = 0;
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const unsigned Form213Index = 1;
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const unsigned Form231Index = 2;
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const unsigned FormsNum = 3;
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size_t GroupsNum;
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const uint16_t (*OpcodeGroups)[3];
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if (IsIntrinOpcode) {
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GroupsNum = array_lengthof(IntrinOpcodeGroups);
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OpcodeGroups = IntrinOpcodeGroups;
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} else {
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GroupsNum = array_lengthof(RegularOpcodeGroups);
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OpcodeGroups = RegularOpcodeGroups;
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}
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const uint16_t *FoundOpcodesGroup = nullptr;
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size_t FormIndex;
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// Look for the input opcode in the corresponding opcodes table.
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for (size_t GroupIndex = 0; GroupIndex < GroupsNum && !FoundOpcodesGroup;
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++GroupIndex) {
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for (FormIndex = 0; FormIndex < FormsNum; ++FormIndex) {
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if (OpcodeGroups[GroupIndex][FormIndex] == Opc) {
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FoundOpcodesGroup = OpcodeGroups[GroupIndex];
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break;
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}
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}
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}
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// The input opcode does not match with any of the opcodes from the tables.
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// The unsupported FMA opcode must be added to one of the two opcode groups
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// defined above.
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assert(FoundOpcodesGroup != nullptr && "Unexpected FMA3 opcode");
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// Put the lowest index to SrcOpIdx1 to simplify the checks below.
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if (SrcOpIdx1 > SrcOpIdx2)
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std::swap(SrcOpIdx1, SrcOpIdx2);
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// TODO: Commuting the 1st operand of FMA*_Int requires some additional
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// analysis. The commute optimization is legal only if all users of FMA*_Int
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// use only the lowest element of the FMA*_Int instruction. Such analysis are
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// not implemented yet. So, just return 0 in that case.
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// When such analysis are available this place will be the right place for
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// calling it.
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if (IsIntrinOpcode && SrcOpIdx1 == 1)
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return 0;
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unsigned Case;
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if (SrcOpIdx1 == 1 && SrcOpIdx2 == 2)
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Case = 0;
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else if (SrcOpIdx1 == 1 && SrcOpIdx2 == 3)
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Case = 1;
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else if (SrcOpIdx1 == 2 && SrcOpIdx2 == 3)
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Case = 2;
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else
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return 0;
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// Define the FMA forms mapping array that helps to map input FMA form
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// to output FMA form to preserve the operation semantics after
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// commuting the operands.
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static const unsigned FormMapping[][3] = {
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// 0: SrcOpIdx1 == 1 && SrcOpIdx2 == 2;
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// FMA132 A, C, b; ==> FMA231 C, A, b;
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// FMA213 B, A, c; ==> FMA213 A, B, c;
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// FMA231 C, A, b; ==> FMA132 A, C, b;
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{ Form231Index, Form213Index, Form132Index },
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// 1: SrcOpIdx1 == 1 && SrcOpIdx2 == 3;
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// FMA132 A, c, B; ==> FMA132 B, c, A;
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// FMA213 B, a, C; ==> FMA231 C, a, B;
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// FMA231 C, a, B; ==> FMA213 B, a, C;
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{ Form132Index, Form231Index, Form213Index },
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// 2: SrcOpIdx1 == 2 && SrcOpIdx2 == 3;
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// FMA132 a, C, B; ==> FMA213 a, B, C;
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// FMA213 b, A, C; ==> FMA132 b, C, A;
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// FMA231 c, A, B; ==> FMA231 c, B, A;
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{ Form213Index, Form132Index, Form231Index }
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};
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// Everything is ready, just adjust the FMA opcode and return it.
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FormIndex = FormMapping[Case][FormIndex];
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return FoundOpcodesGroup[FormIndex];
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}
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MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI,
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unsigned OpIdx1,
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unsigned OpIdx2) const {
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@ -3506,8 +3699,11 @@ MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI,
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OpIdx1, OpIdx2);
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}
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default:
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if (isFMA3(MI.getOpcode())) {
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unsigned Opc = getFMA3OpcodeToCommuteOperands(MI, OpIdx1, OpIdx2);
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bool IsIntrinOpcode;
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if (isFMA3(MI.getOpcode(), IsIntrinOpcode)) {
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unsigned Opc = getFMA3OpcodeToCommuteOperands(MI.getOpcode(),
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IsIntrinOpcode,
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OpIdx1, OpIdx2);
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if (Opc == 0)
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return nullptr;
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auto &WorkingMI = cloneIfNew(MI);
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@ -3521,6 +3717,7 @@ MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI,
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}
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bool X86InstrInfo::findFMA3CommutedOpIndices(MachineInstr &MI,
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bool IsIntrinOpcode,
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unsigned &SrcOpIdx1,
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unsigned &SrcOpIdx2) const {
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@ -3577,195 +3774,8 @@ bool X86InstrInfo::findFMA3CommutedOpIndices(MachineInstr &MI,
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// Check if we can adjust the opcode to preserve the semantics when
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// commute the register operands.
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return getFMA3OpcodeToCommuteOperands(MI, SrcOpIdx1, SrcOpIdx2) != 0;
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}
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unsigned X86InstrInfo::getFMA3OpcodeToCommuteOperands(
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MachineInstr &MI, unsigned SrcOpIdx1, unsigned SrcOpIdx2) const {
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unsigned Opc = MI.getOpcode();
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// Define the array that holds FMA opcodes in groups
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// of 3 opcodes(132, 213, 231) in each group.
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static const uint16_t RegularOpcodeGroups[][3] = {
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{ X86::VFMADDSSr132r, X86::VFMADDSSr213r, X86::VFMADDSSr231r },
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{ X86::VFMADDSDr132r, X86::VFMADDSDr213r, X86::VFMADDSDr231r },
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{ X86::VFMADDPSr132r, X86::VFMADDPSr213r, X86::VFMADDPSr231r },
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{ X86::VFMADDPDr132r, X86::VFMADDPDr213r, X86::VFMADDPDr231r },
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{ X86::VFMADDPSr132rY, X86::VFMADDPSr213rY, X86::VFMADDPSr231rY },
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{ X86::VFMADDPDr132rY, X86::VFMADDPDr213rY, X86::VFMADDPDr231rY },
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{ X86::VFMADDSSr132m, X86::VFMADDSSr213m, X86::VFMADDSSr231m },
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{ X86::VFMADDSDr132m, X86::VFMADDSDr213m, X86::VFMADDSDr231m },
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{ X86::VFMADDPSr132m, X86::VFMADDPSr213m, X86::VFMADDPSr231m },
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{ X86::VFMADDPDr132m, X86::VFMADDPDr213m, X86::VFMADDPDr231m },
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{ X86::VFMADDPSr132mY, X86::VFMADDPSr213mY, X86::VFMADDPSr231mY },
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{ X86::VFMADDPDr132mY, X86::VFMADDPDr213mY, X86::VFMADDPDr231mY },
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{ X86::VFMSUBSSr132r, X86::VFMSUBSSr213r, X86::VFMSUBSSr231r },
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{ X86::VFMSUBSDr132r, X86::VFMSUBSDr213r, X86::VFMSUBSDr231r },
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{ X86::VFMSUBPSr132r, X86::VFMSUBPSr213r, X86::VFMSUBPSr231r },
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{ X86::VFMSUBPDr132r, X86::VFMSUBPDr213r, X86::VFMSUBPDr231r },
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{ X86::VFMSUBPSr132rY, X86::VFMSUBPSr213rY, X86::VFMSUBPSr231rY },
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{ X86::VFMSUBPDr132rY, X86::VFMSUBPDr213rY, X86::VFMSUBPDr231rY },
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{ X86::VFMSUBSSr132m, X86::VFMSUBSSr213m, X86::VFMSUBSSr231m },
|
||||
{ X86::VFMSUBSDr132m, X86::VFMSUBSDr213m, X86::VFMSUBSDr231m },
|
||||
{ X86::VFMSUBPSr132m, X86::VFMSUBPSr213m, X86::VFMSUBPSr231m },
|
||||
{ X86::VFMSUBPDr132m, X86::VFMSUBPDr213m, X86::VFMSUBPDr231m },
|
||||
{ X86::VFMSUBPSr132mY, X86::VFMSUBPSr213mY, X86::VFMSUBPSr231mY },
|
||||
{ X86::VFMSUBPDr132mY, X86::VFMSUBPDr213mY, X86::VFMSUBPDr231mY },
|
||||
|
||||
{ X86::VFNMADDSSr132r, X86::VFNMADDSSr213r, X86::VFNMADDSSr231r },
|
||||
{ X86::VFNMADDSDr132r, X86::VFNMADDSDr213r, X86::VFNMADDSDr231r },
|
||||
{ X86::VFNMADDPSr132r, X86::VFNMADDPSr213r, X86::VFNMADDPSr231r },
|
||||
{ X86::VFNMADDPDr132r, X86::VFNMADDPDr213r, X86::VFNMADDPDr231r },
|
||||
{ X86::VFNMADDPSr132rY, X86::VFNMADDPSr213rY, X86::VFNMADDPSr231rY },
|
||||
{ X86::VFNMADDPDr132rY, X86::VFNMADDPDr213rY, X86::VFNMADDPDr231rY },
|
||||
{ X86::VFNMADDSSr132m, X86::VFNMADDSSr213m, X86::VFNMADDSSr231m },
|
||||
{ X86::VFNMADDSDr132m, X86::VFNMADDSDr213m, X86::VFNMADDSDr231m },
|
||||
{ X86::VFNMADDPSr132m, X86::VFNMADDPSr213m, X86::VFNMADDPSr231m },
|
||||
{ X86::VFNMADDPDr132m, X86::VFNMADDPDr213m, X86::VFNMADDPDr231m },
|
||||
{ X86::VFNMADDPSr132mY, X86::VFNMADDPSr213mY, X86::VFNMADDPSr231mY },
|
||||
{ X86::VFNMADDPDr132mY, X86::VFNMADDPDr213mY, X86::VFNMADDPDr231mY },
|
||||
|
||||
{ X86::VFNMSUBSSr132r, X86::VFNMSUBSSr213r, X86::VFNMSUBSSr231r },
|
||||
{ X86::VFNMSUBSDr132r, X86::VFNMSUBSDr213r, X86::VFNMSUBSDr231r },
|
||||
{ X86::VFNMSUBPSr132r, X86::VFNMSUBPSr213r, X86::VFNMSUBPSr231r },
|
||||
{ X86::VFNMSUBPDr132r, X86::VFNMSUBPDr213r, X86::VFNMSUBPDr231r },
|
||||
{ X86::VFNMSUBPSr132rY, X86::VFNMSUBPSr213rY, X86::VFNMSUBPSr231rY },
|
||||
{ X86::VFNMSUBPDr132rY, X86::VFNMSUBPDr213rY, X86::VFNMSUBPDr231rY },
|
||||
{ X86::VFNMSUBSSr132m, X86::VFNMSUBSSr213m, X86::VFNMSUBSSr231m },
|
||||
{ X86::VFNMSUBSDr132m, X86::VFNMSUBSDr213m, X86::VFNMSUBSDr231m },
|
||||
{ X86::VFNMSUBPSr132m, X86::VFNMSUBPSr213m, X86::VFNMSUBPSr231m },
|
||||
{ X86::VFNMSUBPDr132m, X86::VFNMSUBPDr213m, X86::VFNMSUBPDr231m },
|
||||
{ X86::VFNMSUBPSr132mY, X86::VFNMSUBPSr213mY, X86::VFNMSUBPSr231mY },
|
||||
{ X86::VFNMSUBPDr132mY, X86::VFNMSUBPDr213mY, X86::VFNMSUBPDr231mY },
|
||||
|
||||
{ X86::VFMADDSUBPSr132r, X86::VFMADDSUBPSr213r, X86::VFMADDSUBPSr231r },
|
||||
{ X86::VFMADDSUBPDr132r, X86::VFMADDSUBPDr213r, X86::VFMADDSUBPDr231r },
|
||||
{ X86::VFMADDSUBPSr132rY, X86::VFMADDSUBPSr213rY, X86::VFMADDSUBPSr231rY },
|
||||
{ X86::VFMADDSUBPDr132rY, X86::VFMADDSUBPDr213rY, X86::VFMADDSUBPDr231rY },
|
||||
{ X86::VFMADDSUBPSr132m, X86::VFMADDSUBPSr213m, X86::VFMADDSUBPSr231m },
|
||||
{ X86::VFMADDSUBPDr132m, X86::VFMADDSUBPDr213m, X86::VFMADDSUBPDr231m },
|
||||
{ X86::VFMADDSUBPSr132mY, X86::VFMADDSUBPSr213mY, X86::VFMADDSUBPSr231mY },
|
||||
{ X86::VFMADDSUBPDr132mY, X86::VFMADDSUBPDr213mY, X86::VFMADDSUBPDr231mY },
|
||||
|
||||
{ X86::VFMSUBADDPSr132r, X86::VFMSUBADDPSr213r, X86::VFMSUBADDPSr231r },
|
||||
{ X86::VFMSUBADDPDr132r, X86::VFMSUBADDPDr213r, X86::VFMSUBADDPDr231r },
|
||||
{ X86::VFMSUBADDPSr132rY, X86::VFMSUBADDPSr213rY, X86::VFMSUBADDPSr231rY },
|
||||
{ X86::VFMSUBADDPDr132rY, X86::VFMSUBADDPDr213rY, X86::VFMSUBADDPDr231rY },
|
||||
{ X86::VFMSUBADDPSr132m, X86::VFMSUBADDPSr213m, X86::VFMSUBADDPSr231m },
|
||||
{ X86::VFMSUBADDPDr132m, X86::VFMSUBADDPDr213m, X86::VFMSUBADDPDr231m },
|
||||
{ X86::VFMSUBADDPSr132mY, X86::VFMSUBADDPSr213mY, X86::VFMSUBADDPSr231mY },
|
||||
{ X86::VFMSUBADDPDr132mY, X86::VFMSUBADDPDr213mY, X86::VFMSUBADDPDr231mY }
|
||||
};
|
||||
|
||||
// Define the array that holds FMA*_Int opcodes in groups
|
||||
// of 3 opcodes(132, 213, 231) in each group.
|
||||
static const uint16_t IntrinOpcodeGroups[][3] = {
|
||||
{ X86::VFMADDSSr132r_Int, X86::VFMADDSSr213r_Int, X86::VFMADDSSr231r_Int },
|
||||
{ X86::VFMADDSDr132r_Int, X86::VFMADDSDr213r_Int, X86::VFMADDSDr231r_Int },
|
||||
{ X86::VFMADDSSr132m_Int, X86::VFMADDSSr213m_Int, X86::VFMADDSSr231m_Int },
|
||||
{ X86::VFMADDSDr132m_Int, X86::VFMADDSDr213m_Int, X86::VFMADDSDr231m_Int },
|
||||
|
||||
{ X86::VFMSUBSSr132r_Int, X86::VFMSUBSSr213r_Int, X86::VFMSUBSSr231r_Int },
|
||||
{ X86::VFMSUBSDr132r_Int, X86::VFMSUBSDr213r_Int, X86::VFMSUBSDr231r_Int },
|
||||
{ X86::VFMSUBSSr132m_Int, X86::VFMSUBSSr213m_Int, X86::VFMSUBSSr231m_Int },
|
||||
{ X86::VFMSUBSDr132m_Int, X86::VFMSUBSDr213m_Int, X86::VFMSUBSDr231m_Int },
|
||||
|
||||
{ X86::VFNMADDSSr132r_Int, X86::VFNMADDSSr213r_Int, X86::VFNMADDSSr231r_Int },
|
||||
{ X86::VFNMADDSDr132r_Int, X86::VFNMADDSDr213r_Int, X86::VFNMADDSDr231r_Int },
|
||||
{ X86::VFNMADDSSr132m_Int, X86::VFNMADDSSr213m_Int, X86::VFNMADDSSr231m_Int },
|
||||
{ X86::VFNMADDSDr132m_Int, X86::VFNMADDSDr213m_Int, X86::VFNMADDSDr231m_Int },
|
||||
|
||||
{ X86::VFNMSUBSSr132r_Int, X86::VFNMSUBSSr213r_Int, X86::VFNMSUBSSr231r_Int },
|
||||
{ X86::VFNMSUBSDr132r_Int, X86::VFNMSUBSDr213r_Int, X86::VFNMSUBSDr231r_Int },
|
||||
{ X86::VFNMSUBSSr132m_Int, X86::VFNMSUBSSr213m_Int, X86::VFNMSUBSSr231m_Int },
|
||||
{ X86::VFNMSUBSDr132m_Int, X86::VFNMSUBSDr213m_Int, X86::VFNMSUBSDr231m_Int },
|
||||
};
|
||||
|
||||
const unsigned Form132Index = 0;
|
||||
const unsigned Form213Index = 1;
|
||||
const unsigned Form231Index = 2;
|
||||
const unsigned FormsNum = 3;
|
||||
|
||||
bool IsIntrinOpcode;
|
||||
isFMA3(Opc, &IsIntrinOpcode);
|
||||
|
||||
size_t GroupsNum;
|
||||
const uint16_t (*OpcodeGroups)[3];
|
||||
if (IsIntrinOpcode) {
|
||||
GroupsNum = array_lengthof(IntrinOpcodeGroups);
|
||||
OpcodeGroups = IntrinOpcodeGroups;
|
||||
} else {
|
||||
GroupsNum = array_lengthof(RegularOpcodeGroups);
|
||||
OpcodeGroups = RegularOpcodeGroups;
|
||||
}
|
||||
|
||||
const uint16_t *FoundOpcodesGroup = nullptr;
|
||||
size_t FormIndex;
|
||||
|
||||
// Look for the input opcode in the corresponding opcodes table.
|
||||
for (size_t GroupIndex = 0; GroupIndex < GroupsNum && !FoundOpcodesGroup;
|
||||
++GroupIndex) {
|
||||
for (FormIndex = 0; FormIndex < FormsNum; ++FormIndex) {
|
||||
if (OpcodeGroups[GroupIndex][FormIndex] == Opc) {
|
||||
FoundOpcodesGroup = OpcodeGroups[GroupIndex];
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// The input opcode does not match with any of the opcodes from the tables.
|
||||
// The unsupported FMA opcode must be added to one of the two opcode groups
|
||||
// defined above.
|
||||
assert(FoundOpcodesGroup != nullptr && "Unexpected FMA3 opcode");
|
||||
|
||||
// Put the lowest index to SrcOpIdx1 to simplify the checks below.
|
||||
if (SrcOpIdx1 > SrcOpIdx2)
|
||||
std::swap(SrcOpIdx1, SrcOpIdx2);
|
||||
|
||||
// TODO: Commuting the 1st operand of FMA*_Int requires some additional
|
||||
// analysis. The commute optimization is legal only if all users of FMA*_Int
|
||||
// use only the lowest element of the FMA*_Int instruction. Such analysis are
|
||||
// not implemented yet. So, just return 0 in that case.
|
||||
// When such analysis are available this place will be the right place for
|
||||
// calling it.
|
||||
if (IsIntrinOpcode && SrcOpIdx1 == 1)
|
||||
return 0;
|
||||
|
||||
unsigned Case;
|
||||
if (SrcOpIdx1 == 1 && SrcOpIdx2 == 2)
|
||||
Case = 0;
|
||||
else if (SrcOpIdx1 == 1 && SrcOpIdx2 == 3)
|
||||
Case = 1;
|
||||
else if (SrcOpIdx1 == 2 && SrcOpIdx2 == 3)
|
||||
Case = 2;
|
||||
else
|
||||
return 0;
|
||||
|
||||
// Define the FMA forms mapping array that helps to map input FMA form
|
||||
// to output FMA form to preserve the operation semantics after
|
||||
// commuting the operands.
|
||||
static const unsigned FormMapping[][3] = {
|
||||
// 0: SrcOpIdx1 == 1 && SrcOpIdx2 == 2;
|
||||
// FMA132 A, C, b; ==> FMA231 C, A, b;
|
||||
// FMA213 B, A, c; ==> FMA213 A, B, c;
|
||||
// FMA231 C, A, b; ==> FMA132 A, C, b;
|
||||
{ Form231Index, Form213Index, Form132Index },
|
||||
// 1: SrcOpIdx1 == 1 && SrcOpIdx2 == 3;
|
||||
// FMA132 A, c, B; ==> FMA132 B, c, A;
|
||||
// FMA213 B, a, C; ==> FMA231 C, a, B;
|
||||
// FMA231 C, a, B; ==> FMA213 B, a, C;
|
||||
{ Form132Index, Form231Index, Form213Index },
|
||||
// 2: SrcOpIdx1 == 2 && SrcOpIdx2 == 3;
|
||||
// FMA132 a, C, B; ==> FMA213 a, B, C;
|
||||
// FMA213 b, A, C; ==> FMA132 b, C, A;
|
||||
// FMA231 c, A, B; ==> FMA231 c, B, A;
|
||||
{ Form213Index, Form132Index, Form231Index }
|
||||
};
|
||||
|
||||
// Everything is ready, just adjust the FMA opcode and return it.
|
||||
FormIndex = FormMapping[Case][FormIndex];
|
||||
return FoundOpcodesGroup[FormIndex];
|
||||
return getFMA3OpcodeToCommuteOperands(MI.getOpcode(), IsIntrinOpcode,
|
||||
SrcOpIdx1, SrcOpIdx2) != 0;
|
||||
}
|
||||
|
||||
bool X86InstrInfo::findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1,
|
||||
@ -3792,8 +3802,10 @@ bool X86InstrInfo::findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1,
|
||||
return false;
|
||||
}
|
||||
default:
|
||||
if (isFMA3(MI.getOpcode()))
|
||||
return findFMA3CommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
|
||||
bool IsIntrinOpcode;
|
||||
if (isFMA3(MI.getOpcode(), IsIntrinOpcode))
|
||||
return findFMA3CommutedOpIndices(MI, IsIntrinOpcode,
|
||||
SrcOpIdx1, SrcOpIdx2);
|
||||
return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
|
||||
}
|
||||
return false;
|
||||
|
||||
@ -286,22 +286,10 @@ public:
|
||||
/// FMA213 #1, #2, #3
|
||||
/// results into instruction with adjusted opcode:
|
||||
/// FMA231 #3, #2, #1
|
||||
bool findFMA3CommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1,
|
||||
bool findFMA3CommutedOpIndices(MachineInstr &MI, bool IsIntrinOpcode,
|
||||
unsigned &SrcOpIdx1,
|
||||
unsigned &SrcOpIdx2) const;
|
||||
|
||||
/// Returns an adjusted FMA opcode that must be used in FMA instruction that
|
||||
/// performs the same computations as the given MI but which has the operands
|
||||
/// \p SrcOpIdx1 and \p SrcOpIdx2 commuted.
|
||||
/// It may return 0 if it is unsafe to commute the operands.
|
||||
///
|
||||
/// The returned FMA opcode may differ from the opcode in the given \p MI.
|
||||
/// For example, commuting the operands #1 and #3 in the following FMA
|
||||
/// FMA213 #1, #2, #3
|
||||
/// results into instruction with adjusted opcode:
|
||||
/// FMA231 #3, #2, #1
|
||||
unsigned getFMA3OpcodeToCommuteOperands(MachineInstr &MI, unsigned SrcOpIdx1,
|
||||
unsigned SrcOpIdx2) const;
|
||||
|
||||
// Branch analysis.
|
||||
bool isUnpredicatedTerminator(const MachineInstr &MI) const override;
|
||||
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
|
||||
|
||||
Loading…
Reference in New Issue
Block a user