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[AMDGPU] Do not run IR optimizations at -O0

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Differential Revision: https://reviews.llvm.org/D105515
This commit is contained in:
Stanislav Mekhanoshin 2021-07-06 15:10:58 -07:00
parent 0364d8e371
commit fdcf893dae
2 changed files with 9 additions and 14 deletions
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12
lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
View File

@ -940,11 +940,11 @@ void AMDGPUPassConfig::addIRPasses() {
AAR.addAAResult(WrapperPass->getResult()); AAR.addAAResult(WrapperPass->getResult());
})); }));
} }
}
if (TM.getTargetTriple().getArch() == Triple::amdgcn) { if (TM.getTargetTriple().getArch() == Triple::amdgcn) {
// TODO: May want to move later or split into an early and late one. // TODO: May want to move later or split into an early and late one.
addPass(createAMDGPUCodeGenPreparePass()); addPass(createAMDGPUCodeGenPreparePass());
}
} }
TargetPassConfig::addIRPasses(); TargetPassConfig::addIRPasses();
@ -1062,7 +1062,9 @@ ScheduleDAGInstrs *GCNPassConfig::createMachineScheduler(
bool GCNPassConfig::addPreISel() { bool GCNPassConfig::addPreISel() {
AMDGPUPassConfig::addPreISel(); AMDGPUPassConfig::addPreISel();
addPass(createAMDGPULateCodeGenPreparePass()); if (TM->getOptLevel() > CodeGenOpt::None)
addPass(createAMDGPULateCodeGenPreparePass());
if (EnableAtomicOptimizations) { if (EnableAtomicOptimizations) {
addPass(createAMDGPUAtomicOptimizerPass()); addPass(createAMDGPUAtomicOptimizerPass());
} }

11
test/CodeGen/AMDGPU/llc-pipeline.ll
View File

@ -44,11 +44,6 @@
; GCN-O0-NEXT: Lower OpenCL enqueued blocks ; GCN-O0-NEXT: Lower OpenCL enqueued blocks
; GCN-O0-NEXT: Lower uses of LDS variables from non-kernel functions ; GCN-O0-NEXT: Lower uses of LDS variables from non-kernel functions
; GCN-O0-NEXT: FunctionPass Manager ; GCN-O0-NEXT: FunctionPass Manager
; GCN-O0-NEXT: Dominator Tree Construction
; GCN-O0-NEXT: Post-Dominator Tree Construction
; GCN-O0-NEXT: Natural Loop Information
; GCN-O0-NEXT: Legacy Divergence Analysis
; GCN-O0-NEXT: AMDGPU IR optimizations
; GCN-O0-NEXT: Lower Garbage Collection Instructions ; GCN-O0-NEXT: Lower Garbage Collection Instructions
; GCN-O0-NEXT: Shadow Stack GC Lowering ; GCN-O0-NEXT: Shadow Stack GC Lowering
; GCN-O0-NEXT: Lower constant intrinsics ; GCN-O0-NEXT: Lower constant intrinsics
@ -72,13 +67,11 @@
; GCN-O0-NEXT: Function Alias Analysis Results ; GCN-O0-NEXT: Function Alias Analysis Results
; GCN-O0-NEXT: Flatten the CFG ; GCN-O0-NEXT: Flatten the CFG
; GCN-O0-NEXT: Dominator Tree Construction ; GCN-O0-NEXT: Dominator Tree Construction
; GCN-O0-NEXT: Post-Dominator Tree Construction
; GCN-O0-NEXT: Natural Loop Information
; GCN-O0-NEXT: Legacy Divergence Analysis
; GCN-O0-NEXT: AMDGPU IR late optimizations
; GCN-O0-NEXT: Basic Alias Analysis (stateless AA impl) ; GCN-O0-NEXT: Basic Alias Analysis (stateless AA impl)
; GCN-O0-NEXT: Function Alias Analysis Results ; GCN-O0-NEXT: Function Alias Analysis Results
; GCN-O0-NEXT: Natural Loop Information
; GCN-O0-NEXT: Code sinking ; GCN-O0-NEXT: Code sinking
; GCN-O0-NEXT: Post-Dominator Tree Construction
; GCN-O0-NEXT: Legacy Divergence Analysis ; GCN-O0-NEXT: Legacy Divergence Analysis
; GCN-O0-NEXT: Unify divergent function exit nodes ; GCN-O0-NEXT: Unify divergent function exit nodes
; GCN-O0-NEXT: Lazy Value Information Analysis ; GCN-O0-NEXT: Lazy Value Information Analysis