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Pseudo-ize the Thumb tTPsoft instruction.

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It's just a call to a special helper function. Get rid of the T2 variant
entirely, as it's identical to the Thumb1 version.

llvm-svn: 134178
This commit is contained in:
Jim Grosbach 2011-06-30 19:38:01 +00:00
parent bcaaa0ae73
commit fddcf02338
4 changed files with 7 additions and 28 deletions
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3
lib/Target/ARM/ARMExpandPseudoInsts.cpp
View File

@ -856,10 +856,11 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
MI.eraseFromParent();
return true;
}
case ARM::tTPsoft:
case ARM::TPsoft: {
MachineInstrBuilder MIB =
BuildMI(MBB, MBBI, MI.getDebugLoc(),
TII->get(ARM::BL))
TII->get(Opcode == ARM::tTPsoft ? ARM::tBL : ARM::BL))
.addExternalSymbol("__aeabi_read_tp", 0);
MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());

12
lib/Target/ARM/ARMInstrThumb.td
View File

@ -1392,13 +1392,11 @@ def tCDP : T1Cop<(outs), (ins p_imm:$cop, i32imm:$opc1,
//
// __aeabi_read_tp preserves the registers r1-r3.
let isCall = 1, Defs = [R0, LR], Uses = [SP] in
def tTPsoft : TIx2<0b11110, 0b11, 1, (outs), (ins), IIC_Br,
"bl\t__aeabi_read_tp",
[(set R0, ARMthread_pointer)]> {
// Encoding is 0xf7fffffe.
let Inst = 0xf7fffffe;
}
// This is a pseudo inst so that we can get the encoding right,
// complete with fixup for the aeabi_read_tp function.
let isCall = 1, Defs = [R0, R12, LR, CPSR], Uses = [SP] in
def tTPsoft : tPseudoInst<(outs), (ins), Size4Bytes, IIC_Br,
[(set R0, ARMthread_pointer)]>;
//===----------------------------------------------------------------------===//
// SJLJ Exception handling intrinsics

16
lib/Target/ARM/ARMInstrThumb2.td
View File

@ -2908,22 +2908,6 @@ def t2CLREX : T2XI<(outs), (ins), NoItinerary, "clrex",
let Inst{3-0} = 0b1111;
}
//===----------------------------------------------------------------------===//
// TLS Instructions
//
// __aeabi_read_tp preserves the registers r1-r3.
let isCall = 1,
Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
def t2TPsoft : T2XI<(outs), (ins), IIC_Br,
"bl\t__aeabi_read_tp",
[(set R0, ARMthread_pointer)]> {
let Inst{31-27} = 0b11110;
let Inst{15-14} = 0b11;
let Inst{12} = 1;
}
}
//===----------------------------------------------------------------------===//
// SJLJ Exception handling intrinsics
// eh_sjlj_setjmp() is an instruction sequence to store the return

4
utils/TableGen/ARMDecoderEmitter.cpp
View File

@ -1624,10 +1624,6 @@ ARMDEBackend::populateInstruction(const CodeGenInstruction &CGI,
if (Name == "tBX_RET" || Name == "tBX_RET_vararg")
return false;
// Ignore the TPsoft (TLS) instructions, which conflict with tBLr9.
if (Name == "tTPsoft" || Name == "t2TPsoft")
return false;
// Ignore tADR, prefer tADDrPCi.
if (Name == "tADR")
return false;