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[Hexagon] Fix instruction descriptor flags for memory access size

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llvm-svn: 254613
This commit is contained in:
Krzysztof Parzyszek 2015-12-03 15:41:33 +00:00
parent ee432f5070
commit fe24354d38
1 changed files with 6 additions and 2 deletions
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8
lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h
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@ -90,12 +90,16 @@ namespace HexagonII {
PostInc = 6 // Post increment addressing mode
};
// MemAccessSize is represented as 1+log2(N) where N is size in bits.
enum class MemAccessSize {
NoMemAccess = 0, // Not a memory acces instruction.
ByteAccess = 1, // Byte access instruction (memb).
HalfWordAccess = 2, // Half word access instruction (memh).
WordAccess = 3, // Word access instruction (memw).
DoubleWordAccess = 4 // Double word access instruction (memd)
DoubleWordAccess = 4, // Double word access instruction (memd)
// 5, // We do not have a 16 byte vector access.
Vector64Access = 7, // 64 Byte vector access instruction (vmem).
Vector128Access = 8 // 128 Byte vector access instruction (vmem).
};
// MCInstrDesc TSFlags
@ -175,7 +179,7 @@ namespace HexagonII {
AddrModeMask = 0x7,
// Access size for load/store instructions.
MemAccessSizePos = 43,
MemAccesSizeMask = 0x7,
MemAccesSizeMask = 0xf,
// Branch predicted taken.
TakenPos = 47,