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[RISCV] Add isel support for bitcasts between fixed vector types.

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This should fix the issue reported in D96972.

I don't have a good test case for this without those changes.

Differential Revision: https://reviews.llvm.org/D97082
This commit is contained in:
Craig Topper 2021-02-22 11:27:51 -08:00
parent c6be302f55
commit fe30457cb7
2 changed files with 19 additions and 5 deletions
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11
lib/Target/RISCV/RISCVISelDAGToDAG.cpp
View File

@ -912,15 +912,18 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
} }
break; break;
} }
case ISD::BITCAST: case ISD::BITCAST: {
// Just drop bitcasts between scalable vectors. MVT SrcVT = Node->getOperand(0).getSimpleValueType();
if (VT.isScalableVector() && // Just drop bitcasts between vectors if both are fixed or both are
Node->getOperand(0).getSimpleValueType().isScalableVector()) { // scalable.
if ((VT.isScalableVector() && SrcVT.isScalableVector()) ||
(VT.isFixedLengthVector() && SrcVT.isFixedLengthVector())) {
ReplaceUses(SDValue(Node, 0), Node->getOperand(0)); ReplaceUses(SDValue(Node, 0), Node->getOperand(0));
CurDAG->RemoveDeadNode(Node); CurDAG->RemoveDeadNode(Node);
return; return;
} }
break; break;
}
case ISD::INSERT_SUBVECTOR: { case ISD::INSERT_SUBVECTOR: {
SDValue V = Node->getOperand(0); SDValue V = Node->getOperand(0);
SDValue SubV = Node->getOperand(1); SDValue SubV = Node->getOperand(1);

13
lib/Target/RISCV/RISCVISelLowering.cpp
View File

@ -571,6 +571,8 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::ANY_EXTEND, VT, Custom); setOperationAction(ISD::ANY_EXTEND, VT, Custom);
setOperationAction(ISD::SIGN_EXTEND, VT, Custom); setOperationAction(ISD::SIGN_EXTEND, VT, Custom);
setOperationAction(ISD::ZERO_EXTEND, VT, Custom); setOperationAction(ISD::ZERO_EXTEND, VT, Custom);
setOperationAction(ISD::BITCAST, VT, Custom);
} }
for (MVT VT : MVT::fp_fixedlen_vector_valuetypes()) { for (MVT VT : MVT::fp_fixedlen_vector_valuetypes()) {
@ -602,6 +604,8 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setCondCodeAction(CC, VT, Expand); setCondCodeAction(CC, VT, Expand);
setOperationAction(ISD::VSELECT, VT, Custom); setOperationAction(ISD::VSELECT, VT, Custom);
setOperationAction(ISD::BITCAST, VT, Custom);
} }
} }
} }
@ -1099,11 +1103,18 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
case ISD::SRL_PARTS: case ISD::SRL_PARTS:
return lowerShiftRightParts(Op, DAG, false); return lowerShiftRightParts(Op, DAG, false);
case ISD::BITCAST: { case ISD::BITCAST: {
SDValue Op0 = Op.getOperand(0);
// We can handle fixed length vector bitcasts with a simple replacement
// in isel.
if (Op.getValueType().isFixedLengthVector()) {
if (Op0.getValueType().isFixedLengthVector())
return Op;
return SDValue();
}
assert(((Subtarget.is64Bit() && Subtarget.hasStdExtF()) || assert(((Subtarget.is64Bit() && Subtarget.hasStdExtF()) ||
Subtarget.hasStdExtZfh()) && Subtarget.hasStdExtZfh()) &&
"Unexpected custom legalisation"); "Unexpected custom legalisation");
SDLoc DL(Op); SDLoc DL(Op);
SDValue Op0 = Op.getOperand(0);
if (Op.getValueType() == MVT::f16 && Subtarget.hasStdExtZfh()) { if (Op.getValueType() == MVT::f16 && Subtarget.hasStdExtZfh()) {
if (Op0.getValueType() != MVT::i16) if (Op0.getValueType() != MVT::i16)
return SDValue(); return SDValue();