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https://github.com/RPCS3/llvm-mirror.git
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Implement AnalyzeBranch in Sparc Backend.
llvm-svn: 123561
This commit is contained in:
Venkatraman Govindaraju
parent
24ea7f696e
commit
fe346f6cba
@ -66,15 +66,200 @@ unsigned SparcInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
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return 0;
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}
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static bool IsIntegerCC(unsigned CC)
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{
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return (CC <= SPCC::ICC_VC);
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}
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static SPCC::CondCodes GetOppositeBranchCondition(SPCC::CondCodes CC)
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{
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switch(CC) {
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default: llvm_unreachable("Unknown condition code");
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case SPCC::ICC_NE: return SPCC::ICC_E;
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case SPCC::ICC_E: return SPCC::ICC_NE;
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case SPCC::ICC_G: return SPCC::ICC_LE;
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case SPCC::ICC_LE: return SPCC::ICC_G;
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case SPCC::ICC_GE: return SPCC::ICC_L;
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case SPCC::ICC_L: return SPCC::ICC_GE;
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case SPCC::ICC_GU: return SPCC::ICC_LEU;
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case SPCC::ICC_LEU: return SPCC::ICC_GU;
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case SPCC::ICC_CC: return SPCC::ICC_CS;
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case SPCC::ICC_CS: return SPCC::ICC_CC;
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case SPCC::ICC_POS: return SPCC::ICC_NEG;
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case SPCC::ICC_NEG: return SPCC::ICC_POS;
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case SPCC::ICC_VC: return SPCC::ICC_VS;
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case SPCC::ICC_VS: return SPCC::ICC_VC;
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case SPCC::FCC_U: return SPCC::FCC_O;
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case SPCC::FCC_O: return SPCC::FCC_U;
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case SPCC::FCC_G: return SPCC::FCC_LE;
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case SPCC::FCC_LE: return SPCC::FCC_G;
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case SPCC::FCC_UG: return SPCC::FCC_ULE;
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case SPCC::FCC_ULE: return SPCC::FCC_UG;
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case SPCC::FCC_L: return SPCC::FCC_GE;
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case SPCC::FCC_GE: return SPCC::FCC_L;
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case SPCC::FCC_UL: return SPCC::FCC_UGE;
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case SPCC::FCC_UGE: return SPCC::FCC_UL;
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case SPCC::FCC_LG: return SPCC::FCC_UE;
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case SPCC::FCC_UE: return SPCC::FCC_LG;
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case SPCC::FCC_NE: return SPCC::FCC_E;
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case SPCC::FCC_E: return SPCC::FCC_NE;
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}
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}
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bool SparcInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
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MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify) const
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{
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MachineBasicBlock::iterator I = MBB.end();
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MachineBasicBlock::iterator UnCondBrIter = MBB.end();
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while (I != MBB.begin()) {
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--I;
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if (I->isDebugValue())
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continue;
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//When we see a non-terminator, we are done
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if (!isUnpredicatedTerminator(I))
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break;
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//Terminator is not a branch
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if (!I->getDesc().isBranch())
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return true;
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//Handle Unconditional branches
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if (I->getOpcode() == SP::BA) {
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UnCondBrIter = I;
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if (!AllowModify) {
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TBB = I->getOperand(0).getMBB();
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continue;
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}
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while (llvm::next(I) != MBB.end())
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llvm::next(I)->eraseFromParent();
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Cond.clear();
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FBB = 0;
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if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
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TBB = 0;
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I->eraseFromParent();
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I = MBB.end();
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UnCondBrIter = MBB.end();
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continue;
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}
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TBB = I->getOperand(0).getMBB();
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continue;
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}
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unsigned Opcode = I->getOpcode();
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if (Opcode != SP::BCOND && Opcode != SP::FBCOND)
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return true; //Unknown Opcode
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SPCC::CondCodes BranchCode = (SPCC::CondCodes)I->getOperand(1).getImm();
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if (Cond.empty()) {
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MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
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if (AllowModify && UnCondBrIter != MBB.end() &&
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MBB.isLayoutSuccessor(TargetBB)) {
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//Transform the code
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//
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// brCC L1
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// ba L2
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// L1:
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// ..
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// L2:
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//
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// into
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//
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// brnCC L2
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// L1:
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// ...
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// L2:
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//
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BranchCode = GetOppositeBranchCondition(BranchCode);
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MachineBasicBlock::iterator OldInst = I;
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BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(Opcode))
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.addMBB(UnCondBrIter->getOperand(0).getMBB()).addImm(BranchCode);
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BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(SP::BA))
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.addMBB(TargetBB);
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MBB.addSuccessor(TargetBB);
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OldInst->eraseFromParent();
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UnCondBrIter->eraseFromParent();
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UnCondBrIter = MBB.end();
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I = MBB.end();
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continue;
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}
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FBB = TBB;
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TBB = I->getOperand(0).getMBB();
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Cond.push_back(MachineOperand::CreateImm(BranchCode));
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continue;
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}
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//FIXME: Handle subsequent conditional branches
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//For now, we can't handle multiple conditional branches
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return true;
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}
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return false;
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}
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unsigned
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SparcInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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const SmallVectorImpl<MachineOperand> &Cond,
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DebugLoc DL)const{
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// Can only insert uncond branches so far.
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assert(Cond.empty() && !FBB && TBB && "Can only handle uncond branches!");
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BuildMI(&MBB, DL, get(SP::BA)).addMBB(TBB);
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return 1;
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DebugLoc DL) const {
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assert(TBB && "InsertBranch must not be told to insert a fallthrough");
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assert((Cond.size() == 1 || Cond.size() == 0) &&
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"Sparc branch conditions should have one component!");
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if (Cond.empty()) {
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assert(!FBB && "Unconditional branch with multiple successors!");
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BuildMI(&MBB, DL, get(SP::BA)).addMBB(TBB);
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return 1;
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}
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//Conditional branch
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unsigned CC = Cond[0].getImm();
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if (IsIntegerCC(CC))
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BuildMI(&MBB, DL, get(SP::BCOND)).addMBB(TBB).addImm(CC);
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else
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BuildMI(&MBB, DL, get(SP::FBCOND)).addMBB(TBB).addImm(CC);
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if (!FBB)
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return 1;
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BuildMI(&MBB, DL, get(SP::BA)).addMBB(FBB);
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return 2;
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}
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unsigned SparcInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const
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{
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MachineBasicBlock::iterator I = MBB.end();
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unsigned Count = 0;
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while (I != MBB.begin()) {
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--I;
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if (I->isDebugValue())
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continue;
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if (I->getOpcode() != SP::BA
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&& I->getOpcode() != SP::BCOND
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&& I->getOpcode() != SP::FBCOND)
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break; // Not a branch
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I->eraseFromParent();
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I = MBB.end();
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++Count;
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}
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return Count;
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}
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void SparcInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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@ -58,8 +58,15 @@ public:
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/// any side effects other than storing to the stack slot.
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virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
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int &FrameIndex) const;
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virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify = false) const ;
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virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
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virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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const SmallVectorImpl<MachineOperand> &Cond,
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@ -17,7 +17,7 @@ define i32 @test_select_int_icc(i32 %a, i32 %b, i32 %c) nounwind readnone noinli
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entry:
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; CHECK: test_select_int_icc
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; CHECK: subcc
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; CHECK: be
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; CHECK: {{be|bne}}
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%0 = icmp eq i32 %a, 0
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%1 = select i1 %0, i32 %b, i32 %c
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ret i32 %1
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@ -28,7 +28,7 @@ define float @test_select_fp_icc(i32 %a, float %f1, float %f2) nounwind readnone
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entry:
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; CHECK: test_select_fp_icc
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; CHECK: subcc
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; CHECK: be
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; CHECK: {{be|bne}}
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%0 = icmp eq i32 %a, 0
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%1 = select i1 %0, float %f1, float %f2
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ret float %1
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@ -36,9 +36,9 @@ entry:
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define double @test_select_dfp_icc(i32 %a, double %f1, double %f2) nounwind readnone noinline {
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entry:
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; CHECK: test_select_fp_icc
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; CHECK: test_select_dfp_icc
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; CHECK: subcc
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; CHECK: be
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; CHECK: {{be|bne}}
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%0 = icmp eq i32 %a, 0
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%1 = select i1 %0, double %f1, double %f2
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ret double %1
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@ -48,7 +48,7 @@ define i32 @test_select_int_fcc(float %f, i32 %a, i32 %b) nounwind readnone noin
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entry:
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;CHECK: test_select_int_fcc
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;CHECK: fcmps
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;CHECK: fbne
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;CHECK: {{fbe|fbne}}
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%0 = fcmp une float %f, 0.000000e+00
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%a.b = select i1 %0, i32 %a, i32 %b
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ret i32 %a.b
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@ -59,7 +59,7 @@ define float @test_select_fp_fcc(float %f, float %f1, float %f2) nounwind readno
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entry:
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;CHECK: test_select_fp_fcc
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;CHECK: fcmps
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;CHECK: fbne
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;CHECK: {{fbe|fbne}}
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%0 = fcmp une float %f, 0.000000e+00
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%1 = select i1 %0, float %f1, float %f2
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ret float %1
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@ -69,7 +69,7 @@ define double @test_select_dfp_fcc(double %f, double %f1, double %f2) nounwind r
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entry:
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;CHECK: test_select_dfp_fcc
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;CHECK: fcmpd
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;CHECK: fbne
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;CHECK: {{fbne|fbe}}
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%0 = fcmp une double %f, 0.000000e+00
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%1 = select i1 %0, double %f1, double %f2
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ret double %1
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