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Merge ISD::TRUNCSTORE to ISD::STORE. Switch to using StoreSDNode.

Browse Source 
llvm-svn: 30945
This commit is contained in:
Evan Cheng 2006-10-13 21:14:26 +00:00
parent b441d8e8ce
commit fe5bb5dbe6
23 changed files with 457 additions and 378 deletions
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5
include/llvm/CodeGen/SelectionDAG.h
View File

@ -319,7 +319,10 @@ public:
/// getStore - Helper function to build ISD::STORE nodes.
///
SDOperand getStore(SDOperand Chain, SDOperand Value, SDOperand Ptr,
SDOperand SV);
const Value *SV, int SVOffset, bool isVolatile=false);
SDOperand getTruncStore(SDOperand Chain, SDOperand Value, SDOperand Ptr,
const Value *SV, int SVOffset, MVT::ValueType TVT,
bool isVolatile=false);
// getSrcValue - construct a node to track a Value* through the backend
SDOperand getSrcValue(const Value* I, int offset = 0);

32
include/llvm/CodeGen/SelectionDAGNodes.h
View File

@ -1408,15 +1408,6 @@ protected:
assert((Off.getOpcode() == ISD::UNDEF || AddrMode == ISD::POST_INDEXED) &&
"Only post-indexed load has a non-undef offset operand");
}
LoadSDNode(SDOperand Chain, SDOperand Ptr, SDOperand Off,
ISD::LoadExtType ETy, MVT::ValueType LVT,
const Value *SV, int O=0, unsigned Align=1, bool Vol=false)
: SDNode(ISD::LOAD, Chain, Ptr, Off),
AddrMode(ISD::UNINDEXED), ExtType(ETy), LoadedVT(LVT), SrcValue(SV),
SVOffset(O), Alignment(Align), IsVolatile(Vol) {
assert((Off.getOpcode() == ISD::UNDEF || AddrMode == ISD::POST_INDEXED) &&
"Only post-indexed load has a non-undef offset operand");
}
public:
const SDOperand getChain() const { return getOperand(0); }
@ -1461,10 +1452,10 @@ class StoreSDNode : public SDNode {
bool IsVolatile;
protected:
friend class SelectionDAG;
StoreSDNode(SDOperand Chain, SDOperand Ptr, SDOperand Off,
StoreSDNode(SDOperand Chain, SDOperand Value, SDOperand Ptr, SDOperand Off,
ISD::MemOpAddrMode AM, bool isTrunc, MVT::ValueType SVT,
const Value *SV, int O=0, unsigned Align=0, bool Vol=false)
: SDNode(ISD::STORE, Chain, Ptr, Off),
: SDNode(ISD::STORE, Chain, Value, Ptr, Off),
AddrMode(AM), IsTruncStore(isTrunc), StoredVT(SVT), SrcValue(SV),
SVOffset(O), Alignment(Align), IsVolatile(Vol) {
assert((Off.getOpcode() == ISD::UNDEF || AddrMode == ISD::POST_INDEXED) &&
@ -1473,8 +1464,9 @@ protected:
public:
const SDOperand getChain() const { return getOperand(0); }
const SDOperand getBasePtr() const { return getOperand(1); }
const SDOperand getOffset() const { return getOperand(2); }
const SDOperand getValue() const { return getOperand(1); }
const SDOperand getBasePtr() const { return getOperand(2); }
const SDOperand getOffset() const { return getOperand(3); }
ISD::MemOpAddrMode getAddressingMode() const { return AddrMode; }
bool isTruncatingStore() const { return IsTruncStore; }
MVT::ValueType getStoredVT() const { return StoredVT; }
@ -1591,6 +1583,20 @@ namespace ISD {
return N->getOpcode() == ISD::LOAD &&
cast<LoadSDNode>(N)->getExtensionType() == ISD::ZEXTLOAD;
}
/// isNON_TRUNCStore - Returns true if the specified node is a non-truncating
/// store.
inline bool isNON_TRUNCStore(const SDNode *N) {
return N->getOpcode() == ISD::STORE &&
!cast<StoreSDNode>(N)->isTruncatingStore();
}
/// isTRUNCStore - Returns true if the specified node is a truncating
/// store.
inline bool isTRUNCStore(const SDNode *N) {
return N->getOpcode() == ISD::STORE &&
cast<StoreSDNode>(N)->isTruncatingStore();
}
}

29
include/llvm/Target/TargetLowering.h
View File

@ -238,12 +238,26 @@ public:
}
/// isLoadXLegal - Return true if the specified load with extension is legal
/// is legal on this target.
/// on this target.
bool isLoadXLegal(unsigned LType, MVT::ValueType VT) const {
return getLoadXAction(LType, VT) == Legal ||
getLoadXAction(LType, VT) == Custom;
}
/// getStoreXAction - Return how this store with truncation should be treated:
/// either it is legal, needs to be promoted to a larger size, needs to be
/// expanded to some other code sequence, or the target has a custom expander
/// for it.
LegalizeAction getStoreXAction(MVT::ValueType VT) const {
return (LegalizeAction)((StoreXActions >> (2*VT)) & 3);
}
/// isStoreXLegal - Return true if the specified store with truncation is
/// legal on this target.
bool isStoreXLegal(MVT::ValueType VT) const {
return getStoreXAction(VT) == Legal || getStoreXAction(VT) == Custom;
}
/// getTypeToPromoteTo - If the action for this operation is to promote, this
/// method returns the ValueType to promote to.
MVT::ValueType getTypeToPromoteTo(unsigned Op, MVT::ValueType VT) const {
@ -559,6 +573,14 @@ protected:
LoadXActions[ExtType] |= (uint64_t)Action << VT*2;
}
/// setStoreXAction - Indicate that the specified store with truncation does
/// not work with the with specified type and indicate what to do about it.
void setStoreXAction(MVT::ValueType VT, LegalizeAction Action) {
assert(VT < 32 && "Table isn't big enough!");
StoreXActions &= ~(uint64_t(3UL) << VT*2);
StoreXActions |= (uint64_t)Action << VT*2;
}
/// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the
/// promotion code defaults to trying a larger integer/fp until it can find
/// one that works. If that default is insufficient, this method can be used
@ -814,6 +836,11 @@ private:
/// with the load.
uint64_t LoadXActions[ISD::LAST_LOADX_TYPE];
/// StoreXActions - For each store with truncation of each value type, keep a
/// LegalizeAction that indicates how instruction selection should deal with
/// the store.
uint64_t StoreXActions;
ValueTypeActionImpl ValueTypeActions;
std::vector<double> LegalFPImmediates;

76
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
View File

@ -503,8 +503,6 @@ SDOperand DAGCombiner::visit(SDNode *N) {
case ISD::BRCOND: return visitBRCOND(N);
case ISD::BR_CC: return visitBR_CC(N);
case ISD::LOAD: return visitLOAD(N);
// FIXME - Switch over after StoreSDNode comes online.
case ISD::TRUNCSTORE: // Fall thru
case ISD::STORE: return visitSTORE(N);
case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
case ISD::VINSERT_VECTOR_ELT: return visitVINSERT_VECTOR_ELT(N);
@ -2687,9 +2685,12 @@ SDOperand DAGCombiner::visitLOAD(SDNode *N) {
// TODO: Handle store large -> read small portion.
// TODO: Handle TRUNCSTORE/LOADEXT
if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
if (Chain.getOpcode() == ISD::STORE && Chain.getOperand(2) == Ptr &&
Chain.getOperand(1).getValueType() == N->getValueType(0))
if (ISD::isNON_TRUNCStore(Chain.Val)) {
StoreSDNode *PrevST = cast<StoreSDNode>(Chain);
if (PrevST->getBasePtr() == Ptr &&
PrevST->getValue().getValueType() == N->getValueType(0))
return CombineTo(N, Chain.getOperand(1), Chain);
}
}
if (CombinerAA) {
@ -2725,13 +2726,13 @@ SDOperand DAGCombiner::visitLOAD(SDNode *N) {
}
SDOperand DAGCombiner::visitSTORE(SDNode *N) {
SDOperand Chain = N->getOperand(0);
SDOperand Value = N->getOperand(1);
SDOperand Ptr = N->getOperand(2);
SDOperand SrcValue = N->getOperand(3);
StoreSDNode *ST = cast<StoreSDNode>(N);
SDOperand Chain = ST->getChain();
SDOperand Value = ST->getValue();
SDOperand Ptr = ST->getBasePtr();
// FIXME - Switch over after StoreSDNode comes online.
if (N->getOpcode() == ISD::TRUNCSTORE) {
if (ST->isTruncatingStore()) {
if (CombinerAA) {
// Walk up chain skipping non-aliasing memory nodes.
SDOperand BetterChain = FindBetterChain(N, Chain);
@ -2739,9 +2740,9 @@ SDOperand DAGCombiner::visitSTORE(SDNode *N) {
// If there is a better chain.
if (Chain != BetterChain) {
// Replace the chain to avoid dependency.
SDOperand ReplTStore = DAG.getNode(ISD::TRUNCSTORE, MVT::Other,
BetterChain, Value, Ptr, SrcValue,
N->getOperand(4));
SDOperand ReplTStore =
DAG.getTruncStore(BetterChain, Value, Ptr, ST->getSrcValue(),
ST->getSrcValueOffset(), ST->getStoredVT());
// Create token to keep both nodes around.
return DAG.getNode(ISD::TokenFactor, MVT::Other, Chain, ReplTStore);
@ -2752,27 +2753,30 @@ SDOperand DAGCombiner::visitSTORE(SDNode *N) {
}
// If this is a store that kills a previous store, remove the previous store.
if (Chain.getOpcode() == ISD::STORE && Chain.getOperand(2) == Ptr &&
Chain.Val->hasOneUse() /* Avoid introducing DAG cycles */ &&
// Make sure that these stores are the same value type:
// FIXME: we really care that the second store is >= size of the first.
Value.getValueType() == Chain.getOperand(1).getValueType()) {
// Create a new store of Value that replaces both stores.
SDNode *PrevStore = Chain.Val;
if (PrevStore->getOperand(1) == Value) // Same value multiply stored.
return Chain;
SDOperand NewStore = DAG.getStore(PrevStore->getOperand(0), Value, Ptr,
SrcValue);
CombineTo(N, NewStore); // Nuke this store.
CombineTo(PrevStore, NewStore); // Nuke the previous store.
return SDOperand(N, 0);
if (ISD::isNON_TRUNCStore(Chain.Val)) {
StoreSDNode *PrevST = cast<StoreSDNode>(Chain);
if (PrevST->getBasePtr() == Ptr &&
Chain.Val->hasOneUse() /* Avoid introducing DAG cycles */ &&
// Make sure that these stores are the same value type:
// FIXME: we really care that the second store is >= size of the first.
Value.getValueType() == PrevST->getValue().getValueType()) {
// Create a new store of Value that replaces both stores.
if (PrevST->getValue() == Value) // Same value multiply stored.
return Chain;
SDOperand NewStore = DAG.getStore(PrevST->getChain(), Value, Ptr,
ST->getSrcValue(), ST->getSrcValueOffset());
CombineTo(N, NewStore); // Nuke this store.
CombineTo(Chain.Val, NewStore); // Nuke the previous store.
return SDOperand(N, 0);
}
}
// If this is a store of a bit convert, store the input value.
// FIXME: This needs to know that the resultant store does not need a
// higher alignment than the original.
if (0 && Value.getOpcode() == ISD::BIT_CONVERT) {
return DAG.getStore(Chain, Value.getOperand(0), Ptr, SrcValue);
return DAG.getStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(),
ST->getSrcValueOffset());
}
if (CombinerAA) {
@ -2789,7 +2793,8 @@ SDOperand DAGCombiner::visitSTORE(SDNode *N) {
// If there is a better chain.
if (Chain != BetterChain) {
// Replace the chain to avoid dependency.
SDOperand ReplStore = DAG.getStore(BetterChain, Value, Ptr, SrcValue);
SDOperand ReplStore = DAG.getStore(BetterChain, Value, Ptr,
ST->getSrcValue(), ST->getSrcValueOffset());
// Create token to keep both nodes around.
return DAG.getNode(ISD::TokenFactor, MVT::Other, Chain, ReplStore);
}
@ -4050,20 +4055,9 @@ bool DAGCombiner::FindAliasInfo(SDNode *N,
SrcValue = LD->getSrcValue();
return true;
} else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
#if 1 // FIXME - Switch over after StoreSDNode comes online.
Ptr = ST->getOperand(2);
Size = MVT::getSizeInBits(ST->getOperand(1).getValueType()) >> 3;
SrcValue = 0;
#else
Ptr = ST->getBasePtr();
Size = MVT::getSizeInBits(ST->getOperand(1).getValueType()) >> 3;
Size = MVT::getSizeInBits(ST->getStoredVT()) >> 3;
SrcValue = ST->getSrcValue();
#endif
// FIXME - Switch over after StoreSDNode comes online.
} else if (N->getOpcode() == ISD::TRUNCSTORE) {
Ptr = N->getOperand(2);
Size = MVT::getSizeInBits(cast<VTSDNode>(N->getOperand(4))->getVT()) >> 3;
SrcValue = 0;
} else {
assert(0 && "FindAliasInfo expected a memory operand");
}
@ -4104,8 +4098,6 @@ void DAGCombiner::GatherAllAliases(SDNode *N, SDOperand OriginalChain,
break;
case ISD::LOAD:
// FIXME - Switch over after StoreSDNode comes online.
case ISD::TRUNCSTORE:
case ISD::STORE: {
// Get alias information for Chain.
SDOperand OpPtr;

293
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
View File

@ -917,8 +917,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
MVT::ValueType PtrVT = TLI.getPointerTy();
SDOperand StackPtr = CreateStackTemporary(VT);
// Store the vector.
SDOperand Ch = DAG.getStore(DAG.getEntryNode(),
Tmp1, StackPtr, DAG.getSrcValue(NULL));
SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr, NULL, 0);
// Truncate or zero extend offset to target pointer type.
unsigned CastOpc = (IdxVT > PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
@ -928,7 +927,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr);
// Store the scalar value.
Ch = DAG.getStore(Ch, Tmp2, StackPtr2, DAG.getSrcValue(NULL));
Ch = DAG.getStore(Ch, Tmp2, StackPtr2, NULL, 0);
// Load the updated vector.
Result = DAG.getLoad(VT, Ch, StackPtr, NULL, 0);
break;
@ -1592,109 +1591,144 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
}
break;
case ISD::STORE: {
Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
Tmp2 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer.
StoreSDNode *ST = cast<StoreSDNode>(Node);
Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain.
Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer.
// Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
// FIXME: We shouldn't do this for TargetConstantFP's.
// FIXME: move this to the DAG Combiner!
if (ConstantFPSDNode *CFP =dyn_cast<ConstantFPSDNode>(Node->getOperand(1))){
if (CFP->getValueType(0) == MVT::f32) {
Tmp3 = DAG.getConstant(FloatToBits(CFP->getValue()), MVT::i32);
} else {
assert(CFP->getValueType(0) == MVT::f64 && "Unknown FP type!");
Tmp3 = DAG.getConstant(DoubleToBits(CFP->getValue()), MVT::i64);
if (!ST->isTruncatingStore()) {
// Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
// FIXME: We shouldn't do this for TargetConstantFP's.
// FIXME: move this to the DAG Combiner!
if (ConstantFPSDNode *CFP =dyn_cast<ConstantFPSDNode>(ST->getValue())) {
if (CFP->getValueType(0) == MVT::f32) {
Tmp3 = DAG.getConstant(FloatToBits(CFP->getValue()), MVT::i32);
} else {
assert(CFP->getValueType(0) == MVT::f64 && "Unknown FP type!");
Tmp3 = DAG.getConstant(DoubleToBits(CFP->getValue()), MVT::i64);
}
Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
ST->getSrcValueOffset());
break;
}
Result = DAG.getStore(Tmp1, Tmp3, Tmp2, Node->getOperand(3));
break;
}
switch (getTypeAction(Node->getOperand(1).getValueType())) {
case Legal: {
Tmp3 = LegalizeOp(Node->getOperand(1));
Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
Node->getOperand(3));
switch (getTypeAction(ST->getStoredVT())) {
case Legal: {
Tmp3 = LegalizeOp(ST->getValue());
Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
ST->getOffset());
MVT::ValueType VT = Tmp3.getValueType();
switch (TLI.getOperationAction(ISD::STORE, VT)) {
MVT::ValueType VT = Tmp3.getValueType();
switch (TLI.getOperationAction(ISD::STORE, VT)) {
default: assert(0 && "This action is not supported yet!");
case TargetLowering::Legal: break;
case TargetLowering::Custom:
Tmp1 = TLI.LowerOperation(Result, DAG);
if (Tmp1.Val) Result = Tmp1;
break;
case TargetLowering::Promote:
assert(MVT::isVector(VT) && "Unknown legal promote case!");
Tmp3 = DAG.getNode(ISD::BIT_CONVERT,
TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
Result = DAG.getStore(Tmp1, Tmp3, Tmp2,
ST->getSrcValue(), ST->getSrcValueOffset());
break;
}
break;
}
case Promote:
// Truncate the value and store the result.
Tmp3 = PromoteOp(ST->getValue());
Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
ST->getSrcValueOffset(), ST->getStoredVT());
break;
case Expand:
unsigned IncrementSize = 0;
SDOperand Lo, Hi;
// If this is a vector type, then we have to calculate the increment as
// the product of the element size in bytes, and the number of elements
// in the high half of the vector.
if (ST->getValue().getValueType() == MVT::Vector) {
SDNode *InVal = ST->getValue().Val;
unsigned NumElems =
cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
// Figure out if there is a Packed type corresponding to this Vector
// type. If so, convert to the packed type.
MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
// Turn this into a normal store of the packed type.
Tmp3 = PackVectorOp(Node->getOperand(1), TVT);
Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
ST->getSrcValueOffset());
Result = LegalizeOp(Result);
break;
} else if (NumElems == 1) {
// Turn this into a normal store of the scalar type.
Tmp3 = PackVectorOp(Node->getOperand(1), EVT);
Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
ST->getSrcValueOffset());
// The scalarized value type may not be legal, e.g. it might require
// promotion or expansion. Relegalize the scalar store.
Result = LegalizeOp(Result);
break;
} else {
SplitVectorOp(Node->getOperand(1), Lo, Hi);
IncrementSize = NumElems/2 * MVT::getSizeInBits(EVT)/8;
}
} else {
ExpandOp(Node->getOperand(1), Lo, Hi);
IncrementSize = MVT::getSizeInBits(Hi.getValueType())/8;
if (!TLI.isLittleEndian())
std::swap(Lo, Hi);
}
Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
ST->getSrcValueOffset());
Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
getIntPtrConstant(IncrementSize));
assert(isTypeLegal(Tmp2.getValueType()) &&
"Pointers must be legal!");
// FIXME: This sets the srcvalue of both halves to be the same, which is
// wrong.
Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
ST->getSrcValueOffset());
Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
break;
}
} else {
// Truncating store
assert(isTypeLegal(ST->getValue().getValueType()) &&
"Cannot handle illegal TRUNCSTORE yet!");
Tmp3 = LegalizeOp(ST->getValue());
// The only promote case we handle is TRUNCSTORE:i1 X into
// -> TRUNCSTORE:i8 (and X, 1)
if (ST->getStoredVT() == MVT::i1 &&
TLI.getStoreXAction(MVT::i1) == TargetLowering::Promote) {
// Promote the bool to a mask then store.
Tmp3 = DAG.getNode(ISD::AND, Tmp3.getValueType(), Tmp3,
DAG.getConstant(1, Tmp3.getValueType()));
Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
ST->getSrcValueOffset(), MVT::i8);
} else if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
Tmp2 != ST->getBasePtr()) {
Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
ST->getOffset());
}
MVT::ValueType StVT = cast<StoreSDNode>(Result.Val)->getStoredVT();
switch (TLI.getStoreXAction(StVT)) {
default: assert(0 && "This action is not supported yet!");
case TargetLowering::Legal: break;
case TargetLowering::Legal: break;
case TargetLowering::Custom:
Tmp1 = TLI.LowerOperation(Result, DAG);
if (Tmp1.Val) Result = Tmp1;
break;
case TargetLowering::Promote:
assert(MVT::isVector(VT) && "Unknown legal promote case!");
Tmp3 = DAG.getNode(ISD::BIT_CONVERT,
TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
Node->getOperand(3));
break;
}
break;
}
case Promote:
// Truncate the value and store the result.
Tmp3 = PromoteOp(Node->getOperand(1));
Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp3, Tmp2,
Node->getOperand(3),
DAG.getValueType(Node->getOperand(1).getValueType()));
break;
case Expand:
unsigned IncrementSize = 0;
SDOperand Lo, Hi;
// If this is a vector type, then we have to calculate the increment as
// the product of the element size in bytes, and the number of elements
// in the high half of the vector.
if (Node->getOperand(1).getValueType() == MVT::Vector) {
SDNode *InVal = Node->getOperand(1).Val;
unsigned NumElems =
cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
// Figure out if there is a Packed type corresponding to this Vector
// type. If so, convert to the packed type.
MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
// Turn this into a normal store of the packed type.
Tmp3 = PackVectorOp(Node->getOperand(1), TVT);
Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
Node->getOperand(3));
Result = LegalizeOp(Result);
break;
} else if (NumElems == 1) {
// Turn this into a normal store of the scalar type.
Tmp3 = PackVectorOp(Node->getOperand(1), EVT);
Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
Node->getOperand(3));
// The scalarized value type may not be legal, e.g. it might require
// promotion or expansion. Relegalize the scalar store.
Result = LegalizeOp(Result);
break;
} else {
SplitVectorOp(Node->getOperand(1), Lo, Hi);
IncrementSize = NumElems/2 * MVT::getSizeInBits(EVT)/8;
}
} else {
ExpandOp(Node->getOperand(1), Lo, Hi);
IncrementSize = MVT::getSizeInBits(Hi.getValueType())/8;
if (!TLI.isLittleEndian())
std::swap(Lo, Hi);
}
Lo = DAG.getStore(Tmp1, Lo, Tmp2, Node->getOperand(3));
Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
getIntPtrConstant(IncrementSize));
assert(isTypeLegal(Tmp2.getValueType()) &&
"Pointers must be legal!");
// FIXME: This sets the srcvalue of both halves to be the same, which is
// wrong.
Hi = DAG.getStore(Tmp1, Hi, Tmp2, Node->getOperand(3));
Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
break;
}
break;
}
@ -1772,42 +1806,6 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
return Result;
case ISD::TRUNCSTORE: {
Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer.
assert(isTypeLegal(Node->getOperand(1).getValueType()) &&
"Cannot handle illegal TRUNCSTORE yet!");
Tmp2 = LegalizeOp(Node->getOperand(1));
// The only promote case we handle is TRUNCSTORE:i1 X into
// -> TRUNCSTORE:i8 (and X, 1)
if (cast<VTSDNode>(Node->getOperand(4))->getVT() == MVT::i1 &&
TLI.getOperationAction(ISD::TRUNCSTORE, MVT::i1) ==
TargetLowering::Promote) {
// Promote the bool to a mask then store.
Tmp2 = DAG.getNode(ISD::AND, Tmp2.getValueType(), Tmp2,
DAG.getConstant(1, Tmp2.getValueType()));
Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp2, Tmp3,
Node->getOperand(3), DAG.getValueType(MVT::i8));
} else if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
Tmp3 != Node->getOperand(2)) {
Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
Node->getOperand(3), Node->getOperand(4));
}
MVT::ValueType StVT = cast<VTSDNode>(Result.Val->getOperand(4))->getVT();
switch (TLI.getOperationAction(Result.Val->getOpcode(), StVT)) {
default: assert(0 && "This action is not supported yet!");
case TargetLowering::Legal: break;
case TargetLowering::Custom:
Tmp1 = TLI.LowerOperation(Result, DAG);
if (Tmp1.Val) Result = Tmp1;
break;
}
break;
}
case ISD::SELECT:
switch (getTypeAction(Node->getOperand(0).getValueType())) {
case Expand: assert(0 && "It's impossible to expand bools");
@ -2386,7 +2384,8 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
DAG.getConstant(MVT::getSizeInBits(VT)/8,
TLI.getPointerTy()));
// Store the incremented VAList to the legalized pointer
Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, Node->getOperand(2));
Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV->getValue(),
SV->getOffset());
// Load the actual argument out of the pointer VAList
Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0);
Tmp1 = LegalizeOp(Result.getValue(1));
@ -2423,9 +2422,11 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
// This defaults to loading a pointer from the input and storing it to the
// output, returning the chain.
SrcValueSDNode *SVD = cast<SrcValueSDNode>(Node->getOperand(3));
SrcValueSDNode *SVS = cast<SrcValueSDNode>(Node->getOperand(4));
Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, SVD->getValue(),
SVD->getOffset());
Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, Node->getOperand(4));
Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, SVS->getValue(),
SVS->getOffset());
break;
}
break;
@ -2864,9 +2865,8 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
int SSFI =
MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align);
SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, DAG.getEntryNode(),
Node->getOperand(0), StackSlot,
DAG.getSrcValue(NULL), DAG.getValueType(ExtraVT));
Result = DAG.getTruncStore(DAG.getEntryNode(), Node->getOperand(0),
StackSlot, NULL, 0, ExtraVT);
Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
Result, StackSlot, NULL, 0, ExtraVT);
} else {
@ -3213,7 +3213,8 @@ SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
DAG.getConstant(MVT::getSizeInBits(VT)/8,
TLI.getPointerTy()));
// Store the incremented VAList to the legalized pointer
Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, Node->getOperand(2));
Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV->getValue(),
SV->getOffset());
// Load the actual argument out of the pointer VAList
Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT);
}
@ -3351,8 +3352,7 @@ SDOperand SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDOperand Op) {
// If the target doesn't support this, store the value to a temporary
// stack slot, then LOAD the scalar element back out.
SDOperand StackPtr = CreateStackTemporary(Vector.getValueType());
SDOperand Ch = DAG.getStore(DAG.getEntryNode(),
Vector, StackPtr, DAG.getSrcValue(NULL));
SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Vector, StackPtr, NULL, 0);
// Add the offset to the index.
unsigned EltSize = MVT::getSizeInBits(Op.getValueType())/8;
@ -3495,8 +3495,7 @@ SDOperand SelectionDAGLegalize::ExpandBIT_CONVERT(MVT::ValueType DestVT,
SDOperand FIPtr = CreateStackTemporary(DestVT);
// Emit a store to the stack slot.
SDOperand Store = DAG.getStore(DAG.getEntryNode(),
SrcOp, FIPtr, DAG.getSrcValue(NULL));
SDOperand Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr, NULL, 0);
// Result is a load from the stack slot.
return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0);
}
@ -3506,7 +3505,7 @@ SDOperand SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
// then load the whole vector back out.
SDOperand StackPtr = CreateStackTemporary(Node->getValueType(0));
SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr,
DAG.getSrcValue(NULL));
NULL, 0);
return DAG.getLoad(Node->getValueType(0), Ch, StackPtr, NULL, 0);
}
@ -3655,7 +3654,7 @@ SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx);
Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx,
DAG.getSrcValue(NULL)));
NULL, 0));
}
SDOperand StoreChain;
@ -3999,11 +3998,11 @@ SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
}
// store the lo of the constructed double - based on integer input
SDOperand Store1 = DAG.getStore(DAG.getEntryNode(),
Op0Mapped, Lo, DAG.getSrcValue(NULL));
Op0Mapped, Lo, NULL, 0);
// initial hi portion of constructed double
SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
// store the hi of the constructed double - biased exponent
SDOperand Store2=DAG.getStore(Store1, InitialHi, Hi, DAG.getSrcValue(NULL));
SDOperand Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0);
// load the constructed double
SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0);
// FP constant to bias correct the final result
@ -4905,7 +4904,7 @@ void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo,
SDOperand Ptr = CreateStackTemporary(Op.getOperand(0).getValueType());
SDOperand St = DAG.getStore(DAG.getEntryNode(),
Op.getOperand(0), Ptr, DAG.getSrcValue(0));
Op.getOperand(0), Ptr, NULL, 0);
MVT::ValueType EVT = cast<VTSDNode>(TypeNode)->getVT();
St = DAG.getVecLoad(NumElements, EVT, St, Ptr, DAG.getSrcValue(0));
SplitVectorOp(St, Lo, Hi);

97
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
View File

@ -495,6 +495,14 @@ SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N,
ID.AddInteger(LD->getSrcValueOffset());
ID.AddInteger(LD->getAlignment());
ID.AddInteger(LD->isVolatile());
} else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
ID.AddInteger(ST->getAddressingMode());
ID.AddInteger(ST->isTruncatingStore());
ID.AddInteger(ST->getStoredVT());
ID.AddPointer(ST->getSrcValue());
ID.AddInteger(ST->getSrcValueOffset());
ID.AddInteger(ST->getAlignment());
ID.AddInteger(ST->isVolatile());
}
ID.SetOperands(Ops, NumOps);
return CSEMap.FindNodeOrInsertPos(ID, InsertPos);
@ -1507,7 +1515,7 @@ SDOperand SelectionDAG::getLoad(MVT::ValueType VT,
// FIXME: Alignment == 1 for now.
unsigned Alignment = 1;
SDVTList VTs = getVTList(VT, MVT::Other);
SDOperand Undef = getNode(ISD::UNDEF, VT);
SDOperand Undef = getNode(ISD::UNDEF, Ptr.getValueType());
SelectionDAGCSEMap::NodeID ID(ISD::LOAD, VTs, Chain, Ptr, Undef);
ID.AddInteger(ISD::UNINDEXED);
ID.AddInteger(ISD::NON_EXTLOAD);
@ -1519,8 +1527,9 @@ SDOperand SelectionDAG::getLoad(MVT::ValueType VT,
void *IP = 0;
if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
return SDOperand(E, 0);
SDNode *N = new LoadSDNode(Chain, Ptr, Undef, ISD::NON_EXTLOAD, VT,
SV, SVOffset, Alignment, isVolatile);
SDNode *N = new LoadSDNode(Chain, Ptr, Undef, ISD::UNINDEXED,
ISD::NON_EXTLOAD, VT, SV, SVOffset, Alignment,
isVolatile);
N->setValueTypes(VTs);
CSEMap.InsertNode(N, IP);
AllNodes.push_back(N);
@ -1548,7 +1557,7 @@ SDOperand SelectionDAG::getExtLoad(ISD::LoadExtType ExtType, MVT::ValueType VT,
// FIXME: Alignment == 1 for now.
unsigned Alignment = 1;
SDVTList VTs = getVTList(VT, MVT::Other);
SDOperand Undef = getNode(ISD::UNDEF, VT);
SDOperand Undef = getNode(ISD::UNDEF, Ptr.getValueType());
SelectionDAGCSEMap::NodeID ID(ISD::LOAD, VTs, Chain, Ptr, Undef);
ID.AddInteger(ISD::UNINDEXED);
ID.AddInteger(ExtType);
@ -1560,8 +1569,8 @@ SDOperand SelectionDAG::getExtLoad(ISD::LoadExtType ExtType, MVT::ValueType VT,
void *IP = 0;
if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
return SDOperand(E, 0);
SDNode *N = new LoadSDNode(Chain, Ptr, Undef, ExtType, EVT, SV, SVOffset,
Alignment, isVolatile);
SDNode *N = new LoadSDNode(Chain, Ptr, Undef, ISD::UNINDEXED, ExtType, EVT,
SV, SVOffset, Alignment, isVolatile);
N->setValueTypes(VTs);
CSEMap.InsertNode(N, IP);
AllNodes.push_back(N);
@ -1577,14 +1586,63 @@ SDOperand SelectionDAG::getVecLoad(unsigned Count, MVT::ValueType EVT,
}
SDOperand SelectionDAG::getStore(SDOperand Chain, SDOperand Value,
SDOperand Ptr, SDOperand SV) {
SDOperand Ptr, const Value *SV, int SVOffset,
bool isVolatile) {
MVT::ValueType VT = Value.getValueType();
// FIXME: Alignment == 1 for now.
unsigned Alignment = 1;
SDVTList VTs = getVTList(MVT::Other);
SDOperand Ops[] = { Chain, Value, Ptr, SV };
SDOperand Undef = getNode(ISD::UNDEF, Ptr.getValueType());
SDOperand Ops[] = { Chain, Value, Ptr, Undef };
SelectionDAGCSEMap::NodeID ID(ISD::STORE, VTs, Ops, 4);
ID.AddInteger(ISD::UNINDEXED);
ID.AddInteger(false);
ID.AddInteger(VT);
ID.AddPointer(SV);
ID.AddInteger(SVOffset);
ID.AddInteger(Alignment);
ID.AddInteger(isVolatile);
void *IP = 0;
if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
return SDOperand(E, 0);
SDNode *N = new SDNode(ISD::STORE, Chain, Value, Ptr, SV);
SDNode *N = new StoreSDNode(Chain, Value, Ptr, Undef, ISD::UNINDEXED, false,
VT, SV, SVOffset, Alignment, isVolatile);
N->setValueTypes(VTs);
CSEMap.InsertNode(N, IP);
AllNodes.push_back(N);
return SDOperand(N, 0);
}
SDOperand SelectionDAG::getTruncStore(SDOperand Chain, SDOperand Value,
SDOperand Ptr, const Value *SV,
int SVOffset, MVT::ValueType SVT,
bool isVolatile) {
MVT::ValueType VT = Value.getValueType();
bool isTrunc = VT != SVT;
assert(VT > SVT && "Not a truncation?");
assert(MVT::isInteger(VT) == MVT::isInteger(SVT) &&
"Can't do FP-INT conversion!");
// FIXME: Alignment == 1 for now.
unsigned Alignment = 1;
SDVTList VTs = getVTList(MVT::Other);
SDOperand Undef = getNode(ISD::UNDEF, Ptr.getValueType());
SDOperand Ops[] = { Chain, Value, Ptr, Undef };
SelectionDAGCSEMap::NodeID ID(ISD::STORE, VTs, Ops, 4);
ID.AddInteger(ISD::UNINDEXED);
ID.AddInteger(isTrunc);
ID.AddInteger(SVT);
ID.AddPointer(SV);
ID.AddInteger(SVOffset);
ID.AddInteger(Alignment);
ID.AddInteger(isVolatile);
void *IP = 0;
if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
return SDOperand(E, 0);
SDNode *N = new StoreSDNode(Chain, Value, Ptr, Undef, ISD::UNINDEXED, isTrunc,
SVT, SV, SVOffset, Alignment, isVolatile);
N->setValueTypes(VTs);
CSEMap.InsertNode(N, IP);
AllNodes.push_back(N);
@ -1610,26 +1668,6 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
switch (Opcode) {
default: break;
case ISD::TRUNCSTORE: {
assert(NumOps == 5 && "TRUNCSTORE takes 5 operands!");
MVT::ValueType EVT = cast<VTSDNode>(Ops[4])->getVT();
#if 0 // FIXME: If the target supports EVT natively, convert to a truncate/store
// If this is a truncating store of a constant, convert to the desired type
// and store it instead.
if (isa<Constant>(Ops[0])) {
SDOperand Op = getNode(ISD::TRUNCATE, EVT, N1);
if (isa<Constant>(Op))
N1 = Op;
}
// Also for ConstantFP?
#endif
if (Ops[0].getValueType() == EVT) // Normal store?
return getStore(Ops[0], Ops[1], Ops[2], Ops[3]);
assert(Ops[1].getValueType() > EVT && "Not a truncation?");
assert(MVT::isInteger(Ops[1].getValueType()) == MVT::isInteger(EVT) &&
"Can't do FP-INT conversion!");
break;
}
case ISD::SELECT_CC: {
assert(NumOps == 5 && "SELECT_CC takes 5 operands!");
assert(Ops[0].getValueType() == Ops[1].getValueType() &&
@ -2609,7 +2647,6 @@ const char *SDNode::getOperationName(const SelectionDAG *G) const {
case ISD::LOAD: return "load";
case ISD::STORE: return "store";
case ISD::VLOAD: return "vload";
case ISD::TRUNCSTORE: return "truncstore";
case ISD::VAARG: return "vaarg";
case ISD::VACOPY: return "vacopy";
case ISD::VAEND: return "vaend";

12
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
View File

@ -1393,8 +1393,8 @@ void SelectionDAGLowering::visitStore(StoreInst &I) {
Value *SrcV = I.getOperand(0);
SDOperand Src = getValue(SrcV);
SDOperand Ptr = getValue(I.getOperand(1));
DAG.setRoot(DAG.getStore(getRoot(), Src, Ptr,
DAG.getSrcValue(I.getOperand(1))));
DAG.setRoot(DAG.getStore(getRoot(), Src, Ptr, I.getOperand(1),
I.isVolatile()));
}
/// IntrinsicCannotAccessMemory - Return true if the specified intrinsic cannot
@ -2287,7 +2287,7 @@ void SelectionDAGLowering::visitInlineAsm(CallInst &I) {
for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i)
OutChains.push_back(DAG.getStore(Chain, StoresToEmit[i].first,
getValue(StoresToEmit[i].second),
DAG.getSrcValue(StoresToEmit[i].second)));
StoresToEmit[i].second, 0));
if (!OutChains.empty())
Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
&OutChains[0], OutChains.size());
@ -2864,7 +2864,7 @@ void SelectionDAGLowering::visitMemIntrinsic(CallInst &I, unsigned Op) {
SDOperand Value = getMemsetValue(Op2, VT, DAG);
SDOperand Store = DAG.getStore(getRoot(), Value,
getMemBasePlusOffset(Op1, Offset, DAG, TLI),
DAG.getSrcValue(I.getOperand(1), Offset));
I.getOperand(1), Offset);
OutChains.push_back(Store);
Offset += VTSize;
}
@ -2910,7 +2910,7 @@ void SelectionDAGLowering::visitMemIntrinsic(CallInst &I, unsigned Op) {
Store =
DAG.getStore(Chain, Value,
getMemBasePlusOffset(Op1, DstOff, DAG, TLI),
DAG.getSrcValue(I.getOperand(1), DstOff));
I.getOperand(1), DstOff);
} else {
Value = DAG.getLoad(VT, getRoot(),
getMemBasePlusOffset(Op2, SrcOff, DAG, TLI),
@ -2919,7 +2919,7 @@ void SelectionDAGLowering::visitMemIntrinsic(CallInst &I, unsigned Op) {
Store =
DAG.getStore(Chain, Value,
getMemBasePlusOffset(Op1, DstOff, DAG, TLI),
DAG.getSrcValue(I.getOperand(1), DstOff));
I.getOperand(1), DstOff);
}
OutChains.push_back(Store);
SrcOff += VTSize;

1
lib/CodeGen/SelectionDAG/TargetLowering.cpp
View File

@ -28,6 +28,7 @@ TargetLowering::TargetLowering(TargetMachine &tm)
// All operations default to being supported.
memset(OpActions, 0, sizeof(OpActions));
memset(LoadXActions, 0, sizeof(LoadXActions));
memset(&StoreXActions, 0, sizeof(StoreXActions));
IsLittleEndian = TD->isLittleEndian();
UsesGlobalOffsetTable = false;

10
lib/Target/ARM/ARMISelDAGToDAG.cpp
View File

@ -309,8 +309,7 @@ static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) {
unsigned ArgOffset = Layout.getOffset(i);
SDOperand PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff,
DAG.getSrcValue(NULL)));
MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
}
if (!MemOpChains.empty())
Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
@ -490,7 +489,9 @@ static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG,
// memory location argument.
MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), Op.getOperand(2));
SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2));
return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV->getValue(),
SV->getOffset());
}
static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
@ -566,8 +567,7 @@ static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
MF.addLiveIn(REGS[RegNo], VReg);
SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::i32);
SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN,
DAG.getSrcValue(NULL));
SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
MemOps.push_back(Store);
}
Root = DAG.getNode(ISD::TokenFactor, MVT::Other,&MemOps[0],MemOps.size());

39
lib/Target/Alpha/AlphaISelLowering.cpp
View File

@ -59,12 +59,12 @@ AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM)
setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote);
setLoadXAction(ISD::SEXTLOAD, MVT::i8, Expand);
setLoadXAction(ISD::SEXTLOAD, MVT::i16, Expand);
setStoreXAction(MVT::i1, Promote);
// setOperationAction(ISD::BRIND, MVT::i64, Expand);
setOperationAction(ISD::BR_CC, MVT::Other, Expand);
setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
setOperationAction(ISD::TRUNCSTORE, MVT::i1, Promote);
setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
@ -267,14 +267,14 @@ static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
int FI = MFI->CreateFixedObject(8, -8 * (6 - i));
if (i == 0) VarArgsBase = FI;
SDOperand SDFI = DAG.getFrameIndex(FI, MVT::i64);
LS.push_back(DAG.getStore(Root, argt, SDFI, DAG.getSrcValue(NULL)));
LS.push_back(DAG.getStore(Root, argt, SDFI, NULL, 0));
if (MRegisterInfo::isPhysicalRegister(args_float[i]))
args_float[i] = AddLiveIn(MF, args_float[i], &Alpha::F8RCRegClass);
argt = DAG.getCopyFromReg(Root, args_float[i], MVT::f64);
FI = MFI->CreateFixedObject(8, - 8 * (12 - i));
SDFI = DAG.getFrameIndex(FI, MVT::i64);
LS.push_back(DAG.getStore(Root, argt, SDFI, DAG.getSrcValue(NULL)));
LS.push_back(DAG.getStore(Root, argt, SDFI, NULL, 0));
}
//Set up a token factor with all the stack traffic
@ -414,7 +414,7 @@ SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
DAG.getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i64);
SDOperand ST = DAG.getStore(DAG.getEntryNode(),
Op.getOperand(0), FI, DAG.getSrcValue(0));
Op.getOperand(0), FI, NULL, 0);
LD = DAG.getLoad(MVT::f64, ST, FI, NULL, 0);
}
SDOperand FP = DAG.getNode(isDouble?AlphaISD::CVTQT_:AlphaISD::CVTQS_,
@ -436,8 +436,7 @@ SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
int FrameIdx =
DAG.getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i64);
SDOperand ST = DAG.getStore(DAG.getEntryNode(),
src, FI, DAG.getSrcValue(0));
SDOperand ST = DAG.getStore(DAG.getEntryNode(), src, FI, NULL, 0);
return DAG.getLoad(MVT::i64, ST, FI, NULL, 0);
}
}
@ -531,10 +530,8 @@ SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
SDOperand NewOffset = DAG.getNode(ISD::ADD, MVT::i64, Offset,
DAG.getConstant(8, MVT::i64));
SDOperand Update = DAG.getNode(ISD::TRUNCSTORE, MVT::Other,
Offset.getValue(1), NewOffset,
Tmp, DAG.getSrcValue(0),
DAG.getValueType(MVT::i32));
SDOperand Update = DAG.getTruncStore(Offset.getValue(1), NewOffset,
Tmp, NULL, 0, MVT::i32);
SDOperand Result;
if (Op.getValueType() == MVT::i32)
@ -548,33 +545,33 @@ SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
SDOperand Chain = Op.getOperand(0);
SDOperand DestP = Op.getOperand(1);
SDOperand SrcP = Op.getOperand(2);
SDOperand DestS = Op.getOperand(3);
SrcValueSDNode *DestS = cast<SrcValueSDNode>(Op.getOperand(3));
SrcValueSDNode *SrcS = cast<SrcValueSDNode>(Op.getOperand(4));
SDOperand Val = DAG.getLoad(getPointerTy(), Chain, SrcP,
SrcS->getValue(), SrcS->getOffset());
SDOperand Result = DAG.getStore(Val.getValue(1), Val, DestP, DestS);
SDOperand Result = DAG.getStore(Val.getValue(1), Val, DestP, DestS->getValue(),
DestS->getOffset());
SDOperand NP = DAG.getNode(ISD::ADD, MVT::i64, SrcP,
DAG.getConstant(8, MVT::i64));
Val = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Result, NP, NULL,0, MVT::i32);
SDOperand NPD = DAG.getNode(ISD::ADD, MVT::i64, DestP,
DAG.getConstant(8, MVT::i64));
return DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Val.getValue(1),
Val, NPD, DAG.getSrcValue(0),DAG.getValueType(MVT::i32));
return DAG.getTruncStore(Val.getValue(1), Val, NPD, NULL, 0, MVT::i32);
}
case ISD::VASTART: {
SDOperand Chain = Op.getOperand(0);
SDOperand VAListP = Op.getOperand(1);
SDOperand VAListS = Op.getOperand(2);
SrcValueSDNode *VAListS = cast<SrcValueSDNode>(Op.getOperand(3));
// vastart stores the address of the VarArgsBase and VarArgsOffset
SDOperand FR = DAG.getFrameIndex(VarArgsBase, MVT::i64);
SDOperand S1 = DAG.getStore(Chain, FR, VAListP, VAListS);
SDOperand S1 = DAG.getStore(Chain, FR, VAListP, VAListS->getValue(),
VAListS->getOffset());
SDOperand SA2 = DAG.getNode(ISD::ADD, MVT::i64, VAListP,
DAG.getConstant(8, MVT::i64));
return DAG.getNode(ISD::TRUNCSTORE, MVT::Other, S1,
DAG.getConstant(VarArgsOffset, MVT::i64), SA2,
DAG.getSrcValue(0), DAG.getValueType(MVT::i32));
return DAG.getTruncStore(S1, DAG.getConstant(VarArgsOffset, MVT::i64),
SA2, NULL, 0, MVT::i32);
}
}

18
lib/Target/Alpha/AlphaInstrInfo.td
View File

@ -501,17 +501,17 @@ def LDWU : MForm<0x0C, 0, 1, "ldwu $RA,$DISP($RB)",
def LDWUr : MForm<0x0C, 0, 1, "ldwu $RA,$DISP($RB)\t\t!gprellow",
[(set GPRC:$RA, (zextloadi16 (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB)))], s_ild>;
def STB : MForm<0x0E, 1, 0, "stb $RA,$DISP($RB)",
[(truncstore GPRC:$RA, (add GPRC:$RB, immSExt16:$DISP), i8)], s_ist>;
[(truncstorei8 GPRC:$RA, (add GPRC:$RB, immSExt16:$DISP))], s_ist>;
def STBr : MForm<0x0E, 1, 0, "stb $RA,$DISP($RB)\t\t!gprellow",
[(truncstore GPRC:$RA, (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB), i8)], s_ist>;
[(truncstorei8 GPRC:$RA, (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB))], s_ist>;
def STW : MForm<0x0D, 1, 0, "stw $RA,$DISP($RB)",
[(truncstore GPRC:$RA, (add GPRC:$RB, immSExt16:$DISP), i16)], s_ist>;
[(truncstorei16 GPRC:$RA, (add GPRC:$RB, immSExt16:$DISP))], s_ist>;
def STWr : MForm<0x0D, 1, 0, "stw $RA,$DISP($RB)\t\t!gprellow",
[(truncstore GPRC:$RA, (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB), i16)], s_ist>;
[(truncstorei16 GPRC:$RA, (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB))], s_ist>;
def STL : MForm<0x2C, 1, 0, "stl $RA,$DISP($RB)",
[(truncstore GPRC:$RA, (add GPRC:$RB, immSExt16:$DISP), i32)], s_ist>;
[(truncstorei32 GPRC:$RA, (add GPRC:$RB, immSExt16:$DISP))], s_ist>;
def STLr : MForm<0x2C, 1, 0, "stl $RA,$DISP($RB)\t\t!gprellow",
[(truncstore GPRC:$RA, (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB), i32)], s_ist>;
[(truncstorei32 GPRC:$RA, (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB))], s_ist>;
def STQ : MForm<0x2D, 1, 0, "stq $RA,$DISP($RB)",
[(store GPRC:$RA, (add GPRC:$RB, immSExt16:$DISP))], s_ist>;
def STQr : MForm<0x2D, 1, 0, "stq $RA,$DISP($RB)\t\t!gprellow",
@ -609,11 +609,11 @@ def : Pat<(store F8RC:$DATA, GPRC:$addr),
(STT F8RC:$DATA, 0, GPRC:$addr)>;
def : Pat<(store F4RC:$DATA, GPRC:$addr),
(STS F4RC:$DATA, 0, GPRC:$addr)>;
def : Pat<(truncstore GPRC:$DATA, GPRC:$addr, i32),
def : Pat<(truncstorei32 GPRC:$DATA, GPRC:$addr),
(STL GPRC:$DATA, 0, GPRC:$addr)>;
def : Pat<(truncstore GPRC:$DATA, GPRC:$addr, i16),
def : Pat<(truncstorei16 GPRC:$DATA, GPRC:$addr),
(STW GPRC:$DATA, 0, GPRC:$addr)>;
def : Pat<(truncstore GPRC:$DATA, GPRC:$addr, i8),
def : Pat<(truncstorei8 GPRC:$DATA, GPRC:$addr),
(STB GPRC:$DATA, 0, GPRC:$addr)>;

14
lib/Target/IA64/IA64ISelDAGToDAG.cpp
View File

@ -493,15 +493,15 @@ SDNode *IA64DAGToDAGISel::Select(SDOperand Op) {
Address, Chain);
}
case ISD::TRUNCSTORE:
case ISD::STORE: {
SDOperand Address = N->getOperand(2);
SDOperand Chain = N->getOperand(0);
StoreSDNode *ST = cast<StoreSDNode>(N);
SDOperand Address = ST->getBasePtr();
SDOperand Chain = ST->getChain();
AddToISelQueue(Address);
AddToISelQueue(Chain);
unsigned Opc;
if (N->getOpcode() == ISD::STORE) {
if (ISD::isNON_TRUNCStore(N)) {
switch (N->getOperand(1).getValueType()) {
default: assert(0 && "unknown type in store");
case MVT::i1: { // this is a bool
@ -510,7 +510,7 @@ SDNode *IA64DAGToDAGISel::Select(SDOperand Op) {
SDOperand Initial = CurDAG->getCopyFromReg(Chain, IA64::r0, MVT::i64);
Chain = Initial.getValue(1);
// then load 1 into the same reg iff the predicate to store is 1
SDOperand Tmp = N->getOperand(1);
SDOperand Tmp = ST->getValue();
AddToISelQueue(Tmp);
Tmp = SDOperand(CurDAG->getTargetNode(IA64::TPCADDS, MVT::i64, Initial,
CurDAG->getConstant(1, MVT::i64),
@ -520,8 +520,8 @@ SDNode *IA64DAGToDAGISel::Select(SDOperand Op) {
case MVT::i64: Opc = IA64::ST8; break;
case MVT::f64: Opc = IA64::STF8; break;
}
} else { //ISD::TRUNCSTORE
switch(cast<VTSDNode>(N->getOperand(4))->getVT()) {
} else { // Truncating store
switch(ST->getStoredVT()) {
default: assert(0 && "unknown type in truncstore");
case MVT::i8: Opc = IA64::ST1; break;
case MVT::i16: Opc = IA64::ST2; break;

10
lib/Target/IA64/IA64ISelLowering.cpp
View File

@ -331,7 +331,7 @@ IA64TargetLowering::LowerCallTo(SDOperand Chain,
Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes, getPointerTy()));
SDOperand StackPtr, NullSV;
SDOperand StackPtr;
std::vector<SDOperand> Stores;
std::vector<SDOperand> Converts;
std::vector<SDOperand> RegValuesToPass;
@ -383,11 +383,10 @@ IA64TargetLowering::LowerCallTo(SDOperand Chain,
if(ValToStore.Val) {
if(!StackPtr.Val) {
StackPtr = DAG.getRegister(IA64::r12, MVT::i64);
NullSV = DAG.getSrcValue(NULL);
}
SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
PtrOff = DAG.getNode(ISD::ADD, MVT::i64, StackPtr, PtrOff);
Stores.push_back(DAG.getStore(Chain, ValToStore, PtrOff, NullSV));
Stores.push_back(DAG.getStore(Chain, ValToStore, PtrOff, NULL, 0));
ArgOffset += ObjSize;
}
@ -592,7 +591,7 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG) {
VT));
// Store the incremented VAList to the legalized pointer
VAIncr = DAG.getStore(VAList.getValue(1), VAIncr,
Op.getOperand(1), Op.getOperand(2));
Op.getOperand(1), SV->getValue(), SV->getOffset());
// Load the actual argument out of the pointer VAList
return DAG.getLoad(Op.getValueType(), VAIncr, VAList, NULL, 0);
}
@ -600,8 +599,9 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG) {
// vastart just stores the address of the VarArgsFrameIndex slot into the
// memory location argument.
SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i64);
SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2));
return DAG.getStore(Op.getOperand(0), FR,
Op.getOperand(1), Op.getOperand(2));
Op.getOperand(1), SV->getValue(), SV->getOffset());
}
}
}

24
lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -47,6 +47,9 @@ PPCTargetLowering::PPCTargetLowering(TargetMachine &TM)
setLoadXAction(ISD::SEXTLOAD, MVT::i1, Expand);
setLoadXAction(ISD::SEXTLOAD, MVT::i8, Expand);
// PowerPC does not have truncstore for i1.
setStoreXAction(MVT::i1, Promote);
setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
@ -117,9 +120,6 @@ PPCTargetLowering::PPCTargetLowering(TargetMachine &TM)
setOperationAction(ISD::BIT_CONVERT, MVT::i64, Expand);
setOperationAction(ISD::BIT_CONVERT, MVT::f64, Expand);
// PowerPC does not have truncstore for i1.
setOperationAction(ISD::TRUNCSTORE, MVT::i1, Promote);
// We cannot sextinreg(i1). Expand to shifts.
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
@ -743,7 +743,9 @@ static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG,
// memory location argument.
MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), Op.getOperand(2));
SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2));
return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV->getValue(),
SV->getOffset());
}
static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
@ -898,8 +900,7 @@ static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
MF.addLiveIn(GPR[GPR_idx], VReg);
SDOperand Val = DAG.getCopyFromReg(Root, VReg, PtrVT);
SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN,
DAG.getSrcValue(NULL));
SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
MemOps.push_back(Store);
// Increment the address by four for the next argument to store
SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8, PtrVT);
@ -1033,8 +1034,7 @@ static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) {
if (GPR_idx != NumGPRs) {
RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
} else {
MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff,
DAG.getSrcValue(NULL)));
MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
}
ArgOffset += PtrByteSize;
break;
@ -1044,8 +1044,7 @@ static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) {
RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
if (isVarArg) {
SDOperand Store = DAG.getStore(Chain, Arg, PtrOff,
DAG.getSrcValue(NULL));
SDOperand Store = DAG.getStore(Chain, Arg, PtrOff, NULL, 0);
MemOpChains.push_back(Store);
// Float varargs are always shadowed in available integer registers
@ -1071,8 +1070,7 @@ static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) {
++GPR_idx;
}
} else {
MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff,
DAG.getSrcValue(NULL)));
MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
}
if (isPPC64)
ArgOffset += 8;
@ -2119,7 +2117,7 @@ static SDOperand LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG) {
// Store the input value into Value#0 of the stack slot.
SDOperand Store = DAG.getStore(DAG.getEntryNode(),
Op.getOperand(0), FIdx,DAG.getSrcValue(NULL));
Op.getOperand(0), FIdx, NULL, 0);
// Load it out.
return DAG.getLoad(Op.getValueType(), Store, FIdx, NULL, 0);
}

12
lib/Target/PowerPC/PPCInstr64Bit.td
View File

@ -304,24 +304,24 @@ def STDX_32 : XForm_8<31, 149, (ops GPRC:$rT, memrr:$dst),
// Truncating stores.
def STB8 : DForm_3<38, (ops G8RC:$rS, memri:$src),
"stb $rS, $src", LdStGeneral,
[(truncstore G8RC:$rS, iaddr:$src, i8)]>;
[(truncstorei8 G8RC:$rS, iaddr:$src)]>;
def STH8 : DForm_3<44, (ops G8RC:$rS, memri:$src),
"sth $rS, $src", LdStGeneral,
[(truncstore G8RC:$rS, iaddr:$src, i16)]>;
[(truncstorei16 G8RC:$rS, iaddr:$src)]>;
def STW8 : DForm_3<36, (ops G8RC:$rS, memri:$src),
"stw $rS, $src", LdStGeneral,
[(truncstore G8RC:$rS, iaddr:$src, i32)]>;
[(truncstorei32 G8RC:$rS, iaddr:$src)]>;
def STBX8 : XForm_8<31, 215, (ops G8RC:$rS, memrr:$dst),
"stbx $rS, $dst", LdStGeneral,
[(truncstore G8RC:$rS, xaddr:$dst, i8)]>,
[(truncstorei8 G8RC:$rS, xaddr:$dst)]>,
PPC970_DGroup_Cracked;
def STHX8 : XForm_8<31, 407, (ops G8RC:$rS, memrr:$dst),
"sthx $rS, $dst", LdStGeneral,
[(truncstore G8RC:$rS, xaddr:$dst, i16)]>,
[(truncstorei16 G8RC:$rS, xaddr:$dst)]>,
PPC970_DGroup_Cracked;
def STWX8 : XForm_8<31, 151, (ops G8RC:$rS, memrr:$dst),
"stwx $rS, $dst", LdStGeneral,
[(truncstore G8RC:$rS, xaddr:$dst, i32)]>,
[(truncstorei32 G8RC:$rS, xaddr:$dst)]>,
PPC970_DGroup_Cracked;
}

8
lib/Target/PowerPC/PPCInstrInfo.td
View File

@ -431,10 +431,10 @@ def LIS : DForm_2_r0<15, (ops GPRC:$rD, symbolHi:$imm),
let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
def STB : DForm_3<38, (ops GPRC:$rS, memri:$src),
"stb $rS, $src", LdStGeneral,
[(truncstore GPRC:$rS, iaddr:$src, i8)]>;
[(truncstorei8 GPRC:$rS, iaddr:$src)]>;
def STH : DForm_3<44, (ops GPRC:$rS, memri:$src),
"sth $rS, $src", LdStGeneral,
[(truncstore GPRC:$rS, iaddr:$src, i16)]>;
[(truncstorei16 GPRC:$rS, iaddr:$src)]>;
def STW : DForm_3<36, (ops GPRC:$rS, memri:$src),
"stw $rS, $src", LdStGeneral,
[(store GPRC:$rS, iaddr:$src)]>;
@ -553,11 +553,11 @@ def SRAW : XForm_6<31, 792, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
def STBX : XForm_8<31, 215, (ops GPRC:$rS, memrr:$dst),
"stbx $rS, $dst", LdStGeneral,
[(truncstore GPRC:$rS, xaddr:$dst, i8)]>,
[(truncstorei8 GPRC:$rS, xaddr:$dst)]>,
PPC970_DGroup_Cracked;
def STHX : XForm_8<31, 407, (ops GPRC:$rS, memrr:$dst),
"sthx $rS, $dst", LdStGeneral,
[(truncstore GPRC:$rS, xaddr:$dst, i16)]>,
[(truncstorei16 GPRC:$rS, xaddr:$dst)]>,
PPC970_DGroup_Cracked;
def STWX : XForm_8<31, 151, (ops GPRC:$rS, memrr:$dst),
"stwx $rS, $dst", LdStGeneral,

13
lib/Target/Sparc/SparcISelDAGToDAG.cpp
View File

@ -436,8 +436,7 @@ SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
OutChains.push_back(DAG.getStore(DAG.getRoot(),
Arg, FIPtr, DAG.getSrcValue(0)));
OutChains.push_back(DAG.getStore(DAG.getRoot(), Arg, FIPtr, NULL, 0));
ArgOffset += 4;
}
}
@ -504,7 +503,7 @@ SparcTargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(ArgsSize, getPointerTy()));
SDOperand StackPtr, NullSV;
SDOperand StackPtr;
std::vector<SDOperand> Stores;
std::vector<SDOperand> RegValuesToPass;
unsigned ArgOffset = 68;
@ -584,11 +583,10 @@ SparcTargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
if (ValToStore.Val) {
if (!StackPtr.Val) {
StackPtr = DAG.getRegister(SP::O6, MVT::i32);
NullSV = DAG.getSrcValue(NULL);
}
SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
Stores.push_back(DAG.getStore(Chain, ValToStore, PtrOff, NullSV));
Stores.push_back(DAG.getStore(Chain, ValToStore, PtrOff, NULL, 0));
}
ArgOffset += ObjSize;
}
@ -785,8 +783,9 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG) {
SDOperand Offset = DAG.getNode(ISD::ADD, MVT::i32,
DAG.getRegister(SP::I6, MVT::i32),
DAG.getConstant(VarArgsFrameOffset, MVT::i32));
SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2));
return DAG.getStore(Op.getOperand(0), Offset,
Op.getOperand(1), Op.getOperand(2));
Op.getOperand(1), SV->getValue(), SV->getOffset());
}
case ISD::VAARG: {
SDNode *Node = Op.Val;
@ -802,7 +801,7 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG) {
getPointerTy()));
// Store the incremented VAList to the legalized pointer
InChain = DAG.getStore(VAList.getValue(1), NextPtr,
VAListPtr, Node->getOperand(2));
VAListPtr, SV->getValue(), SV->getOffset());
// Load the actual argument out of the pointer VAList, unless this is an
// f64 load.
if (VT != MVT::f64) {

12
lib/Target/Sparc/SparcInstrInfo.td
View File

@ -338,19 +338,19 @@ def LDDFri : F3_2<3, 0b100011,
def STBrr : F3_1<3, 0b000101,
(ops MEMrr:$addr, IntRegs:$src),
"stb $src, [$addr]",
[(truncstore IntRegs:$src, ADDRrr:$addr, i8)]>;
[(truncstorei8 IntRegs:$src, ADDRrr:$addr)]>;
def STBri : F3_2<3, 0b000101,
(ops MEMri:$addr, IntRegs:$src),
"stb $src, [$addr]",
[(truncstore IntRegs:$src, ADDRri:$addr, i8)]>;
[(truncstorei8 IntRegs:$src, ADDRri:$addr)]>;
def STHrr : F3_1<3, 0b000110,
(ops MEMrr:$addr, IntRegs:$src),
"sth $src, [$addr]",
[(truncstore IntRegs:$src, ADDRrr:$addr, i16)]>;
[(truncstorei16 IntRegs:$src, ADDRrr:$addr)]>;
def STHri : F3_2<3, 0b000110,
(ops MEMri:$addr, IntRegs:$src),
"sth $src, [$addr]",
[(truncstore IntRegs:$src, ADDRri:$addr, i16)]>;
[(truncstorei16 IntRegs:$src, ADDRri:$addr)]>;
def STrr : F3_1<3, 0b000100,
(ops MEMrr:$addr, IntRegs:$src),
"st $src, [$addr]",
@ -772,7 +772,7 @@ def : Pat<(i32 (zextloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
def : Pat<(i32 (zextloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>;
// truncstore bool -> truncstore byte.
def : Pat<(truncstore IntRegs:$src, ADDRrr:$addr, i1),
def : Pat<(truncstorei1 IntRegs:$src, ADDRrr:$addr),
(STBrr ADDRrr:$addr, IntRegs:$src)>;
def : Pat<(truncstore IntRegs:$src, ADDRri:$addr, i1),
def : Pat<(truncstorei1 IntRegs:$src, ADDRri:$addr),
(STBri ADDRri:$addr, IntRegs:$src)>;

52
lib/Target/TargetSelectionDAG.td
View File

@ -164,10 +164,6 @@ def SDTStore : SDTypeProfile<0, 2, [ // store
SDTCisPtrTy<1>
]>;
def SDTTruncStore : SDTypeProfile<0, 4, [ // truncstore
SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>
]>;
def SDTVecShuffle : SDTypeProfile<1, 3, [
SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisIntVectorOfSameSize<3, 0>
]>;
@ -299,11 +295,10 @@ def brind : SDNode<"ISD::BRIND" , SDTBrind, [SDNPHasChain]>;
def br : SDNode<"ISD::BR" , SDTBr, [SDNPHasChain]>;
def ret : SDNode<"ISD::RET" , SDTRet, [SDNPHasChain]>;
// Do not use ld directly. Use load, extload, sextload, zextload (see below).
// Do not use ld, st directly. Use load, extload, sextload, zextload, store,
// and truncst (see below).
def ld : SDNode<"ISD::LOAD" , SDTLoad, [SDNPHasChain]>;
def store : SDNode<"ISD::STORE" , SDTStore, [SDNPHasChain]>;
def truncst : SDNode<"ISD::TRUNCSTORE" , SDTTruncStore, [SDNPHasChain]>;
def st : SDNode<"ISD::STORE" , SDTStore, [SDNPHasChain]>;
def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>;
def build_vector : SDNode<"ISD::BUILD_VECTOR", SDTypeProfile<1, 0, []>, []>;
@ -408,7 +403,7 @@ def load : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
return ISD::isNON_EXTLoad(N);
}]>;
// extending load & truncstore fragments.
// extending load fragments.
def extloadi1 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
if (ISD::isEXTLoad(N))
return cast<LoadSDNode>(N)->getLoadedVT() == MVT::i1;
@ -477,9 +472,42 @@ def zextloadi32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
return false;
}]>;
def truncstore : PatFrag<(ops node:$val, node:$ptr, node:$vt),
(truncst node:$val, node:$ptr, srcvalue:$dummy,
node:$vt)>;
def store : PatFrag<(ops node:$val, node:$ptr),
(st node:$val, node:$ptr), [{
return ISD::isNON_TRUNCStore(N);
}]>;
// truncstore fragments.
def truncstorei1 : PatFrag<(ops node:$val, node:$ptr),
(st node:$val, node:$ptr), [{
if (ISD::isTRUNCStore(N))
return cast<StoreSDNode>(N)->getStoredVT() == MVT::i1;
return false;
}]>;
def truncstorei8 : PatFrag<(ops node:$val, node:$ptr),
(st node:$val, node:$ptr), [{
if (ISD::isTRUNCStore(N))
return cast<StoreSDNode>(N)->getStoredVT() == MVT::i8;
return false;
}]>;
def truncstorei16 : PatFrag<(ops node:$val, node:$ptr),
(st node:$val, node:$ptr), [{
if (ISD::isTRUNCStore(N))
return cast<StoreSDNode>(N)->getStoredVT() == MVT::i16;
return false;
}]>;
def truncstorei32 : PatFrag<(ops node:$val, node:$ptr),
(st node:$val, node:$ptr), [{
if (ISD::isTRUNCStore(N))
return cast<StoreSDNode>(N)->getStoredVT() == MVT::i32;
return false;
}]>;
def truncstoref32 : PatFrag<(ops node:$val, node:$ptr),
(st node:$val, node:$ptr), [{
if (ISD::isTRUNCStore(N))
return cast<StoreSDNode>(N)->getStoredVT() == MVT::f32;
return false;
}]>;
// setcc convenience fragments.
def setoeq : PatFrag<(ops node:$lhs, node:$rhs),

2
lib/Target/X86/X86ISelDAGToDAG.cpp
View File

@ -372,7 +372,7 @@ static void MoveBelowTokenFactor(SelectionDAG &DAG, SDOperand Load,
void X86DAGToDAGISel::InstructionSelectPreprocess(SelectionDAG &DAG) {
for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
E = DAG.allnodes_end(); I != E; ++I) {
if (I->getOpcode() != ISD::STORE)
if (!ISD::isNON_TRUNCStore(I))
continue;
SDOperand Chain = I->getOperand(0);
if (Chain.Val->getOpcode() != ISD::TokenFactor)

70
lib/Target/X86/X86ISelLowering.cpp
View File

@ -598,8 +598,7 @@ SDOperand X86TargetLowering::LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG) {
case MVT::f32: {
SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff,
DAG.getSrcValue(NULL)));
MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
ArgOffset += 4;
break;
}
@ -607,8 +606,7 @@ SDOperand X86TargetLowering::LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG) {
case MVT::f64: {
SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff,
DAG.getSrcValue(NULL)));
MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
ArgOffset += 8;
break;
}
@ -626,8 +624,7 @@ SDOperand X86TargetLowering::LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG) {
ArgOffset = ((ArgOffset + 15) / 16) * 16;
SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff,
DAG.getSrcValue(NULL)));
MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
ArgOffset += 16;
}
}
@ -988,8 +985,7 @@ X86TargetLowering::LowerX86_64CCCArguments(SDOperand Op, SelectionDAG &DAG) {
unsigned VReg = AddLiveIn(MF, GPR64ArgRegs[NumIntRegs],
X86::GR64RegisterClass);
SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::i64);
SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN,
DAG.getSrcValue(NULL));
SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
MemOps.push_back(Store);
FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
DAG.getConstant(8, getPointerTy()));
@ -1002,8 +998,7 @@ X86TargetLowering::LowerX86_64CCCArguments(SDOperand Op, SelectionDAG &DAG) {
unsigned VReg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs],
X86::VR128RegisterClass);
SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::v4f32);
SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN,
DAG.getSrcValue(NULL));
SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
MemOps.push_back(Store);
FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
DAG.getConstant(16, getPointerTy()));
@ -1126,8 +1121,7 @@ X86TargetLowering::LowerX86_64CCCCallTo(SDOperand Op, SelectionDAG &DAG) {
} else {
SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff,
DAG.getSrcValue(NULL)));
MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
ArgOffset += 8;
}
break;
@ -1149,8 +1143,7 @@ X86TargetLowering::LowerX86_64CCCCallTo(SDOperand Op, SelectionDAG &DAG) {
}
SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff,
DAG.getSrcValue(NULL)));
MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
if (ArgVT == MVT::f32 || ArgVT == MVT::f64)
ArgOffset += 8;
else
@ -1631,16 +1624,14 @@ SDOperand X86TargetLowering::LowerFastCCCallTo(SDOperand Op, SelectionDAG &DAG,
case MVT::f32: {
SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff,
DAG.getSrcValue(NULL)));
MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
ArgOffset += 4;
break;
}
case MVT::f64: {
SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff,
DAG.getSrcValue(NULL)));
MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
ArgOffset += 8;
break;
}
@ -1661,8 +1652,7 @@ SDOperand X86TargetLowering::LowerFastCCCallTo(SDOperand Op, SelectionDAG &DAG,
ArgOffset = ((ArgOffset + 15) / 16) * 16;
SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff,
DAG.getSrcValue(NULL)));
MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
ArgOffset += 16;
}
}
@ -1961,8 +1951,7 @@ SDOperand X86TargetLowering::LowerStdCallCCCallTo(SDOperand Op,
case MVT::f32: {
SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff,
DAG.getSrcValue(NULL)));
MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
ArgOffset += 4;
break;
}
@ -1970,8 +1959,7 @@ SDOperand X86TargetLowering::LowerStdCallCCCallTo(SDOperand Op,
case MVT::f64: {
SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff,
DAG.getSrcValue(NULL)));
MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
ArgOffset += 8;
break;
}
@ -3989,7 +3977,7 @@ SDOperand X86TargetLowering::LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
SDOperand Chain = DAG.getStore(DAG.getEntryNode(), Op.getOperand(0),
StackSlot, DAG.getSrcValue(NULL));
StackSlot, NULL, 0);
// Build the FILD
std::vector<MVT::ValueType> Tys;
@ -4050,7 +4038,7 @@ SDOperand X86TargetLowering::LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) {
SDOperand Value = Op.getOperand(0);
if (X86ScalarSSE) {
assert(Op.getValueType() == MVT::i64 && "Invalid FP_TO_SINT to lower!");
Chain = DAG.getStore(Chain, Value, StackSlot, DAG.getSrcValue(0));
Chain = DAG.getStore(Chain, Value, StackSlot, NULL, 0);
std::vector<MVT::ValueType> Tys;
Tys.push_back(MVT::f64);
Tys.push_back(MVT::Other);
@ -4366,8 +4354,7 @@ SDOperand X86TargetLowering::LowerRET(SDOperand Op, SelectionDAG &DAG) {
MachineFunction &MF = DAG.getMachineFunction();
int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
MemLoc = DAG.getFrameIndex(SSFI, getPointerTy());
Chain = DAG.getStore(Op.getOperand(0), Value, MemLoc,
DAG.getSrcValue(0));
Chain = DAG.getStore(Op.getOperand(0), Value, MemLoc, NULL, 0);
}
std::vector<MVT::ValueType> Tys;
Tys.push_back(MVT::f64);
@ -4570,7 +4557,7 @@ SDOperand X86TargetLowering::LowerMEMSET(SDOperand Op, SelectionDAG &DAG) {
Chain = DAG.getStore(Chain, Value,
DAG.getNode(ISD::ADD, AddrVT, DstAddr,
DAG.getConstant(Offset, AddrVT)),
DAG.getSrcValue(NULL));
NULL, 0);
BytesLeft -= 4;
Offset += 4;
}
@ -4579,7 +4566,7 @@ SDOperand X86TargetLowering::LowerMEMSET(SDOperand Op, SelectionDAG &DAG) {
Chain = DAG.getStore(Chain, Value,
DAG.getNode(ISD::ADD, AddrVT, DstAddr,
DAG.getConstant(Offset, AddrVT)),
DAG.getSrcValue(NULL));
NULL, 0);
BytesLeft -= 2;
Offset += 2;
}
@ -4588,7 +4575,7 @@ SDOperand X86TargetLowering::LowerMEMSET(SDOperand Op, SelectionDAG &DAG) {
Chain = DAG.getStore(Chain, Value,
DAG.getNode(ISD::ADD, AddrVT, DstAddr,
DAG.getConstant(Offset, AddrVT)),
DAG.getSrcValue(NULL));
NULL, 0);
}
}
@ -4705,7 +4692,7 @@ SDOperand X86TargetLowering::LowerMEMCPY(SDOperand Op, SelectionDAG &DAG) {
Chain = DAG.getStore(Chain, Value,
DAG.getNode(ISD::ADD, DstVT, DstAddr,
DAG.getConstant(Offset, DstVT)),
DAG.getSrcValue(NULL));
NULL, 0);
BytesLeft -= 4;
Offset += 4;
}
@ -4718,7 +4705,7 @@ SDOperand X86TargetLowering::LowerMEMCPY(SDOperand Op, SelectionDAG &DAG) {
Chain = DAG.getStore(Chain, Value,
DAG.getNode(ISD::ADD, DstVT, DstAddr,
DAG.getConstant(Offset, DstVT)),
DAG.getSrcValue(NULL));
NULL, 0);
BytesLeft -= 2;
Offset += 2;
}
@ -4732,7 +4719,7 @@ SDOperand X86TargetLowering::LowerMEMCPY(SDOperand Op, SelectionDAG &DAG) {
Chain = DAG.getStore(Chain, Value,
DAG.getNode(ISD::ADD, DstVT, DstAddr,
DAG.getConstant(Offset, DstVT)),
DAG.getSrcValue(NULL));
NULL, 0);
}
}
@ -4758,11 +4745,14 @@ X86TargetLowering::LowerREADCYCLCECOUNTER(SDOperand Op, SelectionDAG &DAG) {
}
SDOperand X86TargetLowering::LowerVASTART(SDOperand Op, SelectionDAG &DAG) {
SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2));
if (!Subtarget->is64Bit()) {
// vastart just stores the address of the VarArgsFrameIndex slot into the
// memory location argument.
SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
return DAG.getStore(Op.getOperand(0), FR,Op.getOperand(1),Op.getOperand(2));
return DAG.getStore(Op.getOperand(0), FR,Op.getOperand(1), SV->getValue(),
SV->getOffset());
}
// __va_list_tag:
@ -4775,7 +4765,7 @@ SDOperand X86TargetLowering::LowerVASTART(SDOperand Op, SelectionDAG &DAG) {
// Store gp_offset
SDOperand Store = DAG.getStore(Op.getOperand(0),
DAG.getConstant(VarArgsGPOffset, MVT::i32),
FIN, Op.getOperand(2));
FIN, SV->getValue(), SV->getOffset());
MemOps.push_back(Store);
// Store fp_offset
@ -4783,21 +4773,23 @@ SDOperand X86TargetLowering::LowerVASTART(SDOperand Op, SelectionDAG &DAG) {
DAG.getConstant(4, getPointerTy()));
Store = DAG.getStore(Op.getOperand(0),
DAG.getConstant(VarArgsFPOffset, MVT::i32),
FIN, Op.getOperand(2));
FIN, SV->getValue(), SV->getOffset());
MemOps.push_back(Store);
// Store ptr to overflow_arg_area
FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
DAG.getConstant(4, getPointerTy()));
SDOperand OVFIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
Store = DAG.getStore(Op.getOperand(0), OVFIN, FIN, Op.getOperand(2));
Store = DAG.getStore(Op.getOperand(0), OVFIN, FIN, SV->getValue(),
SV->getOffset());
MemOps.push_back(Store);
// Store ptr to reg_save_area.
FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
DAG.getConstant(8, getPointerTy()));
SDOperand RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
Store = DAG.getStore(Op.getOperand(0), RSFIN, FIN, Op.getOperand(2));
Store = DAG.getStore(Op.getOperand(0), RSFIN, FIN, SV->getValue(),
SV->getOffset());
MemOps.push_back(Store);
return DAG.getNode(ISD::TokenFactor, MVT::Other, &MemOps[0], MemOps.size());
}

2
lib/Target/X86/X86InstrFPStack.td
View File

@ -366,7 +366,7 @@ def FpILD64m : FpI<(ops RFP:$dst, i64mem:$src), ZeroArgFP,
[(set RFP:$dst, (X86fild addr:$src, i64))]>;
def FpST32m : FpI<(ops f32mem:$op, RFP:$src), OneArgFP,
[(truncstore RFP:$src, addr:$op, f32)]>;
[(truncstoref32 RFP:$src, addr:$op)]>;
def FpST64m : FpI<(ops f64mem:$op, RFP:$src), OneArgFP,
[(store RFP:$src, addr:$op)]>;

4
lib/Target/X86/X86InstrInfo.td
View File

@ -2512,9 +2512,9 @@ def : Pat<(subc GR32:$src1, imm:$src2),
def : Pat<(subc GR32:$src1, i32immSExt8:$src2),
(SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
def : Pat<(truncstore (i8 imm:$src), addr:$dst, i1),
def : Pat<(truncstorei1 (i8 imm:$src), addr:$dst),
(MOV8mi addr:$dst, imm:$src)>;
def : Pat<(truncstore GR8:$src, addr:$dst, i1),
def : Pat<(truncstorei1 GR8:$src, addr:$dst),
(MOV8mr addr:$dst, GR8:$src)>;
// Comparisons.