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https://github.com/RPCS3/llvm-mirror.git
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AMDGPU: Un-xfail and add tests
Un XFAIL a few tests plus a few more I had lying around in my tree, which seem to all work now but I don't see tests that quite test the same things. llvm-svn: 273655
This commit is contained in:
Matt Arsenault
parent
c72c584a96
commit
fe796a3979
121
test/CodeGen/AMDGPU/cf-loop-on-constant.ll
Normal file
121
test/CodeGen/AMDGPU/cf-loop-on-constant.ll
Normal file
@ -0,0 +1,121 @@
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; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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; RUN: llc -march=amdgcn -verify-machineinstrs -O0 < %s
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; GCN-LABEL: {{^}}test_loop:
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; GCN: [[LABEL:BB[0-9+]_[0-9]+]]:
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; GCN: ds_read_b32
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; GCN: ds_write_b32
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; GCN: s_branch [[LABEL]]
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; GCN: s_endpgm
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define void @test_loop(float addrspace(3)* %ptr, i32 %n) nounwind {
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entry:
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%cmp = icmp eq i32 %n, -1
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br i1 %cmp, label %for.exit, label %for.body
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for.exit:
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ret void
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for.body:
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%indvar = phi i32 [ %inc, %for.body ], [ 0, %entry ]
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%tmp = add i32 %indvar, 32
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%arrayidx = getelementptr float, float addrspace(3)* %ptr, i32 %tmp
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%vecload = load float, float addrspace(3)* %arrayidx, align 4
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%add = fadd float %vecload, 1.0
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store float %add, float addrspace(3)* %arrayidx, align 8
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%inc = add i32 %indvar, 1
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br label %for.body
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}
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; GCN-LABEL: @loop_const_true
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; GCN: [[LABEL:BB[0-9+]_[0-9]+]]:
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; GCN: ds_read_b32
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; GCN: ds_write_b32
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; GCN: s_branch [[LABEL]]
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define void @loop_const_true(float addrspace(3)* %ptr, i32 %n) nounwind {
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entry:
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br label %for.body
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for.exit:
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ret void
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for.body:
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%indvar = phi i32 [ %inc, %for.body ], [ 0, %entry ]
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%tmp = add i32 %indvar, 32
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%arrayidx = getelementptr float, float addrspace(3)* %ptr, i32 %tmp
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%vecload = load float, float addrspace(3)* %arrayidx, align 4
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%add = fadd float %vecload, 1.0
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store float %add, float addrspace(3)* %arrayidx, align 8
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%inc = add i32 %indvar, 1
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br i1 true, label %for.body, label %for.exit
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}
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; GCN-LABEL: {{^}}loop_const_false:
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; GCN-NOT: s_branch
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; GCN: s_endpgm
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define void @loop_const_false(float addrspace(3)* %ptr, i32 %n) nounwind {
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entry:
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br label %for.body
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for.exit:
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ret void
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; XXX - Should there be an S_ENDPGM?
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for.body:
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%indvar = phi i32 [ %inc, %for.body ], [ 0, %entry ]
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%tmp = add i32 %indvar, 32
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%arrayidx = getelementptr float, float addrspace(3)* %ptr, i32 %tmp
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%vecload = load float, float addrspace(3)* %arrayidx, align 4
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%add = fadd float %vecload, 1.0
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store float %add, float addrspace(3)* %arrayidx, align 8
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%inc = add i32 %indvar, 1
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br i1 false, label %for.body, label %for.exit
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}
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; GCN-LABEL: {{^}}loop_const_undef:
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; GCN-NOT: s_branch
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; GCN: s_endpgm
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define void @loop_const_undef(float addrspace(3)* %ptr, i32 %n) nounwind {
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entry:
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br label %for.body
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for.exit:
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ret void
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; XXX - Should there be an s_endpgm?
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for.body:
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%indvar = phi i32 [ %inc, %for.body ], [ 0, %entry ]
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%tmp = add i32 %indvar, 32
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%arrayidx = getelementptr float, float addrspace(3)* %ptr, i32 %tmp
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%vecload = load float, float addrspace(3)* %arrayidx, align 4
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%add = fadd float %vecload, 1.0
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store float %add, float addrspace(3)* %arrayidx, align 8
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%inc = add i32 %indvar, 1
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br i1 undef, label %for.body, label %for.exit
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}
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; GCN-LABEL: {{^}}loop_arg_0:
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; GCN: v_and_b32_e32 v{{[0-9]+}}, 1, v{{[0-9]+}}
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; GCN: v_cmp_eq_i32_e32 vcc, 1,
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; GCN: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, exec, vcc
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; GCN: [[LOOPBB:BB[0-9]+_[0-9]+]]
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; GCN: s_cbranch_vccnz [[LOOPBB]]
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; GCN-NEXT: ; BB#2
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; GCN-NEXT: s_endpgm
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define void @loop_arg_0(float addrspace(3)* %ptr, i32 %n, i1 %cond) nounwind {
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entry:
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br label %for.body
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for.exit:
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ret void
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for.body:
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%indvar = phi i32 [ %inc, %for.body ], [ 0, %entry ]
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%tmp = add i32 %indvar, 32
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%arrayidx = getelementptr float, float addrspace(3)* %ptr, i32 %tmp
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%vecload = load float, float addrspace(3)* %arrayidx, align 4
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%add = fadd float %vecload, 1.0
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store float %add, float addrspace(3)* %arrayidx, align 8
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%inc = add i32 %indvar, 1
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br i1 %cond, label %for.body, label %for.exit
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}
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126
test/CodeGen/AMDGPU/extract-vector-elt-build-vector-combine.ll
Normal file
126
test/CodeGen/AMDGPU/extract-vector-elt-build-vector-combine.ll
Normal file
@ -0,0 +1,126 @@
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; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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; GCN-LABEL: {{^}}store_build_vector_multiple_uses_v4i32:
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; GCN: buffer_load_dword
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; GCN: buffer_load_dword
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; GCN: buffer_load_dword
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; GCN: buffer_load_dword
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; GCN: buffer_store_dwordx4
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; GCN: buffer_store_dwordx4
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; GCN: buffer_store_dword
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; GCN: buffer_store_dword
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; GCN: buffer_store_dword
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; GCN: buffer_store_dword
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define void @store_build_vector_multiple_uses_v4i32(<4 x i32> addrspace(1)* noalias %out0,
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<4 x i32> addrspace(1)* noalias %out1,
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i32 addrspace(1)* noalias %out2,
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i32 addrspace(1)* %in) {
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%elt0 = load volatile i32, i32 addrspace(1)* %in
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%elt1 = load volatile i32, i32 addrspace(1)* %in
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%elt2 = load volatile i32, i32 addrspace(1)* %in
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%elt3 = load volatile i32, i32 addrspace(1)* %in
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%vec0 = insertelement <4 x i32> undef, i32 %elt0, i32 0
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%vec1 = insertelement <4 x i32> %vec0, i32 %elt1, i32 1
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%vec2 = insertelement <4 x i32> %vec1, i32 %elt2, i32 2
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%vec3 = insertelement <4 x i32> %vec2, i32 %elt3, i32 3
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store <4 x i32> %vec3, <4 x i32> addrspace(1)* %out0
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store <4 x i32> %vec3, <4 x i32> addrspace(1)* %out1
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%extract0 = extractelement <4 x i32> %vec3, i32 0
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%extract1 = extractelement <4 x i32> %vec3, i32 1
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%extract2 = extractelement <4 x i32> %vec3, i32 2
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%extract3 = extractelement <4 x i32> %vec3, i32 3
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store volatile i32 %extract0, i32 addrspace(1)* %out2
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store volatile i32 %extract1, i32 addrspace(1)* %out2
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store volatile i32 %extract2, i32 addrspace(1)* %out2
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store volatile i32 %extract3, i32 addrspace(1)* %out2
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ret void
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}
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; GCN-LABEL: {{^}}store_build_vector_multiple_extract_uses_v4i32:
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; GCN: buffer_load_dword
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; GCN: buffer_load_dword
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; GCN: buffer_load_dword
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; GCN: buffer_load_dword
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; GCN: buffer_store_dwordx4
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; GCN: buffer_store_dword
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; GCN: buffer_store_dword
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; GCN: buffer_store_dword
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; GCN: buffer_store_dword
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define void @store_build_vector_multiple_extract_uses_v4i32(<4 x i32> addrspace(1)* noalias %out0,
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<4 x i32> addrspace(1)* noalias %out1,
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i32 addrspace(1)* noalias %out2,
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i32 addrspace(1)* %in) {
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%elt0 = load volatile i32, i32 addrspace(1)* %in
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%elt1 = load volatile i32, i32 addrspace(1)* %in
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%elt2 = load volatile i32, i32 addrspace(1)* %in
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%elt3 = load volatile i32, i32 addrspace(1)* %in
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%vec0 = insertelement <4 x i32> undef, i32 %elt0, i32 0
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%vec1 = insertelement <4 x i32> %vec0, i32 %elt1, i32 1
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%vec2 = insertelement <4 x i32> %vec1, i32 %elt2, i32 2
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%vec3 = insertelement <4 x i32> %vec2, i32 %elt3, i32 3
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%extract0 = extractelement <4 x i32> %vec3, i32 0
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%extract1 = extractelement <4 x i32> %vec3, i32 1
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%extract2 = extractelement <4 x i32> %vec3, i32 2
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%extract3 = extractelement <4 x i32> %vec3, i32 3
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%op0 = add i32 %extract0, 3
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%op1 = sub i32 %extract1, 9
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%op2 = xor i32 %extract2, 1231412
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%op3 = and i32 %extract3, 258233412312
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store <4 x i32> %vec3, <4 x i32> addrspace(1)* %out0
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store volatile i32 %op0, i32 addrspace(1)* %out2
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store volatile i32 %op1, i32 addrspace(1)* %out2
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store volatile i32 %op2, i32 addrspace(1)* %out2
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store volatile i32 %op3, i32 addrspace(1)* %out2
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ret void
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}
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; GCN-LABEL: {{^}}store_build_vector_multiple_uses_v4i32_bitcast_to_v2i64:
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; GCN: buffer_load_dword
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; GCN: buffer_load_dword
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; GCN: buffer_load_dword
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; GCN: buffer_load_dword
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; GCN: buffer_store_dwordx4
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; GCN: buffer_store_dwordx2
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; GCN: buffer_store_dwordx2
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define void @store_build_vector_multiple_uses_v4i32_bitcast_to_v2i64(<2 x i64> addrspace(1)* noalias %out0,
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<4 x i32> addrspace(1)* noalias %out1,
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i64 addrspace(1)* noalias %out2,
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i32 addrspace(1)* %in) {
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%elt0 = load volatile i32, i32 addrspace(1)* %in
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%elt1 = load volatile i32, i32 addrspace(1)* %in
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%elt2 = load volatile i32, i32 addrspace(1)* %in
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%elt3 = load volatile i32, i32 addrspace(1)* %in
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%vec0 = insertelement <4 x i32> undef, i32 %elt0, i32 0
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%vec1 = insertelement <4 x i32> %vec0, i32 %elt1, i32 1
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%vec2 = insertelement <4 x i32> %vec1, i32 %elt2, i32 2
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%vec3 = insertelement <4 x i32> %vec2, i32 %elt3, i32 3
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%bc.vec3 = bitcast <4 x i32> %vec3 to <2 x i64>
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store <2 x i64> %bc.vec3, <2 x i64> addrspace(1)* %out0
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%extract0 = extractelement <2 x i64> %bc.vec3, i32 0
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%extract1 = extractelement <2 x i64> %bc.vec3, i32 1
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store volatile i64 %extract0, i64 addrspace(1)* %out2
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store volatile i64 %extract1, i64 addrspace(1)* %out2
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ret void
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}
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36
test/CodeGen/AMDGPU/mad24-get-global-id.ll
Normal file
36
test/CodeGen/AMDGPU/mad24-get-global-id.ll
Normal file
@ -0,0 +1,36 @@
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; RUN: llc -mtriple=amdgcn--amdhsa -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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; If the workgroup id range is restricted, we should be able to use
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; mad24 for the usual indexing pattern.
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declare i32 @llvm.amdgcn.workgroup.id.x() #0
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declare i32 @llvm.amdgcn.workitem.id.x() #0
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declare i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr() #0
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; GCN-LABEL: {{^}}get_global_id_0:
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; GCN: s_and_b32 [[WGSIZEX:s[0-9]+]], {{s[0-9]+}}, 0xffff
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; GCN: v_mov_b32_e32 [[VWGSIZEX:v[0-9]+]], [[WGSIZEX]]
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; GCN: v_mad_u32_u24 v{{[0-9]+}}, [[VWGSIZEX]], s8, v0
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define void @get_global_id_0(i32 addrspace(1)* %out) #1 {
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%dispatch.ptr = call i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr()
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%cast.dispatch.ptr = bitcast i8 addrspace(2)* %dispatch.ptr to i32 addrspace(2)*
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%gep = getelementptr inbounds i32, i32 addrspace(2)* %cast.dispatch.ptr, i64 1
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%workgroup.size.xy = load i32, i32 addrspace(2)* %gep, align 4, !invariant.load !0
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%workgroup.size.x = and i32 %workgroup.size.xy, 65535
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%workitem.id.x = call i32 @llvm.amdgcn.workitem.id.x(), !range !1
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%workgroup.id.x = call i32 @llvm.amdgcn.workgroup.id.x(), !range !2
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%mul = mul i32 %workgroup.id.x, %workgroup.size.x
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%add = add i32 %mul, %workitem.id.x
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store i32 %add, i32 addrspace(1)* %out, align 4
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ret void
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}
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attributes #0 = { nounwind readnone }
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attributes #1 = { nounwind }
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!0 = !{}
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!1 = !{i32 0, i32 1024}
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!2 = !{i32 0, i32 16777216}
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@ -201,3 +201,15 @@ entry:
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store i32 %mask, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}extract_hi_i64_bitcast_v2i32:
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; SI: buffer_load_dword v
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; SI: buffer_store_dword v
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define void @extract_hi_i64_bitcast_v2i32(i32 addrspace(1)* %out, <2 x i32> addrspace(1)* %in) nounwind {
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%ld = load <2 x i32>, <2 x i32> addrspace(1)* %in
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%bc = bitcast <2 x i32> %ld to i64
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%hi = lshr i64 %bc, 32
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%trunc = trunc i64 %hi to i32
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store i32 %trunc, i32 addrspace(1)* %out
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ret void
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}
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@ -1,25 +0,0 @@
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; REQUIRES: asserts
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; XFAIL: *
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; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs-asm-verbose=false < %s | FileCheck %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs-asm-verbose=false < %s | FileCheck %s
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define void @test(i32 addrspace(1)* %g, i8 addrspace(3)* %l, i32 %x) nounwind {
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; CHECK-LABEL: {{^}}test:
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entry:
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switch i32 %x, label %sw.default [
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i32 0, label %sw.bb
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i32 60, label %sw.bb
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]
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sw.bb:
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unreachable
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sw.default:
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unreachable
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sw.epilog:
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ret void
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}
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@ -64,6 +64,87 @@ exit:
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ret void
|
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}
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; FIXME: should emit s_endpgm
|
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; CHECK-LABEL: {{^}}switch_unreachable:
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; CHECK-NOT: s_endpgm
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; CHECK: .Lfunc_end2
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define void @switch_unreachable(i32 addrspace(1)* %g, i8 addrspace(3)* %l, i32 %x) nounwind {
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centry:
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switch i32 %x, label %sw.default [
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i32 0, label %sw.bb
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i32 60, label %sw.bb
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]
|
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|
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sw.bb:
|
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unreachable
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|
||||
sw.default:
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unreachable
|
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|
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sw.epilog:
|
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ret void
|
||||
}
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declare float @llvm.fabs.f32(float) nounwind readnone
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|
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; This broke the old AMDIL cfg structurizer
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; FUNC-LABEL: {{^}}loop_land_info_assert:
|
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; SI: s_cmp_gt_i32
|
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; SI-NEXT: s_cbranch_scc0 [[ENDPGM:BB[0-9]+_[0-9]+]]
|
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|
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; SI: s_cmp_gt_i32
|
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; SI-NEXT: s_cbranch_scc1 [[ENDPGM]]
|
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|
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; SI: [[INFLOOP:BB[0-9]+_[0-9]+]]
|
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; SI: s_branch [[INFLOOP]]
|
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|
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; SI: [[ENDPGM]]:
|
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; SI: s_endpgm
|
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define void @loop_land_info_assert(i32 %c0, i32 %c1, i32 %c2, i32 %c3, i32 %x, i32 %y, i1 %arg) nounwind {
|
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entry:
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%cmp = icmp sgt i32 %c0, 0
|
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br label %while.cond.outer
|
||||
|
||||
while.cond.outer:
|
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%tmp = load float, float addrspace(1)* undef
|
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br label %while.cond
|
||||
|
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while.cond:
|
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%cmp1 = icmp slt i32 %c1, 4
|
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br i1 %cmp1, label %convex.exit, label %for.cond
|
||||
|
||||
convex.exit:
|
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%or = or i1 %cmp, %cmp1
|
||||
br i1 %or, label %return, label %if.end
|
||||
|
||||
if.end:
|
||||
%tmp3 = call float @llvm.fabs.f32(float %tmp) nounwind readnone
|
||||
%cmp2 = fcmp olt float %tmp3, 0x3E80000000000000
|
||||
br i1 %cmp2, label %if.else, label %while.cond.outer
|
||||
|
||||
if.else:
|
||||
store volatile i32 3, i32 addrspace(1)* undef, align 4
|
||||
br label %while.cond
|
||||
|
||||
for.cond:
|
||||
%cmp3 = icmp slt i32 %c3, 1000
|
||||
br i1 %cmp3, label %for.body, label %return
|
||||
|
||||
for.body:
|
||||
br i1 %cmp3, label %self.loop, label %if.end.2
|
||||
|
||||
if.end.2:
|
||||
%or.cond2 = or i1 %cmp3, %arg
|
||||
br i1 %or.cond2, label %return, label %for.cond
|
||||
|
||||
self.loop:
|
||||
br label %self.loop
|
||||
|
||||
return:
|
||||
ret void
|
||||
}
|
||||
|
||||
|
||||
declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #0
|
||||
|
||||
attributes #0 = { nounwind readnone }
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
; RUN: llc -march=amdgcn -mcpu=kaveri < %s | FileCheck %s
|
||||
; RUN: llc -march=amdgcn -mcpu=kaveri -verify-machineinstrs < %s | FileCheck %s
|
||||
|
||||
; CHECK-LABEL: {{^}}test:
|
||||
; CHECK s_and_saveexec_b64
|
||||
@ -6,7 +6,7 @@
|
||||
; CHECK s_or_b64 exec, exec
|
||||
; CHECK s_andn2_b64 exec, exec
|
||||
; CHECK s_cbranch_execnz
|
||||
define spir_kernel void @test(i32 %arg, i32 %arg1, i32 addrspace(1)* nocapture %arg2, i32 %arg3, i32 %arg4, i32 %arg5, i32 %arg6) {
|
||||
define void @test(i32 %arg, i32 %arg1) {
|
||||
bb:
|
||||
%tmp = icmp ne i32 %arg, 0
|
||||
%tmp7 = icmp ne i32 %arg1, 0
|
||||
|
||||
@ -1,8 +1,6 @@
|
||||
; REQUIRES: asserts
|
||||
; XFAIL: *
|
||||
; RUN: llc -O0 -verify-machineinstrs -asm-verbose=0 -march=amdgcn -mcpu=SI < %s | FileCheck -check-prefix=SI -check-prefix=COMMON %s
|
||||
; RUN: llc -O0 -verify-machineinstrs -asm-verbose=0 -march=amdgcn < %s | FileCheck -check-prefix=SI -check-prefix=COMMON %s
|
||||
; RUN: llc -O0 -verify-machineinstrs -asm-verbose=0 -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=SI -check-prefix=COMMON %s
|
||||
; RUN: llc -O0 -verify-machineinstrs -asm-verbose=0 -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=COMMON %s
|
||||
; XUN: llc -O0 -verify-machineinstrs -asm-verbose=0 -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=COMMON %s
|
||||
|
||||
; SI hits an assertion at -O0, evergreen hits a not implemented unreachable.
|
||||
|
||||
@ -41,8 +39,9 @@ for.end: ; preds = %for.body, %entry
|
||||
}
|
||||
|
||||
; COMMON-LABEL: {{^}}branch_false:
|
||||
; SI: .text
|
||||
; SI-NEXT: s_endpgm
|
||||
; SI: s_cbranch_vccnz
|
||||
; SI: s_cbranch_vccnz
|
||||
; SI: s_endpgm
|
||||
define void @branch_false(i8 addrspace(1)* nocapture %main, i32 %main_stride) #0 {
|
||||
entry:
|
||||
br i1 false, label %for.end, label %for.body.lr.ph
|
||||
@ -77,8 +76,9 @@ for.end: ; preds = %for.body, %entry
|
||||
}
|
||||
|
||||
; COMMON-LABEL: {{^}}branch_undef:
|
||||
; SI: .text
|
||||
; SI-NEXT: s_endpgm
|
||||
; SI: s_cbranch_vccnz
|
||||
; SI: s_cbranch_vccnz
|
||||
; SI: s_endpgm
|
||||
define void @branch_undef(i8 addrspace(1)* nocapture %main, i32 %main_stride) #0 {
|
||||
entry:
|
||||
br i1 undef, label %for.end, label %for.body.lr.ph
|
||||
|
||||
Loading…
Reference in New Issue
Block a user