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https://github.com/RPCS3/llvm-mirror.git
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[PowerPC] Strength reduction of multiply by a constant by shift and add/sub in place
A shift and add/sub sequence combination is faster in place of a multiply by constant. Because the cycle or latency of multiply is not huge, we only consider such following worthy patterns. ``` (mul x, 2^N + 1) => (add (shl x, N), x) (mul x, -(2^N + 1)) => -(add (shl x, N), x) (mul x, 2^N - 1) => (sub (shl x, N), x) (mul x, -(2^N - 1)) => (sub x, (shl x, N)) ``` And the cycles or latency is subtarget-dependent so that we need consider the subtarget to determine to do or not do such transformation. Also data type is considered for different cycles or latency to do multiply. Differential Revision: https://reviews.llvm.org/D58950 llvm-svn: 357233
This commit is contained in:
Zi Xuan Wu
parent
ab1afdd4e4
commit
fe88774ae8
@ -1071,6 +1071,7 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
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setTargetDAGCombine(ISD::SHL);
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setTargetDAGCombine(ISD::SRA);
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setTargetDAGCombine(ISD::SRL);
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setTargetDAGCombine(ISD::MUL);
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setTargetDAGCombine(ISD::SINT_TO_FP);
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setTargetDAGCombine(ISD::BUILD_VECTOR);
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if (Subtarget.hasFPCVT())
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@ -12643,6 +12644,8 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
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return combineSRA(N, DCI);
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case ISD::SRL:
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return combineSRL(N, DCI);
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case ISD::MUL:
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return combineMUL(N, DCI);
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case PPCISD::SHL:
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if (isNullConstant(N->getOperand(0))) // 0 << V -> 0.
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return N->getOperand(0);
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@ -14565,6 +14568,89 @@ SDValue PPCTargetLowering::combineTRUNCATE(SDNode *N,
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return SDValue();
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}
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SDValue PPCTargetLowering::combineMUL(SDNode *N, DAGCombinerInfo &DCI) const {
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SelectionDAG &DAG = DCI.DAG;
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ConstantSDNode *ConstOpOrElement = isConstOrConstSplat(N->getOperand(1));
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if (!ConstOpOrElement)
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return SDValue();
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// An imul is usually smaller than the alternative sequence for legal type.
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if (DAG.getMachineFunction().getFunction().optForMinSize() &&
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isOperationLegal(ISD::MUL, N->getValueType(0)))
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return SDValue();
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auto IsProfitable = [this](bool IsNeg, bool IsAddOne, EVT VT) -> bool {
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switch (this->Subtarget.getDarwinDirective()) {
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default:
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// TODO: enhance the condition for subtarget before pwr8
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return false;
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case PPC::DIR_PWR8:
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// type mul add shl
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// scalar 4 1 1
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// vector 7 2 2
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return true;
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case PPC::DIR_PWR9:
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// type mul add shl
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// scalar 5 2 2
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// vector 7 2 2
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// The cycle RATIO of related operations are showed as a table above.
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// Because mul is 5(scalar)/7(vector), add/sub/shl are all 2 for both
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// scalar and vector type. For 2 instrs patterns, add/sub + shl
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// are 4, it is always profitable; but for 3 instrs patterns
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// (mul x, -(2^N + 1)) => -(add (shl x, N), x), sub + add + shl are 6.
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// So we should only do it for vector type.
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return IsAddOne && IsNeg ? VT.isVector() : true;
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}
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};
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EVT VT = N->getValueType(0);
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SDLoc DL(N);
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const APInt &MulAmt = ConstOpOrElement->getAPIntValue();
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bool IsNeg = MulAmt.isNegative();
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APInt MulAmtAbs = MulAmt.abs();
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if ((MulAmtAbs - 1).isPowerOf2()) {
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// (mul x, 2^N + 1) => (add (shl x, N), x)
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// (mul x, -(2^N + 1)) => -(add (shl x, N), x)
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if (!IsProfitable(IsNeg, true, VT))
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return SDValue();
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SDValue Op0 = N->getOperand(0);
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SDValue Op1 =
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DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
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DAG.getConstant((MulAmtAbs - 1).logBase2(), DL, VT));
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SDValue Res = DAG.getNode(ISD::ADD, DL, VT, Op0, Op1);
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if (!IsNeg)
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return Res;
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return DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), Res);
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} else if ((MulAmtAbs + 1).isPowerOf2()) {
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// (mul x, 2^N - 1) => (sub (shl x, N), x)
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// (mul x, -(2^N - 1)) => (sub x, (shl x, N))
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if (!IsProfitable(IsNeg, false, VT))
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return SDValue();
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SDValue Op0 = N->getOperand(0);
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SDValue Op1 =
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DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
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DAG.getConstant((MulAmtAbs + 1).logBase2(), DL, VT));
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if (!IsNeg)
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return DAG.getNode(ISD::SUB, DL, VT, Op1, Op0);
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else
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return DAG.getNode(ISD::SUB, DL, VT, Op0, Op1);
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} else {
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return SDValue();
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}
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}
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bool PPCTargetLowering::mayBeEmittedAsTailCall(const CallInst *CI) const {
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// Only duplicate to increase tail-calls for the 64bit SysV ABIs.
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if (!Subtarget.isSVR4ABI() || !Subtarget.isPPC64())
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@ -1121,6 +1121,7 @@ namespace llvm {
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SDValue combineSHL(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue combineSRA(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue combineSRL(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue combineMUL(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue combineADD(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue combineTRUNCATE(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue combineSetCC(SDNode *N, DAGCombinerInfo &DCI) const;
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92
test/CodeGen/PowerPC/mul-const-i64.ll
Normal file
92
test/CodeGen/PowerPC/mul-const-i64.ll
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@ -0,0 +1,92 @@
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; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -mcpu=generic < %s -mtriple=ppc64-- | FileCheck %s -check-prefix=GENERIC-CHECK
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; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -mcpu=pwr8 < %s -mtriple=ppc64-- | FileCheck %s -check-prefixes=PWR8-CHECK,CHECK
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; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -mcpu=pwr9 < %s -mtriple=ppc64le-- | FileCheck %s -check-prefixes=PWR9-CHECK,CHECK
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define i64 @foo(i64 %a) {
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entry:
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%mul = mul nsw i64 %a, 6
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ret i64 %mul
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}
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; GENERIC-CHECK-LABEL: @foo
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; GENERIC-CHECK: mulli r3, r3, 6
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; GENERIC-CHECK: blr
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define i64 @test1(i64 %a) {
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%tmp.1 = mul nsw i64 %a, 16 ; <i64> [#uses=1]
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ret i64 %tmp.1
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}
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; CHECK-LABEL: test1:
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; CHECK-NOT: mul
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; CHECK: sldi r[[REG1:[0-9]+]], r3, 4
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define i64 @test2(i64 %a) {
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%tmp.1 = mul nsw i64 %a, 17 ; <i64> [#uses=1]
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ret i64 %tmp.1
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}
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; CHECK-LABEL: test2:
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; CHECK-NOT: mul
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; CHECK: sldi r[[REG1:[0-9]+]], r3, 4
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; CHECK-NEXT: add r[[REG2:[0-9]+]], r3, r[[REG1]]
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define i64 @test3(i64 %a) {
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%tmp.1 = mul nsw i64 %a, 15 ; <i64> [#uses=1]
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ret i64 %tmp.1
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}
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; CHECK-LABEL: test3:
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; CHECK-NOT: mul
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; CHECK: sldi r[[REG1:[0-9]+]], r3, 4
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; CHECK-NEXT: sub r[[REG2:[0-9]+]], r[[REG1]], r3
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; negtive constant
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define i64 @test4(i64 %a) {
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%tmp.1 = mul nsw i64 %a, -16 ; <i64> [#uses=1]
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ret i64 %tmp.1
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}
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; CHECK-LABEL: test4:
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; CHECK-NOT: mul
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; CHECK: sldi r[[REG1:[0-9]+]], r3, 4
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; CHECK-NEXT: neg r[[REG2:[0-9]+]], r[[REG1]]
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define i64 @test5(i64 %a) {
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%tmp.1 = mul nsw i64 %a, -17 ; <i64> [#uses=1]
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ret i64 %tmp.1
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}
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; CHECK-LABEL: test5:
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; PWR9-CHECK: mulli r[[REG1:[0-9]+]], r3, -17
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; PWR8-CHECK-NOT: mul
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; PWR8-CHECK: sldi r[[REG1:[0-9]+]], r3, 4
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; PWR8-CHECK-NEXT: add r[[REG2:[0-9]+]], r3, r[[REG1]]
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; PWR8-CHECK-NEXT: neg r{{[0-9]+}}, r[[REG2]]
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define i64 @test6(i64 %a) {
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%tmp.1 = mul nsw i64 %a, -15 ; <i64> [#uses=1]
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ret i64 %tmp.1
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}
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; CHECK-LABEL: test6:
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; CHECK-NOT: mul
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; CHECK: sldi r[[REG1:[0-9]+]], r3, 4
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; CHECK-NEXT: sub r[[REG2:[0-9]+]], r3, r[[REG1]]
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; CHECK-NOT: neg
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; boundary case
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define i64 @test7(i64 %a) {
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%tmp.1 = mul nsw i64 %a, -9223372036854775808 ; <i64> [#uses=1]
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ret i64 %tmp.1
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}
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; CHECK-LABEL: test7:
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; CHECK-NOT: mul
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; CHECK: sldi r[[REG1:[0-9]+]], r3, 63
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define i64 @test8(i64 %a) {
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%tmp.1 = mul nsw i64 %a, 9223372036854775807 ; <i64> [#uses=1]
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ret i64 %tmp.1
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}
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; CHECK-LABEL: test8:
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; CHECK-NOT: mul
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; CHECK: sldi r[[REG1:[0-9]+]], r3, 63
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; CHECK-NEXT: sub r[[REG2:[0-9]+]], r[[REG1]], r3
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382
test/CodeGen/PowerPC/mul-const-vector.ll
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382
test/CodeGen/PowerPC/mul-const-vector.ll
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@ -0,0 +1,382 @@
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; RUN: llc -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s -mtriple=ppc64le-- -mcpu=pwr8 | FileCheck %s --check-prefixes=CHECK,CHECK-P8
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; RUN: llc -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s -mtriple=ppc64le-- -mcpu=pwr9 | FileCheck %s --check-prefixes=CHECK,CHECK-P9
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define <16 x i8> @test1_v16i8(<16 x i8> %a) {
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%tmp.1 = mul nsw <16 x i8> %a, <i8 16, i8 16, i8 16, i8 16, i8 16, i8 16, i8 16, i8 16, i8 16, i8 16, i8 16, i8 16, i8 16, i8 16, i8 16, i8 16> ; <<16 x i8>> [#uses=1]
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ret <16 x i8> %tmp.1
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}
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; CHECK-LABEL: test1_v16i8:
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; CHECK-P8: vspltisb v[[REG1:[0-9]+]], 4
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; CHECK-P9: xxspltib v[[REG1:[0-9]+]], 4
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; CHECK-NOT: vmul
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; CHECK-NEXT: vslb v[[REG2:[0-9]+]], v2, v[[REG1]]
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define <16 x i8> @test2_v16i8(<16 x i8> %a) {
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%tmp.1 = mul nsw <16 x i8> %a, <i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17> ; <<16 x i8>> [#uses=1]
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ret <16 x i8> %tmp.1
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}
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; CHECK-LABEL: test2_v16i8:
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; CHECK-P8: vspltisb v[[REG1:[0-9]+]], 4
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; CHECK-P9: xxspltib v[[REG1:[0-9]+]], 4
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; CHECK-NOT: vmul
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; CHECK-NEXT: vslb v[[REG2:[0-9]+]], v2, v[[REG1]]
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; CHECK-NEXT: vaddubm v[[REG3:[0-9]+]], v2, v[[REG2]]
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define <16 x i8> @test3_v16i8(<16 x i8> %a) {
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%tmp.1 = mul nsw <16 x i8> %a, <i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15> ; <<16 x i8>> [#uses=1]
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ret <16 x i8> %tmp.1
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}
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; CHECK-LABEL: test3_v16i8:
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; CHECK-P8: vspltisb v[[REG1:[0-9]+]], 4
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; CHECK-P9: xxspltib v[[REG1:[0-9]+]], 4
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; CHECK-NOT: vmul
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; CHECK-NEXT: vslb v[[REG2:[0-9]+]], v2, v[[REG1]]
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; CHECK-NEXT: vsububm v[[REG3:[0-9]+]], v[[REG2]], v2
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; negtive constant
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define <16 x i8> @test4_v16i8(<16 x i8> %a) {
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%tmp.1 = mul nsw <16 x i8> %a, <i8 -16, i8 -16, i8 -16, i8 -16, i8 -16, i8 -16, i8 -16, i8 -16, i8 -16, i8 -16, i8 -16, i8 -16, i8 -16, i8 -16, i8 -16, i8 -16> ; <<16 x i8>> [#uses=1]
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ret <16 x i8> %tmp.1
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}
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; CHECK-LABEL: test4_v16i8:
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; CHECK-P8: vspltisb v[[REG1:[0-9]+]], 4
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; CHECK-P9: xxspltib v[[REG1:[0-9]+]], 4
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; CHECK-NOT: vmul
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; CHECK-NEXT: vslb v[[REG3:[0-9]+]], v2, v[[REG1]]
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; CHECK-NEXT: xxlxor v[[REG2:[0-9]+]],
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; CHECK-NEXT: vsububm v[[REG4:[0-9]+]], v[[REG2]], v[[REG3]]
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define <16 x i8> @test5_v16i8(<16 x i8> %a) {
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%tmp.1 = mul nsw <16 x i8> %a, <i8 -17, i8 -17, i8 -17, i8 -17, i8 -17, i8 -17, i8 -17, i8 -17, i8 -17, i8 -17, i8 -17, i8 -17, i8 -17, i8 -17, i8 -17, i8 -17> ; <<16 x i8>> [#uses=1]
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ret <16 x i8> %tmp.1
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}
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; CHECK-LABEL: test5_v16i8:
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; CHECK-P8: vspltisb v[[REG1:[0-9]+]], 4
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; CHECK-P9: xxspltib v[[REG1:[0-9]+]], 4
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; CHECK-NOT: vmul
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; CHECK-NEXT: vslb v[[REG3:[0-9]+]], v2, v[[REG1]]
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; CHECK-NEXT: vaddubm v[[REG4:[0-9]+]], v2, v[[REG3]]
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; CHECK-NEXT: xxlxor v[[REG2:[0-9]+]],
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; CHECK-NEXT: vsububm v[[REG5:[0-9]+]], v[[REG2]], v[[REG4]]
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define <16 x i8> @test6_v16i8(<16 x i8> %a) {
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%tmp.1 = mul nsw <16 x i8> %a, <i8 -15, i8 -15, i8 -15, i8 -15, i8 -15, i8 -15, i8 -15, i8 -15, i8 -15, i8 -15, i8 -15, i8 -15, i8 -15, i8 -15, i8 -15, i8 -15> ; <<16 x i8>> [#uses=1]
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ret <16 x i8> %tmp.1
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}
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; CHECK-LABEL: test6_v16i8:
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; CHECK-P8: vspltisb v[[REG1:[0-9]+]], 4
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; CHECK-P9: xxspltib v[[REG1:[0-9]+]], 4
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; CHECK-NOT: vmul
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; CHECK-NEXT: vslb v[[REG2:[0-9]+]], v2, v[[REG1]]
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; CHECK-NEXT: vsububm v[[REG3:[0-9]+]], v2, v[[REG2]]
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; boundary case
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define <16 x i8> @test7_v16i8(<16 x i8> %a) {
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%tmp.1 = mul nsw <16 x i8> %a, <i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128> ; <<16 x i8>> [#uses=1]
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ret <16 x i8> %tmp.1
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}
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; CHECK-LABEL: test7_v16i8:
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; CHECK-P8: vspltisb v[[REG1:[0-9]+]], 7
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; CHECK-P9: xxspltib v[[REG1:[0-9]+]], 7
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; CHECK-NOT: vmul
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; CHECK-NEXT: vslb v[[REG5:[0-9]+]], v2, v[[REG1]]
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define <16 x i8> @test8_v16i8(<16 x i8> %a) {
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%tmp.1 = mul nsw <16 x i8> %a, <i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127> ; <<16 x i8>> [#uses=1]
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ret <16 x i8> %tmp.1
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}
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; CHECK-LABEL: test8_v16i8:
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; CHECK-P8: vspltisb v[[REG1:[0-9]+]], 7
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; CHECK-P9: xxspltib v[[REG1:[0-9]+]], 7
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; CHECK-NOT: vmul
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; CHECK-NEXT: vslb v[[REG2:[0-9]+]], v2, v[[REG1]]
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; CHECK-NEXT: vsububm v[[REG3:[0-9]+]], v[[REG2]], v2
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define <8 x i16> @test1_v8i16(<8 x i16> %a) {
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%tmp.1 = mul nsw <8 x i16> %a, <i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16> ; <<8 x i16>> [#uses=1]
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ret <8 x i16> %tmp.1
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}
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; CHECK-LABEL: test1_v8i16:
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; CHECK: vspltish v[[REG1:[0-9]+]], 4
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; CHECK-NOT: vmul
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; CHECK-NEXT: vslh v[[REG2:[0-9]+]], v2, v[[REG1]]
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define <8 x i16> @test2_v8i16(<8 x i16> %a) {
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%tmp.1 = mul nsw <8 x i16> %a, <i16 17, i16 17, i16 17, i16 17, i16 17, i16 17, i16 17, i16 17> ; <<8 x i16>> [#uses=1]
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ret <8 x i16> %tmp.1
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}
|
||||
; CHECK-LABEL: test2_v8i16:
|
||||
; CHECK: vspltish v[[REG1:[0-9]+]], 4
|
||||
; CHECK-NOT: vmul
|
||||
; CHECK-NEXT: vslh v[[REG2:[0-9]+]], v2, v[[REG1]]
|
||||
; CHECK-NEXT: vadduhm v[[REG3:[0-9]+]], v2, v[[REG2]]
|
||||
|
||||
define <8 x i16> @test3_v8i16(<8 x i16> %a) {
|
||||
%tmp.1 = mul nsw <8 x i16> %a, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15> ; <<8 x i16>> [#uses=1]
|
||||
ret <8 x i16> %tmp.1
|
||||
}
|
||||
; CHECK-LABEL: test3_v8i16:
|
||||
; CHECK: vspltish v[[REG1:[0-9]+]], 4
|
||||
; CHECK-NOT: vmul
|
||||
; CHECK-NEXT: vslh v[[REG2:[0-9]+]], v2, v[[REG1]]
|
||||
; CHECK-NEXT: vsubuhm v[[REG3:[0-9]+]], v[[REG2]], v2
|
||||
|
||||
; negtive constant
|
||||
|
||||
define <8 x i16> @test4_v8i16(<8 x i16> %a) {
|
||||
%tmp.1 = mul nsw <8 x i16> %a, <i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16> ; <<8 x i16>> [#uses=1]
|
||||
ret <8 x i16> %tmp.1
|
||||
}
|
||||
; CHECK-LABEL: test4_v8i16:
|
||||
; CHECK: vspltish v[[REG1:[0-9]+]], 4
|
||||
; CHECK-NOT: vmul
|
||||
; CHECK-NEXT: vslh v[[REG3:[0-9]+]], v2, v[[REG1]]
|
||||
; CHECK-NEXT: xxlxor v[[REG2:[0-9]+]],
|
||||
; CHECK-NEXT: vsubuhm v[[REG4:[0-9]+]], v[[REG2]], v[[REG3]]
|
||||
|
||||
define <8 x i16> @test5_v8i16(<8 x i16> %a) {
|
||||
%tmp.1 = mul nsw <8 x i16> %a, <i16 -17, i16 -17, i16 -17, i16 -17, i16 -17, i16 -17, i16 -17, i16 -17> ; <<8 x i16>> [#uses=1]
|
||||
ret <8 x i16> %tmp.1
|
||||
}
|
||||
; CHECK-LABEL: test5_v8i16:
|
||||
; CHECK: vspltish v[[REG1:[0-9]+]], 4
|
||||
; CHECK-NOT: vmul
|
||||
; CHECK-NEXT: vslh v[[REG3:[0-9]+]], v2, v[[REG1]]
|
||||
; CHECK-NEXT: vadduhm v[[REG4:[0-9]+]], v2, v[[REG3]]
|
||||
; CHECK-NEXT: xxlxor v[[REG2:[0-9]+]],
|
||||
; CHECK-NEXT: vsubuhm v[[REG5:[0-9]+]], v[[REG2]], v[[REG4]]
|
||||
|
||||
define <8 x i16> @test6_v8i16(<8 x i16> %a) {
|
||||
%tmp.1 = mul nsw <8 x i16> %a, <i16 -15, i16 -15, i16 -15, i16 -15, i16 -15, i16 -15, i16 -15, i16 -15> ; <<8 x i16>> [#uses=1]
|
||||
ret <8 x i16> %tmp.1
|
||||
}
|
||||
; CHECK-LABEL: test6_v8i16:
|
||||
; CHECK: vspltish v[[REG1:[0-9]+]], 4
|
||||
; CHECK-NOT: vmul
|
||||
; CHECK-NEXT: vslh v[[REG2:[0-9]+]], v2, v[[REG1]]
|
||||
; CHECK-NEXT: vsubuhm v[[REG3:[0-9]+]], v2, v[[REG2]]
|
||||
|
||||
; boundary case
|
||||
|
||||
define <8 x i16> @test7_v8i16(<8 x i16> %a) {
|
||||
%tmp.1 = mul nsw <8 x i16> %a, <i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768> ; <<8 x i16>> [#uses=1]
|
||||
ret <8 x i16> %tmp.1
|
||||
}
|
||||
; CHECK-LABEL: test7_v8i16:
|
||||
; CHECK: vspltish v[[REG1:[0-9]+]], 15
|
||||
; CHECK-NOT: vmul
|
||||
; CHECK-NEXT: vslh v[[REG5:[0-9]+]], v2, v[[REG1]]
|
||||
|
||||
define <8 x i16> @test8_v8i16(<8 x i16> %a) {
|
||||
%tmp.1 = mul nsw <8 x i16> %a, <i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767> ; <<8 x i16>> [#uses=1]
|
||||
ret <8 x i16> %tmp.1
|
||||
}
|
||||
; CHECK-LABEL: test8_v8i16:
|
||||
; CHECK: vspltish v[[REG1:[0-9]+]], 15
|
||||
; CHECK-NOT: vmul
|
||||
; CHECK-NEXT: vslh v[[REG2:[0-9]+]], v2, v[[REG1]]
|
||||
; CHECK-NEXT: vsubuhm v[[REG3:[0-9]+]], v[[REG2]], v2
|
||||
|
||||
define <4 x i32> @test1_v4i32(<4 x i32> %a) {
|
||||
%tmp.1 = mul nsw <4 x i32> %a, <i32 16, i32 16, i32 16, i32 16> ; <<4 x i32>> [#uses=1]
|
||||
ret <4 x i32> %tmp.1
|
||||
}
|
||||
; CHECK-LABEL: test1_v4i32:
|
||||
; CHECK: vspltisw v[[REG1:[0-9]+]], 4
|
||||
; CHECK-NOT: vmul
|
||||
; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]]
|
||||
|
||||
define <4 x i32> @test2_v4i32(<4 x i32> %a) {
|
||||
%tmp.1 = mul nsw <4 x i32> %a, <i32 17, i32 17, i32 17, i32 17> ; <<4 x i32>> [#uses=1]
|
||||
ret <4 x i32> %tmp.1
|
||||
}
|
||||
; CHECK-LABEL: test2_v4i32:
|
||||
; CHECK: vspltisw v[[REG1:[0-9]+]], 4
|
||||
; CHECK-NOT: vmul
|
||||
; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]]
|
||||
; CHECK-NEXT: vadduwm v[[REG3:[0-9]+]], v2, v[[REG2]]
|
||||
|
||||
define <4 x i32> @test3_v4i32(<4 x i32> %a) {
|
||||
%tmp.1 = mul nsw <4 x i32> %a, <i32 15, i32 15, i32 15, i32 15> ; <<4 x i32>> [#uses=1]
|
||||
ret <4 x i32> %tmp.1
|
||||
}
|
||||
; CHECK-LABEL: test3_v4i32:
|
||||
; CHECK: vspltisw v[[REG1:[0-9]+]], 4
|
||||
; CHECK-NOT: vmul
|
||||
; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]]
|
||||
; CHECK-NEXT: vsubuwm v[[REG3:[0-9]+]], v[[REG2]], v2
|
||||
|
||||
; negtive constant
|
||||
|
||||
define <4 x i32> @test4_v4i32(<4 x i32> %a) {
|
||||
%tmp.1 = mul nsw <4 x i32> %a, <i32 -16, i32 -16, i32 -16, i32 -16> ; <<4 x i32>> [#uses=1]
|
||||
ret <4 x i32> %tmp.1
|
||||
}
|
||||
; CHECK-LABEL: test4_v4i32:
|
||||
; CHECK: vspltisw v[[REG1:[0-9]+]], 4
|
||||
; CHECK-NOT: vmul
|
||||
; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]]
|
||||
; CHECK-P8-NEXT: xxlxor v[[REG3:[0-9]+]],
|
||||
; CHECK-P8-NEXT: vsubuwm v{{[0-9]+}}, v[[REG3]], v[[REG2]]
|
||||
; CHECK-P9-NEXT: vnegw v{{[0-9]+}}, v[[REG2]]
|
||||
|
||||
define <4 x i32> @test5_v4i32(<4 x i32> %a) {
|
||||
%tmp.1 = mul nsw <4 x i32> %a, <i32 -17, i32 -17, i32 -17, i32 -17> ; <<4 x i32>> [#uses=1]
|
||||
ret <4 x i32> %tmp.1
|
||||
}
|
||||
; CHECK-LABEL: test5_v4i32:
|
||||
; CHECK: vspltisw v[[REG1:[0-9]+]], 4
|
||||
; CHECK-NOT: vmul
|
||||
; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]]
|
||||
; CHECK-NEXT: vadduwm v[[REG3:[0-9]+]], v2, v[[REG2]]
|
||||
; CHECK-P8-NEXT: xxlxor v[[REG4:[0-9]+]],
|
||||
; CHECK-P8-NEXT: vsubuwm v{{[0-9]+}}, v[[REG4]], v[[REG3]]
|
||||
; CHECK-P9-NEXT: vnegw v{{[0-9]+}}, v[[REG3]]
|
||||
|
||||
define <4 x i32> @test6_v4i32(<4 x i32> %a) {
|
||||
%tmp.1 = mul nsw <4 x i32> %a, <i32 -15, i32 -15, i32 -15, i32 -15> ; <<4 x i32>> [#uses=1]
|
||||
ret <4 x i32> %tmp.1
|
||||
}
|
||||
; CHECK-LABEL: test6_v4i32:
|
||||
; CHECK: vspltisw v[[REG1:[0-9]+]], 4
|
||||
; CHECK-NOT: vmul
|
||||
; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]]
|
||||
; CHECK-NEXT: vsubuwm v[[REG3:[0-9]+]], v2, v[[REG2]]
|
||||
|
||||
; boundary case
|
||||
|
||||
define <4 x i32> @test7_v4i32(<4 x i32> %a) {
|
||||
%tmp.1 = mul nsw <4 x i32> %a, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648> ; <<4 x i32>> [#uses=1]
|
||||
ret <4 x i32> %tmp.1
|
||||
}
|
||||
; CHECK-LABEL: test7_v4i32:
|
||||
; CHECK-DAG: vspltisw v[[REG2:[0-9]+]], -16
|
||||
; CHECK-DAG: vspltisw v[[REG3:[0-9]+]], 15
|
||||
; CHECK-NEXT: vsubuwm v[[REG4:[0-9]+]], v[[REG3]], v[[REG2]]
|
||||
; CHECK-NOT: vmul
|
||||
; CHECK-NEXT: vslw v[[REG5:[0-9]+]], v2, v[[REG4]]
|
||||
|
||||
define <4 x i32> @test8_v4i32(<4 x i32> %a) {
|
||||
%tmp.1 = mul nsw <4 x i32> %a, <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647> ; <<4 x i32>> [#uses=1]
|
||||
ret <4 x i32> %tmp.1
|
||||
}
|
||||
; CHECK-LABEL: test8_v4i32:
|
||||
; CHECK-DAG: vspltisw v[[REG2:[0-9]+]], -16
|
||||
; CHECK-DAG: vspltisw v[[REG3:[0-9]+]], 15
|
||||
; CHECK-NEXT: vsubuwm v[[REG4:[0-9]+]], v[[REG3]], v[[REG2]]
|
||||
; CHECK-NOT: vmul
|
||||
; CHECK-NEXT: vslw v[[REG5:[0-9]+]], v2, v[[REG4]]
|
||||
; CHECK-NEXT: vsubuwm v[[REG6:[0-9]+]], v[[REG5]], v2
|
||||
|
||||
define <2 x i64> @test1_v2i64(<2 x i64> %a) {
|
||||
%tmp.1 = mul nsw <2 x i64> %a, <i64 16, i64 16> ; <<2 x i64>> [#uses=1]
|
||||
ret <2 x i64> %tmp.1
|
||||
}
|
||||
; CHECK-LABEL: test1_v2i64:
|
||||
; CHECK-P8: lxvd2x vs[[REG1:[0-9]+]], 0, r{{[0-9]+}}
|
||||
; CHECK-P8-NEXT: xxswapd v[[REG2:[0-9]+]], vs[[REG1]]
|
||||
; CHECK-P9: lxvx v[[REG2:[0-9]+]], 0, r{{[0-9]+}}
|
||||
; CHECK-NOT: vmul
|
||||
; CHECK-NEXT: vsld v{{[0-9]+}}, v2, v[[REG2]]
|
||||
|
||||
define <2 x i64> @test2_v2i64(<2 x i64> %a) {
|
||||
%tmp.1 = mul nsw <2 x i64> %a, <i64 17, i64 17> ; <<2 x i64>> [#uses=1]
|
||||
ret <2 x i64> %tmp.1
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test2_v2i64:
|
||||
; CHECK-P8: lxvd2x vs[[REG1:[0-9]+]], 0, r{{[0-9]+}}
|
||||
; CHECK-P8-NEXT: xxswapd v[[REG2:[0-9]+]], vs[[REG1]]
|
||||
; CHECK-P9: lxvx v[[REG2:[0-9]+]], 0, r{{[0-9]+}}
|
||||
; CHECK-NOT: vmul
|
||||
; CHECK-NEXT: vsld v[[REG3:[0-9]+]], v2, v[[REG2]]
|
||||
; CHECK-NEXT: vaddudm v{{[0-9]+}}, v2, v[[REG3]]
|
||||
|
||||
define <2 x i64> @test3_v2i64(<2 x i64> %a) {
|
||||
%tmp.1 = mul nsw <2 x i64> %a, <i64 15, i64 15> ; <<2 x i64>> [#uses=1]
|
||||
ret <2 x i64> %tmp.1
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test3_v2i64:
|
||||
; CHECK-P8: lxvd2x vs[[REG1:[0-9]+]], 0, r{{[0-9]+}}
|
||||
; CHECK-P8-NEXT: xxswapd v[[REG2:[0-9]+]], vs[[REG1]]
|
||||
; CHECK-P9: lxvx v[[REG2:[0-9]+]], 0, r{{[0-9]+}}
|
||||
; CHECK-NOT: vmul
|
||||
; CHECK-NEXT: vsld v[[REG3:[0-9]+]], v2, v[[REG2]]
|
||||
; CHECK-NEXT: vsubudm v{{[0-9]+}}, v[[REG3]], v2
|
||||
|
||||
; negtive constant
|
||||
|
||||
define <2 x i64> @test4_v2i64(<2 x i64> %a) {
|
||||
%tmp.1 = mul nsw <2 x i64> %a, <i64 -16, i64 -16> ; <<2 x i64>> [#uses=1]
|
||||
ret <2 x i64> %tmp.1
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test4_v2i64:
|
||||
; CHECK-P8: lxvd2x vs[[REG1:[0-9]+]], 0, r{{[0-9]+}}
|
||||
; CHECK-P8-NEXT: xxswapd v[[REG2:[0-9]+]], vs[[REG1]]
|
||||
; CHECK-P9: lxvx v[[REG2:[0-9]+]], 0, r{{[0-9]+}}
|
||||
; CHECK-NOT: vmul
|
||||
; CHECK-NEXT: vsld v[[REG3:[0-9]+]], v2, v[[REG2]]
|
||||
; CHECK-P8-NEXT: xxlxor v[[REG4:[0-9]+]],
|
||||
; CHECK-P8-NEXT: vsubudm v{{[0-9]+}}, v[[REG4]], v[[REG3]]
|
||||
; CHECK-P9-NEXT: vnegd v[[REG4:[0-9]+]], v[[REG3]]
|
||||
|
||||
define <2 x i64> @test5_v2i64(<2 x i64> %a) {
|
||||
%tmp.1 = mul nsw <2 x i64> %a, <i64 -17, i64 -17> ; <<2 x i64>> [#uses=1]
|
||||
ret <2 x i64> %tmp.1
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test5_v2i64:
|
||||
; CHECK-P8: lxvd2x vs[[REG1:[0-9]+]], 0, r{{[0-9]+}}
|
||||
; CHECK-P8-NEXT: xxswapd v[[REG2:[0-9]+]], vs[[REG1]]
|
||||
; CHECK-P9: lxvx v[[REG2:[0-9]+]], 0, r{{[0-9]+}}
|
||||
; CHECK-NOT: vmul
|
||||
; CHECK-NEXT: vsld v[[REG3:[0-9]+]], v2, v[[REG2]]
|
||||
; CHECK-NEXT: vaddudm v[[REG4:[0-9]+]], v2, v[[REG3]]
|
||||
; CHECK-P8-NEXT: xxlxor v[[REG5:[0-9]+]],
|
||||
; CHECK-P8-NEXT: vsubudm v[[REG6:[0-9]+]], v[[REG5]], v[[REG4]]
|
||||
; CHECK-P9-NEXT: vnegd v{{[0-9]+}}, v[[REG4]]
|
||||
|
||||
define <2 x i64> @test6_v2i64(<2 x i64> %a) {
|
||||
%tmp.1 = mul nsw <2 x i64> %a, <i64 -15, i64 -15> ; <<2 x i64>> [#uses=1]
|
||||
ret <2 x i64> %tmp.1
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test6_v2i64:
|
||||
; CHECK-P8: lxvd2x vs[[REG1:[0-9]+]], 0, r{{[0-9]+}}
|
||||
; CHECK-P8-NEXT: xxswapd v[[REG2:[0-9]+]], vs[[REG1]]
|
||||
; CHECK-P9: lxvx v[[REG2:[0-9]+]], 0, r{{[0-9]+}}
|
||||
; CHECK-NOT: vmul
|
||||
; CHECK-NEXT: vsld v[[REG3:[0-9]+]], v2, v[[REG2]]
|
||||
; CHECK-NEXT: vsubudm v{{[0-9]+}}, v2, v[[REG3]]
|
||||
|
||||
|
||||
; boundary case
|
||||
|
||||
define <2 x i64> @test7_v2i64(<2 x i64> %a) {
|
||||
%tmp.1 = mul nsw <2 x i64> %a, <i64 -9223372036854775808, i64 -9223372036854775808> ; <<2 x i64>> [#uses=1]
|
||||
ret <2 x i64> %tmp.1
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test7_v2i64:
|
||||
; CHECK-P8: lxvd2x vs[[REG1:[0-9]+]], 0, r{{[0-9]+}}
|
||||
; CHECK-P8-NEXT: xxswapd v[[REG2:[0-9]+]], vs[[REG1]]
|
||||
; CHECK-P9: lxvx v[[REG2:[0-9]+]], 0, r{{[0-9]+}}
|
||||
; CHECK-NOT: vmul
|
||||
; CHECK-NEXT: vsld v[[REG4:[0-9]+]], v2, v[[REG2]]
|
||||
|
||||
define <2 x i64> @test8_v2i64(<2 x i64> %a) {
|
||||
%tmp.1 = mul nsw <2 x i64> %a, <i64 9223372036854775807, i64 9223372036854775807> ; <<2 x i64>> [#uses=1]
|
||||
ret <2 x i64> %tmp.1
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test8_v2i64:
|
||||
; CHECK-P8: lxvd2x vs[[REG1:[0-9]+]], 0, r{{[0-9]+}}
|
||||
; CHECK-P8-NEXT: xxswapd v[[REG2:[0-9]+]], vs[[REG1]]
|
||||
; CHECK-P9: lxvx v[[REG2:[0-9]+]], 0, r{{[0-9]+}}
|
||||
; CHECK-NOT: vmul
|
||||
; CHECK-NEXT: vsld v[[REG3:[0-9]+]], v2, v[[REG2]]
|
||||
; CHECK-NEXT: vsubudm v{{[0-9]+}}, v[[REG3]], v2
|
||||
79
test/CodeGen/PowerPC/mul-const.ll
Normal file
79
test/CodeGen/PowerPC/mul-const.ll
Normal file
@ -0,0 +1,79 @@
|
||||
; RUN: llc -verify-machineinstrs -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s -mtriple=ppc64-- | FileCheck %s -check-prefixes=PWR8-CHECK,CHECK
|
||||
; RUN: llc -verify-machineinstrs -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s -mtriple=ppc64le-- | FileCheck %s -check-prefixes=PWR9-CHECK,CHECK
|
||||
|
||||
define i32 @test1(i32 %a) {
|
||||
%tmp.1 = mul nsw i32 %a, 16 ; <i32> [#uses=1]
|
||||
ret i32 %tmp.1
|
||||
}
|
||||
; CHECK-LABEL: test1:
|
||||
; CHECK-NOT: mul
|
||||
; CHECK: slwi r[[REG1:[0-9]+]], r3, 4
|
||||
|
||||
define i32 @test2(i32 %a) {
|
||||
%tmp.1 = mul nsw i32 %a, 17 ; <i32> [#uses=1]
|
||||
ret i32 %tmp.1
|
||||
}
|
||||
; CHECK-LABEL: test2:
|
||||
; CHECK-NOT: mul
|
||||
; CHECK: slwi r[[REG1:[0-9]+]], r3, 4
|
||||
; CHECK-NEXT: add r[[REG2:[0-9]+]], r3, r[[REG1]]
|
||||
|
||||
define i32 @test3(i32 %a) {
|
||||
%tmp.1 = mul nsw i32 %a, 15 ; <i32> [#uses=1]
|
||||
ret i32 %tmp.1
|
||||
}
|
||||
; CHECK-LABEL: test3:
|
||||
; CHECK-NOT: mul
|
||||
; CHECK: slwi r[[REG1:[0-9]+]], r3, 4
|
||||
; CHECK-NEXT: subf r[[REG2:[0-9]+]], r3, r[[REG1]]
|
||||
|
||||
; negtive constant
|
||||
|
||||
define i32 @test4(i32 %a) {
|
||||
%tmp.1 = mul nsw i32 %a, -16 ; <i32> [#uses=1]
|
||||
ret i32 %tmp.1
|
||||
}
|
||||
; CHECK-LABEL: test4:
|
||||
; CHECK-NOT: mul
|
||||
; CHECK: slwi r[[REG1:[0-9]+]], r3, 4
|
||||
; CHECK-NEXT: neg r[[REG2:[0-9]+]], r[[REG1]]
|
||||
|
||||
define i32 @test5(i32 %a) {
|
||||
%tmp.1 = mul nsw i32 %a, -17 ; <i32> [#uses=1]
|
||||
ret i32 %tmp.1
|
||||
}
|
||||
; CHECK-LABEL: test5:
|
||||
; PWR9-CHECK: mulli r[[REG1:[0-9]+]], r3, -17
|
||||
; PWR8-CHECK-NOT: mul
|
||||
; PWR8-CHECK: slwi r[[REG1:[0-9]+]], r3, 4
|
||||
; PWR8-CHECK-NEXT: add r[[REG2:[0-9]+]], r3, r[[REG1]]
|
||||
; PWR8-CHECK-NEXT: neg r{{[0-9]+}}, r[[REG2]]
|
||||
|
||||
define i32 @test6(i32 %a) {
|
||||
%tmp.1 = mul nsw i32 %a, -15 ; <i32> [#uses=1]
|
||||
ret i32 %tmp.1
|
||||
}
|
||||
; CHECK-LABEL: test6:
|
||||
; CHECK-NOT: mul
|
||||
; CHECK: slwi r[[REG1:[0-9]+]], r3, 4
|
||||
; CHECK-NEXT: subf r[[REG2:[0-9]+]], r[[REG1]], r3
|
||||
; CHECK-NOT: neg
|
||||
|
||||
; boundary case
|
||||
|
||||
define i32 @test7(i32 %a) {
|
||||
%tmp.1 = mul nsw i32 %a, -2147483648 ; <i32> [#uses=1]
|
||||
ret i32 %tmp.1
|
||||
}
|
||||
; CHECK-LABEL: test7:
|
||||
; CHECK-NOT: mul
|
||||
; CHECK: slwi r[[REG1:[0-9]+]], r3, 31
|
||||
|
||||
define i32 @test8(i32 %a) {
|
||||
%tmp.1 = mul nsw i32 %a, 2147483647 ; <i32> [#uses=1]
|
||||
ret i32 %tmp.1
|
||||
}
|
||||
; CHECK-LABEL: test8:
|
||||
; CHECK-NOT: mul
|
||||
; CHECK: slwi r[[REG1:[0-9]+]], r3, 31
|
||||
; CHECK-NEXT: subf r[[REG2:[0-9]+]], r3, r[[REG1]]
|
||||
@ -1,8 +0,0 @@
|
||||
; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | not grep mul
|
||||
|
||||
define i32 @test1(i32 %a) {
|
||||
%tmp.1 = mul i32 %a, -2 ; <i32> [#uses=1]
|
||||
%tmp.2 = add i32 %tmp.1, 63 ; <i32> [#uses=1]
|
||||
ret i32 %tmp.2
|
||||
}
|
||||
|
||||
@ -1,16 +0,0 @@
|
||||
; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s
|
||||
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
|
||||
target triple = "powerpc64-unknown-linux-gnu"
|
||||
|
||||
define i64 @foo(i64 %a) #0 {
|
||||
entry:
|
||||
%mul = mul nsw i64 %a, 3
|
||||
ret i64 %mul
|
||||
}
|
||||
|
||||
; CHECK-LABEL: @foo
|
||||
; CHECK: mulli 3, 3, 3
|
||||
; CHECK: blr
|
||||
|
||||
attributes #0 = { nounwind readnone }
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user