From ff3fd55327aa144494b1791f827bbd92a652a66a Mon Sep 17 00:00:00 2001 From: Krzysztof Parzyszek Date: Wed, 25 Jul 2018 16:20:59 +0000 Subject: [PATCH] [Hexagon] Properly scale bit index when extracting elements from vNi1 For example v = <2 x i1> is represented as bbbbaaaa in a predicate register, where b = v[1], a = v[0]. Extracting v[1] is equivalent to extracting bit 4 from the predicate register. llvm-svn: 337934 --- lib/Target/Hexagon/HexagonISelLowering.cpp | 4 +++- test/CodeGen/Hexagon/vect/extract-elt-vNi1.ll | 18 ++++++++++++++++++ 2 files changed, 21 insertions(+), 1 deletion(-) create mode 100644 test/CodeGen/Hexagon/vect/extract-elt-vNi1.ll diff --git a/lib/Target/Hexagon/HexagonISelLowering.cpp b/lib/Target/Hexagon/HexagonISelLowering.cpp index 29cf70ab8e1..604d84994b6 100644 --- a/lib/Target/Hexagon/HexagonISelLowering.cpp +++ b/lib/Target/Hexagon/HexagonISelLowering.cpp @@ -2327,7 +2327,9 @@ HexagonTargetLowering::extractVector(SDValue VecV, SDValue IdxV, // If the value extracted is a single bit, use tstbit. if (ValWidth == 1) { SDValue A0 = getInstr(Hexagon::C2_tfrpr, dl, MVT::i32, {VecV}, DAG); - return DAG.getNode(HexagonISD::TSTBIT, dl, MVT::i1, A0, IdxV); + SDValue M0 = DAG.getConstant(8 / VecWidth, dl, MVT::i32); + SDValue I0 = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV, M0); + return DAG.getNode(HexagonISD::TSTBIT, dl, MVT::i1, A0, I0); } // Each bool vector (v2i1, v4i1, v8i1) always occupies 8 bits in diff --git a/test/CodeGen/Hexagon/vect/extract-elt-vNi1.ll b/test/CodeGen/Hexagon/vect/extract-elt-vNi1.ll new file mode 100644 index 00000000000..36c628b3594 --- /dev/null +++ b/test/CodeGen/Hexagon/vect/extract-elt-vNi1.ll @@ -0,0 +1,18 @@ +; RUN: llc -march=hexagon < %s | FileCheck %s + +; Make sure that element no.1 extracted from <2 x i1> translates to extracting +; bit no.4 from the predicate register. + +; CHECK: p[[P0:[0-3]]] = vcmpw.eq(r1:0,r3:2) +; CHECK: r[[R0:[0-9]+]] = p[[P0]] +; This is what we're really testing: the bit index of 4. +; CHECK: p[[P0]] = tstbit(r[[R0]],#4) + +define i32 @fred(<2 x i32> %a0, <2 x i32> %a1) #0 { + %v0 = icmp eq <2 x i32> %a0, %a1 + %v1 = extractelement <2 x i1> %v0, i32 1 + %v2 = zext i1 %v1 to i32 + ret i32 %v2 +} + +attributes #0 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" }