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[NFC][InstCombine] Add tests for "redundant shift input masking" (PR42456)
https://bugs.llvm.org/show_bug.cgi?id=42456 https://rise4fun.com/Alive/Vf1p llvm-svn: 364894
This commit is contained in:
Roman Lebedev
parent
207f6805ea
commit
ffd0b141f9
229
test/Transforms/InstCombine/redundant-shift-input-masking.ll
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229
test/Transforms/InstCombine/redundant-shift-input-masking.ll
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@ -0,0 +1,229 @@
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt %s -instcombine -S | FileCheck %s
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; If we have:
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; (data & (-1 << nbits)) outer>> nbits
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; Or
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; ((data inner>> nbits) << nbits) outer>> nbits
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; The mask is redundant, and can be dropped:
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; data outer>> nbits
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; This is valid for both lshr and ashr in both positions and any combination.
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define i32 @t0_lshr(i32 %data, i32 %nbits) {
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; CHECK-LABEL: @t0_lshr(
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; CHECK-NEXT: [[T0:%.*]] = shl i32 -1, [[NBITS:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = and i32 [[T0]], [[DATA:%.*]]
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; CHECK-NEXT: [[T2:%.*]] = lshr i32 [[T1]], [[NBITS]]
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; CHECK-NEXT: ret i32 [[T2]]
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;
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%t0 = shl i32 -1, %nbits
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%t1 = and i32 %t0, %data
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%t2 = lshr i32 %t1, %nbits
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ret i32 %t2
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}
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define i32 @t1_sshr(i32 %data, i32 %nbits) {
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; CHECK-LABEL: @t1_sshr(
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; CHECK-NEXT: [[T0:%.*]] = shl i32 -1, [[NBITS:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = and i32 [[T0]], [[DATA:%.*]]
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; CHECK-NEXT: [[T2:%.*]] = ashr i32 [[T1]], [[NBITS]]
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; CHECK-NEXT: ret i32 [[T2]]
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;
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%t0 = shl i32 -1, %nbits
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%t1 = and i32 %t0, %data
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%t2 = ashr i32 %t1, %nbits
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ret i32 %t2
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}
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; Vectors
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define <4 x i32> @t2_vec(<4 x i32> %data, <4 x i32> %nbits) {
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; CHECK-LABEL: @t2_vec(
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; CHECK-NEXT: [[T0:%.*]] = shl <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, [[NBITS:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = and <4 x i32> [[T0]], [[DATA:%.*]]
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; CHECK-NEXT: [[T2:%.*]] = lshr <4 x i32> [[T1]], [[NBITS]]
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; CHECK-NEXT: ret <4 x i32> [[T2]]
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;
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%t0 = shl <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, %nbits
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%t1 = and <4 x i32> %t0, %data
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%t2 = lshr <4 x i32> %t1, %nbits
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ret <4 x i32> %t2
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}
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define <4 x i32> @t3_vec_undef(<4 x i32> %data, <4 x i32> %nbits) {
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; CHECK-LABEL: @t3_vec_undef(
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; CHECK-NEXT: [[T0:%.*]] = shl <4 x i32> <i32 -1, i32 -1, i32 undef, i32 -1>, [[NBITS:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = and <4 x i32> [[T0]], [[DATA:%.*]]
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; CHECK-NEXT: [[T2:%.*]] = lshr <4 x i32> [[T1]], [[NBITS]]
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; CHECK-NEXT: ret <4 x i32> [[T2]]
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;
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%t0 = shl <4 x i32> <i32 -1, i32 -1, i32 undef, i32 -1>, %nbits
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%t1 = and <4 x i32> %t0, %data
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%t2 = lshr <4 x i32> %t1, %nbits
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ret <4 x i32> %t2
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}
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; Extra uses
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declare void @use32(i32)
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define i32 @t4_extrause0(i32 %data, i32 %nbits) {
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; CHECK-LABEL: @t4_extrause0(
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; CHECK-NEXT: [[T0:%.*]] = shl i32 -1, [[NBITS:%.*]]
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; CHECK-NEXT: call void @use32(i32 [[T0]])
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; CHECK-NEXT: [[T1:%.*]] = and i32 [[T0]], [[DATA:%.*]]
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; CHECK-NEXT: [[T2:%.*]] = lshr i32 [[T1]], [[NBITS]]
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; CHECK-NEXT: ret i32 [[T2]]
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;
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%t0 = shl i32 -1, %nbits
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call void @use32(i32 %t0)
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%t1 = and i32 %t0, %data
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%t2 = lshr i32 %t1, %nbits
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ret i32 %t2
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}
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define i32 @t5_extrause1(i32 %data, i32 %nbits) {
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; CHECK-LABEL: @t5_extrause1(
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; CHECK-NEXT: [[T0:%.*]] = shl i32 -1, [[NBITS:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = and i32 [[T0]], [[DATA:%.*]]
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; CHECK-NEXT: call void @use32(i32 [[T1]])
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; CHECK-NEXT: [[T2:%.*]] = lshr i32 [[T1]], [[NBITS]]
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; CHECK-NEXT: ret i32 [[T2]]
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;
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%t0 = shl i32 -1, %nbits
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%t1 = and i32 %t0, %data
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call void @use32(i32 %t1)
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%t2 = lshr i32 %t1, %nbits
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ret i32 %t2
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}
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define i32 @t6_extrause2(i32 %data, i32 %nbits) {
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; CHECK-LABEL: @t6_extrause2(
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; CHECK-NEXT: [[T0:%.*]] = shl i32 -1, [[NBITS:%.*]]
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; CHECK-NEXT: call void @use32(i32 [[T0]])
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; CHECK-NEXT: [[T1:%.*]] = and i32 [[T0]], [[DATA:%.*]]
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; CHECK-NEXT: call void @use32(i32 [[T1]])
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; CHECK-NEXT: [[T2:%.*]] = lshr i32 [[T1]], [[NBITS]]
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; CHECK-NEXT: ret i32 [[T2]]
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;
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%t0 = shl i32 -1, %nbits
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call void @use32(i32 %t0)
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%t1 = and i32 %t0, %data
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call void @use32(i32 %t1)
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%t2 = lshr i32 %t1, %nbits
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ret i32 %t2
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}
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; Non-canonical mask pattern. Let's just test a single case with all-extra uses.
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define i32 @t7_noncanonical_lshr_lshr_extrauses(i32 %data, i32 %nbits) {
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; CHECK-LABEL: @t7_noncanonical_lshr_lshr_extrauses(
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; CHECK-NEXT: [[T0:%.*]] = lshr i32 [[DATA:%.*]], [[NBITS:%.*]]
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; CHECK-NEXT: call void @use32(i32 [[T0]])
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; CHECK-NEXT: [[T1:%.*]] = shl i32 [[T0]], [[NBITS]]
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; CHECK-NEXT: call void @use32(i32 [[T1]])
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; CHECK-NEXT: [[T2:%.*]] = lshr i32 [[T1]], [[NBITS]]
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; CHECK-NEXT: ret i32 [[T2]]
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;
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%t0 = lshr i32 %data, %nbits
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call void @use32(i32 %t0)
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%t1 = shl i32 %t0, %nbits
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call void @use32(i32 %t1)
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%t2 = lshr i32 %t1, %nbits
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ret i32 %t2
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}
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define i32 @t8_noncanonical_lshr_ashr_extrauses(i32 %data, i32 %nbits) {
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; CHECK-LABEL: @t8_noncanonical_lshr_ashr_extrauses(
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; CHECK-NEXT: [[T0:%.*]] = lshr i32 [[DATA:%.*]], [[NBITS:%.*]]
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; CHECK-NEXT: call void @use32(i32 [[T0]])
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; CHECK-NEXT: [[T1:%.*]] = shl i32 [[T0]], [[NBITS]]
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; CHECK-NEXT: call void @use32(i32 [[T1]])
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; CHECK-NEXT: [[T2:%.*]] = ashr i32 [[T1]], [[NBITS]]
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; CHECK-NEXT: ret i32 [[T2]]
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;
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%t0 = lshr i32 %data, %nbits
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call void @use32(i32 %t0)
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%t1 = shl i32 %t0, %nbits
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call void @use32(i32 %t1)
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%t2 = ashr i32 %t1, %nbits
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ret i32 %t2
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}
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define i32 @t9_noncanonical_ashr_lshr_extrauses(i32 %data, i32 %nbits) {
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; CHECK-LABEL: @t9_noncanonical_ashr_lshr_extrauses(
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; CHECK-NEXT: [[T0:%.*]] = ashr i32 [[DATA:%.*]], [[NBITS:%.*]]
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; CHECK-NEXT: call void @use32(i32 [[T0]])
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; CHECK-NEXT: [[T1:%.*]] = shl i32 [[T0]], [[NBITS]]
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; CHECK-NEXT: call void @use32(i32 [[T1]])
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; CHECK-NEXT: [[T2:%.*]] = lshr i32 [[T1]], [[NBITS]]
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; CHECK-NEXT: ret i32 [[T2]]
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;
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%t0 = ashr i32 %data, %nbits
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call void @use32(i32 %t0)
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%t1 = shl i32 %t0, %nbits
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call void @use32(i32 %t1)
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%t2 = lshr i32 %t1, %nbits
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ret i32 %t2
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}
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define i32 @t10_noncanonical_ashr_ashr_extrauses(i32 %data, i32 %nbits) {
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; CHECK-LABEL: @t10_noncanonical_ashr_ashr_extrauses(
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; CHECK-NEXT: [[T0:%.*]] = ashr i32 [[DATA:%.*]], [[NBITS:%.*]]
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; CHECK-NEXT: call void @use32(i32 [[T0]])
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; CHECK-NEXT: [[T1:%.*]] = shl i32 [[T0]], [[NBITS]]
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; CHECK-NEXT: call void @use32(i32 [[T1]])
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; CHECK-NEXT: [[T2:%.*]] = ashr i32 [[T1]], [[NBITS]]
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; CHECK-NEXT: ret i32 [[T2]]
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;
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%t0 = ashr i32 %data, %nbits
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call void @use32(i32 %t0)
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%t1 = shl i32 %t0, %nbits
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call void @use32(i32 %t1)
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%t2 = ashr i32 %t1, %nbits
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ret i32 %t2
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}
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; Negative tests
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define i32 @n11(i32 %data, i32 %nbits) {
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; CHECK-LABEL: @n11(
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; CHECK-NEXT: [[T0:%.*]] = shl i32 2147483647, [[NBITS:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = and i32 [[T0]], [[DATA:%.*]]
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; CHECK-NEXT: [[T2:%.*]] = lshr i32 [[T1]], [[NBITS]]
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; CHECK-NEXT: ret i32 [[T2]]
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;
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%t0 = shl i32 2147483647, %nbits ; must be shifting -1
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%t1 = and i32 %t0, %data
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%t2 = lshr i32 %t1, %nbits
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ret i32 %t2
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}
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define i32 @n12(i32 %data, i32 %nbits0, i32 %nbits1) {
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; CHECK-LABEL: @n12(
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; CHECK-NEXT: [[T0:%.*]] = shl i32 -1, [[NBITS0:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = and i32 [[T0]], [[DATA:%.*]]
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; CHECK-NEXT: [[T2:%.*]] = lshr i32 [[T1]], [[NBITS1:%.*]]
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; CHECK-NEXT: ret i32 [[T2]]
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;
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%t0 = shl i32 -1, %nbits0
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%t1 = and i32 %t0, %data
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%t2 = lshr i32 %t1, %nbits1 ; different shift amounts
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ret i32 %t2
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}
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define i32 @n13(i32 %data, i32 %nbits0, i32 %nbits1, i32 %nbits2) {
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; CHECK-LABEL: @n13(
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; CHECK-NEXT: [[T0:%.*]] = lshr i32 [[DATA:%.*]], [[NBITS0:%.*]]
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; CHECK-NEXT: call void @use32(i32 [[T0]])
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; CHECK-NEXT: [[T1:%.*]] = shl i32 [[T0]], [[NBITS1:%.*]]
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; CHECK-NEXT: call void @use32(i32 [[T1]])
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; CHECK-NEXT: [[T2:%.*]] = lshr i32 [[T1]], [[NBITS2:%.*]]
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; CHECK-NEXT: ret i32 [[T2]]
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;
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%t0 = lshr i32 %data, %nbits0
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call void @use32(i32 %t0)
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%t1 = shl i32 %t0, %nbits1 ; different shift amounts
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call void @use32(i32 %t1)
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%t2 = lshr i32 %t1, %nbits2 ; different shift amounts
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ret i32 %t2
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}
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