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15 Commits

Author SHA1 Message Date
Dmitry Preobrazhensky
5b0739ebd4 [AMDGPU][MC] Added register size check for VOP3/SDWA/DPP operands 
See bug 37943: https://bugs.llvm.org/show_bug.cgi?id=37943

Reviewers: artem.tamazov, arsenm, rampitec

Differential Revision: https://reviews.llvm.org/D58287

llvm-svn: 354974
 2019-02-27 13:58:48 +00:00
Valery Pykhtin
3cb4209210 [AMDGPU] Combine DPP mov with use instructions (VOP1/2/3) 
Introduces DPP pseudo instructions and the pass that combines DPP mov with subsequent uses.

Differential revision: https://reviews.llvm.org/D53762

llvm-svn: 347993
 2018-11-30 14:21:56 +00:00
Dmitry Preobrazhensky
12adb5f9d4 [AMDGPU][MC][VI][GFX9] Added support of SDWA/DPP for v_cndmask_b32 
See bug 36356: https://bugs.llvm.org/show_bug.cgi?id=36356

Differential Revision: https://reviews.llvm.org/D45446

Reviewers: artem.tamazov, arsenm, timcorringham
llvm-svn: 330123
 2018-04-16 12:41:38 +00:00
Dmitry Preobrazhensky
28dc2311b5 [AMDGPU][MC][GFX9] Added v_screen_partition_4se_b32 
See bug 36845: https://bugs.llvm.org/show_bug.cgi?id=36845

Differential Revision: https://reviews.llvm.org/D45443

Reviewers: artem.tamazov, arsenm, timcorringham
llvm-svn: 329801
 2018-04-11 13:13:30 +00:00
Dmitry Preobrazhensky
7f103ba304 [AMDGPU][MC][GFX9] Added instructions v_cvt_norm_*16_f16, v_sat_pk_u8_i16 
See bug 36847: https://bugs.llvm.org/show_bug.cgi?id=36847

Differential Revision: https://reviews.llvm.org/D45097

Reviewers: artem.tamazov, arsenm, timcorringham
llvm-svn: 328988
 2018-04-02 17:09:20 +00:00
Dmitry Preobrazhensky
551dde9f3b [AMDGPU][MC][GFX8][GFX9] Corrected names of integer v_{add/addc/sub/subrev/subb/subbrev} 
See bug 34765: https://bugs.llvm.org//show_bug.cgi?id=34765

Reviewers: tamazov, SamWot, arsenm, vpykhtin

Differential Revision: https://reviews.llvm.org/D40088

llvm-svn: 318675
 2017-11-20 18:24:21 +00:00
Matt Arsenault
426c222888 AMDGPU: Remove -mcpu=SI 
Leftover from before amdgcn/r600 split.

llvm-svn: 310277
 2017-08-07 18:30:35 +00:00
Sam Kolton
587bdc31c1 [AMDGPU] DPP: add support for GFX9 
Reviewers: artem.tamazov

Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye

Differential Revision: https://reviews.llvm.org/D32588

llvm-svn: 301551
 2017-04-27 15:42:38 +00:00
Sam Kolton
68af374543 [AMDGPU] Assembler: SDWA/DPP should not accept scalar registers and immediate operands 
Reviewers: artem.tamazov, nhaustov, vpykhtin, tstellarAMD

Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, tony-tye

Differential Revision: https://reviews.llvm.org/D28157

llvm-svn: 291668
 2017-01-11 11:46:30 +00:00
Sam Kolton
db7d918144 [AMDGPU] Assembler: support SDWA and DPP for VOP2b instructions 
Reviewers: nhaustov, artem.tamazov, vpykhtin, tstellarAMD

Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, tony-tye

Differential Revision: https://reviews.llvm.org/D28051

llvm-svn: 290599
 2016-12-27 10:06:42 +00:00
Matt Arsenault
5f7fab5b1a AMDGPU: Fix name for v_ashrrev_i16 
llvm-svn: 289967
 2016-12-16 17:40:11 +00:00
Sam Kolton
cbf772ce03 [AMDGPU] Assembler: support v_mac_f32 DPP and SDWA. Move getNamedOperandIdx to AMDGPUBaseInfo.h 
Reviewers: artem.tamazov, tstellarAMD

Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, tony-tye

Differential Revision: https://reviews.llvm.org/D25084

llvm-svn: 283560
 2016-10-07 14:46:06 +00:00
Sam Kolton
518916f9b4 [AMDGPU] AsmParser: disable DPP for unsupported instructions. New dpp tests. Fix v_nop_dpp. 
Summary:
1. Disable DPP encoding for instructions that do not support it:
    - VOP1:
        - v_readfirstlane_b32
        - v_clrexcp
        - v_movreld_b32
        - v_movrels_b32
        - v_movrelsd_b32
    - VOP2:
        - v_madmk_f16/32
        - v_madak_f16/32
    - VOPC, VINTRP, VOP3
2. Fix DPP for v_nop
3. New DPP tests for VOP1 and VOP2 instructions

Reviewers: nhaustov, tstellarAMD, vpykhtin

Subscribers: tstellarAMD, arsenm

Differential Revision: http://reviews.llvm.org/D18552

llvm-svn: 265538
 2016-04-06 13:29:59 +00:00
Sam Kolton
f56b2d94d4 [AMDGPU] Assembler: Change dpp_ctrl syntax to match sp3 
Review: http://reviews.llvm.org/D18267
llvm-svn: 263789
 2016-03-18 15:35:51 +00:00
Sam Kolton
96f1d9ee4d [AMDGPU] Assembler: Support DPP instructions. 
Supprot DPP syntax as used in SP3 (except several operands syntax).
Added dpp-specific operands in td-files.
Added DPP flag to TSFlags to determine if instruction is dpp in InstPrinter.
Support for VOP2 DPP instructions in td-files.
Some tests for DPP instructions.

ToDo:
  - VOP2bInst:
    - vcc is considered as operand
    - AsmMatcher doesn't apply mnemonic aliases when parsing operands
  - v_mac_f32
  - v_nop
  - disable instructions with 64-bit operands
  - change dpp_ctrl assembler representation to conform sp3

Review: http://reviews.llvm.org/D17804
llvm-svn: 263008
 2016-03-09 12:29:31 +00:00