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02e4f56c18
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42 Commits

Author SHA1 Message Date
Cameron McInally
02e4f56c18 Add support for AVX512 masked vector blend intrinsics. 
llvm-svn: 194006
 2013-11-04 19:14:56 +00:00
Elena Demikhovsky
841cd7d09e AVX-512: added VPCONFLICT instruction and intrinsics, 
added EVEX_KZ to tablegen

llvm-svn: 193959
 2013-11-03 13:46:31 +00:00
Cameron McInally
c38779faad Add AVX512 unmasked integer broadcast intrinsics and support. 
llvm-svn: 193748
 2013-10-31 13:56:31 +00:00
Elena Demikhovsky
0e6849495e AVX-512: PMIN/PMAX intrinsics and patterns 
Patch by Cameron McInally <cameron.mcinally@nyu.edu>

llvm-svn: 193497
 2013-10-27 08:18:37 +00:00
Quentin Colombet
5d88e45af6 [X86][AVX512] Add patterns that match the AVX512 floating point register vbroadcast intrinsics. 
Patch by Cameron McInally <cameron.mcinally@nyu.edu>

llvm-svn: 193422
 2013-10-25 18:04:12 +00:00
Quentin Colombet
5650890143 [X86][AVX512] Add patterns that match the AVX512 floating point vbroadcast intrinsics. 
Patch by Cameron McInally <cameron.mcinally@nyu.edu>

llvm-svn: 193421
 2013-10-25 17:47:18 +00:00
Elena Demikhovsky
da06b9b278 AVX-512: added VCVTPH2PS, VCVTPS2PH with intrinsics 
llvm-svn: 193312
 2013-10-24 07:16:35 +00:00
Elena Demikhovsky
3136868b1d AVX-512: aligned / unaligned load and store for 512-bit integer vectors. 
llvm-svn: 193156
 2013-10-22 09:19:28 +00:00
Lang Hames
df2443e32e X86 vector element shift-by-immediate instructions take i8 immediates. Make 
the instruction defenitions and ISEL reflect this.

Prior to this patch these instructions took an i32i8imm, and the high bits were
dropped during encoding. This led to incorrect behavior for shifts by
immediates higher than 255. This patch fixes that issue by detecting large
immediate shifts and returning constant zero (for logical shifts) or capping
the shift amount at an encodable value (for arithmetic shifts).

Fixes <rdar://problem/14968098>

llvm-svn: 193096
 2013-10-21 17:51:24 +00:00
Craig Topper
47d75426b9 Remove more filters from the disassembler. Mark some AVX512 instructions as CodeGenOnly. 
llvm-svn: 192525
 2013-10-12 05:41:08 +00:00
Elena Demikhovsky
f24ecf7862 AVX-512: Added VRCP28 and VRSQRT28 instructions and intrinsics. 
llvm-svn: 192283
 2013-10-09 08:16:14 +00:00
Andrew Trick
6456fd444d Add missing HasAVX512 predicate. 
This was only working because AVX had cheaper rules in all cases.
I'm sure there are other places in this file where predicates are missing.

llvm-svn: 192276
 2013-10-09 05:11:10 +00:00
Craig Topper
ae27a7b281 Use AVX512PIi8 for the alt forms of vcmp instructions. This adds the TB prefix and keeps the mnemonic from starting with an extra 'v' 
llvm-svn: 192272
 2013-10-09 04:24:38 +00:00
Elena Demikhovsky
cb8eaca2e4 AVX-512: added scalar convert instructions and intrinsics. 
Fixed load folding in VPERM2I instruction.

llvm-svn: 192063
 2013-10-06 13:11:09 +00:00
Elena Demikhovsky
0ff833ab99 AVX-512: fixed shuffle lowering 
in case of BLEND and added VSHUFPS patterns.

llvm-svn: 192055
 2013-10-06 06:11:18 +00:00
Elena Demikhovsky
05028f4106 AVX-512: Fixed encoding of VMOVQ instruction. 
llvm-svn: 191889
 2013-10-03 12:03:26 +00:00
Elena Demikhovsky
ee11e148e9 AVX-512: fixed a bug in getLoadStoreRegOpcode() for AVX-512 target 
llvm-svn: 191818
 2013-10-02 12:20:42 +00:00
Elena Demikhovsky
d336ecd5ad AVX-512: Added TB prefix to all instructions without prefixes, 
otherwise encoding fails after the last change in X86MCCodeEmitter.cpp.

llvm-svn: 191812
 2013-10-02 06:39:07 +00:00
Elena Demikhovsky
84c6cd222d AVX-512: Added X86vzmovl patterns 
llvm-svn: 191733
 2013-10-01 08:38:02 +00:00
Craig Topper
60de5044cf Put HasAVX512 predicate on some patterns to properly disable them when AVX512 isn't enabled. Currently it works simply because the SSE and AVX version of the same patterns are checked first in the DAG isel table. 
llvm-svn: 191490
 2013-09-27 07:20:47 +00:00
Elena Demikhovsky
28417de9de AVX-512: Converted to Unix style 
llvm-svn: 190851
 2013-09-17 07:34:34 +00:00
Preston Gurd
0411803c14 Adds support for Atom Silvermont (SLM) - -march=slm 
Implements Instruction scheduler latencies for Silvermont,
using latencies from the Intel Silvermont Optimization Guide.

Auto detects SLM.

Turns on post RA scheduler when generating code for SLM.

llvm-svn: 190717
 2013-09-13 19:23:28 +00:00
Elena Demikhovsky
139f25ed2c AVX-512: implemented extractelement with variable index. 
Added parsing of mask register and "zeroing" semantic, like {%k1} {z}.

llvm-svn: 190595
 2013-09-12 08:55:00 +00:00
Elena Demikhovsky
04a636836e AVX-512: Added GATHER and SCATTER instructions. 
llvm-svn: 189729
 2013-09-01 14:24:41 +00:00
Elena Demikhovsky
f05835d923 AVX-512: added extend and truncate instructions. 
llvm-svn: 189580
 2013-08-29 11:56:53 +00:00
Elena Demikhovsky
2f3377ea54 AVX-512: added SQRT, VRSQRT14, VCOMISS, VUCOMISS, VRCP14, VPABS 
llvm-svn: 189472
 2013-08-28 11:21:58 +00:00
Elena Demikhovsky
471e732613 AVX-512: added conversion instructions. 
llvm-svn: 189349
 2013-08-27 13:54:04 +00:00
Elena Demikhovsky
8e8304bffc AVX-512: Added FMA instructions. 
llvm-svn: 189326
 2013-08-27 08:39:25 +00:00
Elena Demikhovsky
4333460954 AVX-512: Added shuffle instructions - 
VPSHUFD, VPERMILPS, VMOVDDUP, VMOVLHPS, VMOVHLPS, VSHUFPS, VALIGN
 single and double forms.

llvm-svn: 189215
 2013-08-26 12:45:35 +00:00
Elena Demikhovsky
15c3ef8486 AVX-512: added UNPACK instructions and tests for all-zero/all-ones vectors 
llvm-svn: 189189
 2013-08-25 12:54:30 +00:00
Elena Demikhovsky
5488806c84 AVX-512: Added masked SHIFT commands, more encoding tests 
llvm-svn: 189005
 2013-08-22 12:18:28 +00:00
Elena Demikhovsky
44bbb2b413 AVX-512: Added SHIFT instructions. 
llvm-svn: 188899
 2013-08-21 09:36:02 +00:00
Elena Demikhovsky
f09dad5d90 AVX-512: Added more patterns for VMOVSS, VMOVSD, VMOVD, VMOVQ 
llvm-svn: 188786
 2013-08-20 11:00:29 +00:00
Elena Demikhovsky
f1afd2e4db AVX-512: added arithmetic and logical operations. 
ADD, SUB, MUL integer and FP types. OR, AND, XOR.
Added embeded broadcast form for these instructions.

llvm-svn: 188673
 2013-08-19 13:26:14 +00:00
Elena Demikhovsky
406cf0ea6d AVX-512: Added VMOVD, VMOVQ, VMOVSS, VMOVSD instructions. 
llvm-svn: 188637
 2013-08-18 13:08:57 +00:00
Craig Topper
79189e25c8 Don't use v16i32 for load pattern matching. All 512-bit loads are cated to v8i64. 
llvm-svn: 188534
 2013-08-16 06:07:34 +00:00
Elena Demikhovsky
42b33ee116 AVX-512: Added CMP and BLEND instructions. 
Lowering for SETCC.

llvm-svn: 188265
 2013-08-13 13:24:07 +00:00
Elena Demikhovsky
66a9e4f863 AVX-512: Added VPERM* instructons and MOV* zmm-to-zmm instructions. 
Added a test for shuffles using VPERM.

llvm-svn: 188147
 2013-08-11 07:55:09 +00:00
Elena Demikhovsky
ae2624a373 AVX-512 set: Added BROADCAST instructions 
with lowering logic and a test.

llvm-svn: 187884
 2013-08-07 12:34:55 +00:00
Elena Demikhovsky
cb3f9da2e3 AVX-512 set: added mask operations, lowering BUILD_VECTOR for i1 vector types. 
Added intrinsics and tests.

llvm-svn: 187717
 2013-08-05 08:52:21 +00:00
Elena Demikhovsky
2f33e9fa89 AVX-512 set: added VEXTRACTPS instruction 
llvm-svn: 187705
 2013-08-04 10:46:07 +00:00
Elena Demikhovsky
175a2e60dd Added INSERT and EXTRACT intructions from AVX-512 ISA. 
All insertf*/extractf* functions replaced with insert/extract since we have insertf and inserti forms.
Added lowering for INSERT_VECTOR_ELT / EXTRACT_VECTOR_ELT for 512-bit vectors.
Added lowering for EXTRACT/INSERT subvector for 512-bit vectors.
Added a test.

llvm-svn: 187491
 2013-07-31 11:35:14 +00:00