James Molloy
ac057f13a5
Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler.
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llvm-svn: 139250
2011-09-07 19:42:28 +00:00
Jim Grosbach
f5f321c4ce
Update test for 139243
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llvm-svn: 139244
2011-09-07 18:40:06 +00:00
Owen Anderson
4106b9fb31
Port more assembler tests over to disassembler tests, and fix a minor logic error that exposed.
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llvm-svn: 139240
2011-09-07 17:55:19 +00:00
Owen Anderson
23820ebb17
Port more encoding tests over to Thumb2 decoding tests.
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llvm-svn: 139171
2011-09-06 20:26:34 +00:00
Kevin Enderby
90a1526592
Change X86 disassembly to print immediates values as signed by default. Special
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case those instructions that the immediate is not sign-extend. radr://8795217
llvm-svn: 139028
2011-09-02 20:01:23 +00:00
Kevin Enderby
edfcba2f3c
Fix the disassembly of the X86 "crc32w %ax, %eax" instruction. Bug 10702.
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llvm-svn: 139014
2011-09-02 18:03:03 +00:00
Craig Topper
316c7bfe37
Make IC_VEX* not inherit from IC_*. Prevents instructions with no VEX form from disassembling to their non-VEX form. Also prevents weak filter collisons that were keeping valid VEX instructions from decoding properly. Make VEX_L* not inherit from VEX_* because the VEX.L bit always important. This stops packed int VEX encodings from being disassembled when specified with VEX.L=1. Fixes PR10831 and PR10806.
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llvm-svn: 138997
2011-09-02 04:17:54 +00:00
Owen Anderson
adac5b2109
Fix issues with disassembly of IT instructions involving condition codes other the EQ/NE. Discovered by roundtrip testing.
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llvm-svn: 138840
2011-08-30 22:58:27 +00:00
Owen Anderson
9d3407e7c2
Port Thumb2 assembler tests over to disassembler tests.
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llvm-svn: 138822
2011-08-30 20:03:11 +00:00
Craig Topper
5556444bf7
Add vvvv support to disassembling of instructions with MRMDestMem and MRMDestReg form. Needed to support mem dest form of vmaskmovps/d. Fixes PR10807.
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llvm-svn: 138795
2011-08-30 07:09:35 +00:00
Kevin Enderby
f1aef98ad2
Fix the disassembly of the X86 crc32 instruction. Bug 10702 and rdar://8795217
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llvm-svn: 138771
2011-08-29 22:06:28 +00:00
Owen Anderson
fd21da3506
Improve encoding support for BLX with immediat eoperands, and fix a BLX decoding bug this uncovered.
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llvm-svn: 138675
2011-08-26 23:32:08 +00:00
Owen Anderson
af51fd9868
invalid-LDR_PRE-arm.txt was already passing, but for the wrong reasons. We were failing to specify enough fixed bits of LDR_PRE/LDRB_PRE, resulting in decoding conflicts. Separate them into immediate vs. register versions, allowing us to specify the necessary fixed bits. This in turn results in the test being decoded properly, and being rejected as UNPREDICTABLE rather than a hard failure.
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llvm-svn: 138653
2011-08-26 20:43:14 +00:00
Owen Anderson
86b11d01eb
Support an extension of ARM asm syntax to allow immediate operands to ADR instructions. This is helpful for disassembler testing, and indeed exposed a disassembler bug that is also fixed here.
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llvm-svn: 138635
2011-08-26 18:09:22 +00:00
Owen Anderson
485eda7687
Add a testcase for r138625.
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llvm-svn: 138626
2011-08-26 06:45:08 +00:00
Craig Topper
b20cee1e19
Fix disassembling of VCVTSD2SI
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llvm-svn: 138623
2011-08-26 04:49:29 +00:00
Owen Anderson
d387b48b0b
Port over additional encoding tests to decoding tests, and fix an operand ordering bug this exposed.
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llvm-svn: 138575
2011-08-25 18:30:18 +00:00
Craig Topper
5af7ba783d
Give ATTR_VEX higher priority when generating the disassembler context table. Fixes disassembling of VEX instructions with 'pp'=00. Fixes subset of PR10678.
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llvm-svn: 138552
2011-08-25 07:42:00 +00:00
Craig Topper
06ed6cb856
Add TB encoding to VEROALL, VZEROUPPER, and VCVTPS2PD to allow them to be disassembled. Fixes PR10723.
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llvm-svn: 138551
2011-08-25 06:57:46 +00:00
Owen Anderson
6325690c08
Port over more encoding tests to decoding tests.
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llvm-svn: 138441
2011-08-24 17:08:34 +00:00
Owen Anderson
3de2d7656d
Fix decoding of Thumb2 prefetch instructions, which account for all the remaining Thumb2 decoding failures found by randomized testing so far.
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llvm-svn: 138341
2011-08-23 17:51:38 +00:00
Owen Anderson
9d5074746f
Fix two more instances of mis-matched operand names breaking disassembly. Found by randomized testing.
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llvm-svn: 138337
2011-08-23 17:37:32 +00:00
Owen Anderson
b97912374e
Port more assemble tests over to disassembly tests.
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llvm-svn: 138336
2011-08-23 17:26:35 +00:00
Owen Anderson
d5b7d73696
t2SMLAD is a four-register instruction, not a three-register one.
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llvm-svn: 138301
2011-08-22 23:31:45 +00:00
Owen Anderson
c395a07c42
Correct operand naming of t2USAT16 to allow proper decoding.
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llvm-svn: 138300
2011-08-22 23:27:47 +00:00
Owen Anderson
9e750147fb
Match operand naming to allow correct decoding of t2LDRSH_POST.
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llvm-svn: 138298
2011-08-22 23:22:05 +00:00
Owen Anderson
b400952853
Provide a correct decoder hook for Thumb2 shifted registers. Found by randomized testing.
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llvm-svn: 138292
2011-08-22 23:10:16 +00:00
Owen Anderson
a2231fad2e
Provide operand encoding information for half-precision VCVT instructions. Found by randomized testing.
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llvm-svn: 138273
2011-08-22 21:34:00 +00:00
Owen Anderson
39d3f234f7
Fix decoding of VMOVSRR and VMOVRRS, which account for the overwhelming majority of decoder crashes detected by randomized testing.
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llvm-svn: 138269
2011-08-22 20:27:12 +00:00
Owen Anderson
926f360e53
Fix another batch of VLD/VST decoding crashes discovered by randomized testing.
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llvm-svn: 138255
2011-08-22 18:42:13 +00:00
Owen Anderson
816f5524f8
Correct writeback handling of duplicating VLD instructions. Discovered by randomized testing.
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llvm-svn: 138251
2011-08-22 18:22:06 +00:00
Owen Anderson
e70aed2df9
Port another swathe of Thumb1 encoding tests over to decoding tests.
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llvm-svn: 138250
2011-08-22 18:05:49 +00:00
Owen Anderson
59178665b5
Fix an incorrect shift when decoding SP-relative stores in Thumb1-mode. Add more tests.
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llvm-svn: 138246
2011-08-22 17:56:58 +00:00
Craig Topper
f68d77215d
Add TB encoding to VEX versions of SSE fp logical operations to fix disassembler
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llvm-svn: 138034
2011-08-19 05:28:50 +00:00
Owen Anderson
421e30086e
STC2L_POST and STC2L_POST should be handled the same as STCL_POST/LDC_POST for the purposes of decoding all operands except the predicate.
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Found by randomized testing.
llvm-svn: 138003
2011-08-18 22:47:44 +00:00
Owen Anderson
d113a59074
Fix the decoding of RFE instruction. RFEs have the load bit set, while SRSs have it unset.
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llvm-svn: 138000
2011-08-18 22:31:17 +00:00
Owen Anderson
d121f0e77c
Improve handling of failure and unpredictable cases for CPS, STR, and SMLA instructions.
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Fixes a large class of disassembler crashes found by randomized testing.
llvm-svn: 137995
2011-08-18 22:11:02 +00:00
Jim Grosbach
7ecefeb594
Thumb assembly parsing and encoding for LDM instruction.
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Fix base register type and canonicallize to the "ldm" spelling rather than
"ldmia." Add diagnostics for incorrect writeback token and out-of-range
registers.
llvm-svn: 137986
2011-08-18 21:50:53 +00:00
Owen Anderson
b4bc7704ec
More Thumb1 decoding tests.
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llvm-svn: 137974
2011-08-18 20:05:06 +00:00
James Molloy
5d9ba3b5aa
Test commit; adding test for invalid LDRD which was part of the patch for r137647 but seemingly didn't get svn add'ed.
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llvm-svn: 137960
2011-08-18 18:03:02 +00:00
Owen Anderson
366ac95879
Port over BL/BLX to disassembly tests.
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llvm-svn: 137954
2011-08-18 17:43:52 +00:00
Owen Anderson
eb5c093d8d
Port new Thumb1 encoding tests over to decoding tests.
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llvm-svn: 137902
2011-08-17 23:37:33 +00:00
Owen Anderson
4c26beae4c
Start building a Thumb1 decoding test file based on the Thumb1 parsing/encoding test file.
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llvm-svn: 137840
2011-08-17 18:21:36 +00:00
Owen Anderson
3146968039
Allow the MCDisassembler to return a "soft fail" status code, indicating an instruction that is disassemblable, but invalid. Only used for ARM UNPREDICTABLE instructions at the moment.
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Patch by James Molloy.
llvm-svn: 137830
2011-08-17 17:44:15 +00:00
Owen Anderson
6549866051
Add a test file for Thumb2 NEON.
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llvm-svn: 137687
2011-08-15 23:42:20 +00:00
Owen Anderson
54ded8463c
Add some more comprehensive VFP decoding tests.
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llvm-svn: 137657
2011-08-15 21:29:01 +00:00
Owen Anderson
42946000dd
Enforce the constraint that Rt must be even on LDRD/STRD instructions in ARM mode. Update tests to reflect this fact.
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Patch by James Molloy.
llvm-svn: 137647
2011-08-15 20:51:32 +00:00
Owen Anderson
43b6d1c14e
Add a test for Thumb1 LDRSH decoding.
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llvm-svn: 137645
2011-08-15 20:15:43 +00:00
Owen Anderson
aed8eff14b
Add testcase for STRH. Patch by James Molloy.
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llvm-svn: 137644
2011-08-15 20:12:03 +00:00
Owen Anderson
4854258d9c
Fix incorrect encoding of UMAAL and friends. Patch by James Molloy.
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llvm-svn: 137641
2011-08-15 20:08:25 +00:00