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055ecd8533
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1948 Commits

Author SHA1 Message Date
Chris Lattner
055ecd8533 Only transform (sext (truncate x)) -> (sextinreg x) if before legalize or 
if the target supports the resultant sextinreg

llvm-svn: 24632
 2005-12-07 18:02:05 +00:00
Chris Lattner
8f17c95cc2 Teach the dag combiner to turn a truncate/sign_extend pair into a sextinreg 
when the types match up.  This allows the X86 backend to compile:

sbyte %toggle_value(sbyte* %tmp.1) {
        %tmp.2 = load sbyte* %tmp.1
        ret sbyte %tmp.2
}

to this:

_toggle_value:
        mov %EAX, DWORD PTR [%ESP + 4]
        movsx %EAX, BYTE PTR [%EAX]
        ret

instead of this:

_toggle_value:
        mov %EAX, DWORD PTR [%ESP + 4]
        movsx %EAX, BYTE PTR [%EAX]
        movsx %EAX, %AL
        ret

noticed in Shootout/objinst.

-Chris

llvm-svn: 24630
 2005-12-07 07:11:03 +00:00
Nate Begeman
6c1b8712c5 Teach the SelectionDAG ISel how to turn ConstantPacked values into 
constant nodes with vector types.  Also teach the asm printer how to print
ConstantPacked constant pool entries.  This allows us to generate altivec
code such as the following, which adds a vector constantto a packed float.

LCPI1_0:  <4 x float> < float 0.0e+0, float 0.0e+0, float 0.0e+0, float 1.0e+0 >
        .space  4
        .space  4
        .space  4
        .long   1065353216      ; float 1
        .text
        .align  4
        .globl  _foo
_foo:
        lis r2, ha16(LCPI1_0)
        la r2, lo16(LCPI1_0)(r2)
        li r4, 0
        lvx v0, r4, r2
        lvx v1, r4, r3
        vaddfp v0, v1, v0
        stvx v0, r4, r3
        blr

For the llvm code:

void %foo(<4 x float> * %a) {
entry:
  %tmp1 = load <4 x float> * %a;
  %tmp2 = add <4 x float> %tmp1, < float 0.0, float 0.0, float 0.0, float 1.0 >
  store <4 x float> %tmp2, <4 x float> *%a
  ret void
}

llvm-svn: 24616
 2005-12-06 06:18:55 +00:00
Chris Lattner
46ac4d0810 Fix the #1 code quality problem that I have seen on X86 (and it also affects 
PPC and other targets).  In a particular, consider code like this:

struct Vector3 { double x, y, z; };
struct Matrix3 { Vector3 a, b, c; };
double dot(Vector3 &a, Vector3 &b) {
   return a.x * b.x  +  a.y * b.y  +  a.z * b.z;
}
Vector3 mul(Vector3 &a, Matrix3 &b) {
   Vector3 r;
   r.x = dot( a, b.a );
   r.y = dot( a, b.b );
   r.z = dot( a, b.c );
   return r;
}
void transform(Matrix3 &m, Vector3 *x, int n) {
   for (int i = 0; i < n; i++)
      x[i] = mul( x[i], m );
}

we compile transform to a loop with all of the GEP instructions for indexing
into 'm' pulled out of the loop (9 of them).  Because isel occurs a bb at a time
we are unable to fold the constant index into the loads in the loop, leading to
PPC code that looks like this:

LBB3_1: ; no_exit.preheader
        li r2, 0
        addi r6, r3, 64        ;; 9 values live across the loop body!
        addi r7, r3, 56
        addi r8, r3, 48
        addi r9, r3, 40
        addi r10, r3, 32
        addi r11, r3, 24
        addi r12, r3, 16
        addi r30, r3, 8
LBB3_2: ; no_exit
        lfd f0, 0(r30)
        lfd f1, 8(r4)
        fmul f0, f1, f0
        lfd f2, 0(r3)        ;; no constant indices folded into the loads!
        lfd f3, 0(r4)
        lfd f4, 0(r10)
        lfd f5, 0(r6)
        lfd f6, 0(r7)
        lfd f7, 0(r8)
        lfd f8, 0(r9)
        lfd f9, 0(r11)
        lfd f10, 0(r12)
        lfd f11, 16(r4)
        fmadd f0, f3, f2, f0
        fmul f2, f1, f4
        fmadd f0, f11, f10, f0
        fmadd f2, f3, f9, f2
        fmul f1, f1, f6
        stfd f0, 0(r4)
        fmadd f0, f11, f8, f2
        fmadd f1, f3, f7, f1
        stfd f0, 8(r4)
        fmadd f0, f11, f5, f1
        addi r29, r4, 24
        stfd f0, 16(r4)
        addi r2, r2, 1
        cmpw cr0, r2, r5
        or r4, r29, r29
        bne cr0, LBB3_2 ; no_exit

uh, yuck.  With this patch, we now sink the constant offsets into the loop, producing
this code:

LBB3_1: ; no_exit.preheader
        li r2, 0
LBB3_2: ; no_exit
        lfd f0, 8(r3)
        lfd f1, 8(r4)
        fmul f0, f1, f0
        lfd f2, 0(r3)
        lfd f3, 0(r4)
        lfd f4, 32(r3)       ;; much nicer.
        lfd f5, 64(r3)
        lfd f6, 56(r3)
        lfd f7, 48(r3)
        lfd f8, 40(r3)
        lfd f9, 24(r3)
        lfd f10, 16(r3)
        lfd f11, 16(r4)
        fmadd f0, f3, f2, f0
        fmul f2, f1, f4
        fmadd f0, f11, f10, f0
        fmadd f2, f3, f9, f2
        fmul f1, f1, f6
        stfd f0, 0(r4)
        fmadd f0, f11, f8, f2
        fmadd f1, f3, f7, f1
        stfd f0, 8(r4)
        fmadd f0, f11, f5, f1
        addi r6, r4, 24
        stfd f0, 16(r4)
        addi r2, r2, 1
        cmpw cr0, r2, r5
        or r4, r6, r6
        bne cr0, LBB3_2 ; no_exit

This is much nicer as it reduces register pressure in the loop a lot.  On X86,
this takes the function from having 9 spilled registers to 2.  This should help
some spec programs on X86 (gzip?)

This is currently only enabled with -enable-gep-isel-opt to allow perf testing
tonight.

llvm-svn: 24606
 2005-12-05 07:10:48 +00:00
Chris Lattner
07f4a0cb99 dbg.stoppoint returns a value, don't forget to init it 
llvm-svn: 24583
 2005-12-03 18:50:48 +00:00
Andrew Lenharth
a38ab7b996 bah, must generate all results 
llvm-svn: 24574
 2005-12-02 06:08:08 +00:00
Andrew Lenharth
9662af8cdc cycle counter fix 
llvm-svn: 24573
 2005-12-02 04:56:24 +00:00
Chris Lattner
b5cc216fad Don't remove two operand, two result nodes from the binary ops map. These 
should come from the arbitrary ops map.

This fixes Regression/CodeGen/PowerPC/2005-12-01-Crash.ll

llvm-svn: 24571
 2005-12-01 23:14:50 +00:00
Chris Lattner
29f6c8928b Promote line and column number information for our friendly 64-bit targets. 
llvm-svn: 24568
 2005-12-01 18:21:35 +00:00
Chris Lattner
282123f7fc This is a bugfix for SelectNodeTo. In certain situations, we could be 
selecting a node and use a mix of getTargetNode() and SelectNodeTo.  Because
SelectNodeTo didn't check the CSE maps for a preexisting node and didn't insert
its result into the CSE maps, we would sometimes miss a CSE opportunity.

This is extremely rare, but worth fixing for completeness.

llvm-svn: 24565
 2005-12-01 18:00:57 +00:00
Nate Begeman
811a41a87c Support multiple ValueTypes per RegisterClass, needed for upcoming vector 
work.  This change has no effect on generated code.

llvm-svn: 24563
 2005-12-01 04:51:06 +00:00
Chris Lattner
7bed501258 Make SelectNodeTo return N 
llvm-svn: 24548
 2005-11-30 22:45:14 +00:00
Chris Lattner
5af54cb0fe CALLSEQ_START/END nodes don't get memoized, do not add them in when 
replaceAllUses'ing.

llvm-svn: 24539
 2005-11-30 18:20:52 +00:00
Andrew Lenharth
3836ea30ac At long last, you can say that f32 isn't supported for setcc 
llvm-svn: 24537
 2005-11-30 17:12:26 +00:00
Nate Begeman
31121419c8 First chunk of actually generating vector code for packed types. These 
changes allow us to generate the following code:

_foo:
        li r2, 0
        lvx v0, r2, r3
        vaddfp v0, v0, v0
        stvx v0, r2, r3
        blr

for this llvm:

void %foo(<4 x float>* %a) {
entry:
        %tmp1 = load <4 x float>* %a
        %tmp2 = add <4 x float> %tmp1, %tmp1
        store <4 x float> %tmp2, <4 x float>* %a
        ret void
}

llvm-svn: 24534
 2005-11-30 08:22:07 +00:00
Andrew Lenharth
e14b9bfddf add support for custom lowering SINT_TO_FP 
llvm-svn: 24531
 2005-11-30 06:43:03 +00:00
Reid Spencer
3bac59d2f0 Fix a problem with llvm-ranlib that (on some platforms) caused the archive 
file to become corrupted due to interactions between mmap'd memory segments
and file descriptors closing. The problem is completely avoiding by using
a third temporary file.

Patch provided by Evan Jones

llvm-svn: 24527
 2005-11-30 05:21:10 +00:00
Evan Cheng
08ab45044b Fixed a bug introduced by my last commit: TargetGlobalValues should key on 
GlobalValue * and index pair. Update getGlobalAddress() for symmetry.

llvm-svn: 24524
 2005-11-30 02:49:21 +00:00
Evan Cheng
025dab1137 Added an index field to GlobalAddressSDNode so it can represent X+12, etc. 
llvm-svn: 24523
 2005-11-30 02:04:11 +00:00
Chris Lattner
22327b9d12 Add support for a new STRING and LOCATION node for line number support, patch 
contributed by Daniel Berlin, with a few cleanups here and there by me.

llvm-svn: 24515
 2005-11-29 06:21:05 +00:00
Nate Begeman
a1c2df2471 Add the majority of the vector machien value types we expect to support, 
and make a few changes to the legalization machinery to support more than
16 types.

llvm-svn: 24511
 2005-11-29 05:45:29 +00:00
Nate Begeman
a90bb6d9b1 Check in code to scalarize arbitrarily wide packed types for some simple 
vector operations (load, add, sub, mul).

This allows us to codegen:
void %foo(<4 x float> * %a) {
entry:
  %tmp1 = load <4 x float> * %a;
  %tmp2 = add <4 x float> %tmp1, %tmp1
  store <4 x float> %tmp2, <4 x float> *%a
  ret void
}

on ppc as:
_foo:
        lfs f0, 12(r3)
        lfs f1, 8(r3)
        lfs f2, 4(r3)
        lfs f3, 0(r3)
        fadds f0, f0, f0
        fadds f1, f1, f1
        fadds f2, f2, f2
        fadds f3, f3, f3
        stfs f0, 12(r3)
        stfs f1, 8(r3)
        stfs f2, 4(r3)
        stfs f3, 0(r3)
        blr

llvm-svn: 24484
 2005-11-22 18:16:00 +00:00
Nate Begeman
d2f6fcf327 Rather than attempting to legalize 1 x float, make sure the SD ISel never 
generates it.  Make MVT::Vector expand-only, and remove the code in
Legalize that attempts to legalize it.

The plan for supporting N x Type is to continually epxand it in ExpandOp
until it gets down to 2 x Type, where it will be scalarized into a pair of
scalars.

llvm-svn: 24482
 2005-11-22 01:29:36 +00:00
Duraid Madina
04be8e167c I think I know what you meant here, but just to be safe I'll let you 
do it. :)

    <_sabre_> excuses excuses

llvm-svn: 24471
 2005-11-21 14:09:40 +00:00
Chris Lattner
3820bdc84c Allow target to customize directive used to switch to arbitrary section in SwitchSection, 
add generic constant pool emitter

llvm-svn: 24464
 2005-11-21 08:25:09 +00:00
Chris Lattner
3ad9bee9a4 increment the function number in SetupMachineFunction 
llvm-svn: 24461
 2005-11-21 08:13:27 +00:00
Chris Lattner
4c1efb2a29 Adjust to capitalized asmprinter method names 
llvm-svn: 24457
 2005-11-21 07:51:36 +00:00
Chris Lattner
f78eca1416 Add section switching to common code generator code. Add a couple of 
asserts.

llvm-svn: 24445
 2005-11-21 07:06:27 +00:00
Chris Lattner
bc0a6be68a Legalize MERGE_VALUES, expand READCYCLECOUNTER correctly, so it doesn't 
break control dependence.

llvm-svn: 24437
 2005-11-20 22:56:56 +00:00
Andrew Lenharth
b44263313a The first patch of X86 support for read cycle counter 
llvm-svn: 24429
 2005-11-20 21:32:07 +00:00
Chris Lattner
c830542c70 more progress towards bug 291 being finished. Patch by Owen Anderson, 
HAVE_GV case fixed up by me.

llvm-svn: 24428
 2005-11-20 03:45:52 +00:00
Chris Lattner
517942843d Unbreak codegen of bools. This should fix the llc/jit/llc-beta failures 
from last night.

llvm-svn: 24427
 2005-11-19 18:40:42 +00:00
Chris Lattner
fc1975aa3b Improve Selection DAG printer portability. Patch by Owen Anderson! 
llvm-svn: 24425
 2005-11-19 07:44:09 +00:00
Chris Lattner
72dc36da76 Teach the graph viewer to handle register operands that are zero. 
llvm-svn: 24421
 2005-11-19 06:58:46 +00:00
Chris Lattner
3a1a1557e1 Silence a bogus warning 
llvm-svn: 24420
 2005-11-19 05:51:46 +00:00
Chris Lattner
89056c7145 Add some method variants, patch by Evan Cheng 
llvm-svn: 24418
 2005-11-19 01:44:53 +00:00
Nate Begeman
7d513f65ae Teach LLVM how to scalarize packed types. Currently, this only works on 
packed types with an element count of 1, although more generic support is
coming.  This allows LLVM to turn the following code:

void %foo(<1 x float> * %a) {
entry:
  %tmp1 = load <1 x float> * %a;
  %tmp2 = add <1 x float> %tmp1, %tmp1
  store <1 x float> %tmp2, <1 x float> *%a
  ret void
}

Into:

_foo:
        lfs f0, 0(r3)
        fadds f0, f0, f0
        stfs f0, 0(r3)
        blr

llvm-svn: 24416
 2005-11-19 00:36:38 +00:00
Nate Begeman
78ac456d32 Split out the shift code from visitBinary. 
llvm-svn: 24412
 2005-11-18 07:42:56 +00:00
Chris Lattner
0b177075c2 Allow targets to custom legalize leaf nodes like GlobalAddress. 
llvm-svn: 24387
 2005-11-17 06:41:44 +00:00
Chris Lattner
48668daec3 Teach legalize about targetglobaladdress 
llvm-svn: 24385
 2005-11-17 05:52:24 +00:00
Chris Lattner
2095b19912 when debugging lower dbg intrinsics to calls 
llvm-svn: 24377
 2005-11-16 07:22:30 +00:00
Chris Lattner
5d9032c0e9 Remove extraneous parents around constants when using a constant expr cast. 
llvm-svn: 24357
 2005-11-15 00:03:16 +00:00
Chris Lattner
389e3bfb0c Teach emitAlignment to handle explicit alignment requests by globals. 
llvm-svn: 24354
 2005-11-14 19:00:06 +00:00
Jeff Cohen
566c6d987a Fix operator precedence bug caught by VC++. 
llvm-svn: 24318
 2005-11-12 00:59:01 +00:00
Andrew Lenharth
9b036b1bdb added a chain output 
llvm-svn: 24306
 2005-11-11 22:48:54 +00:00
Andrew Lenharth
dca2f13e76 continued readcyclecounter support 
llvm-svn: 24300
 2005-11-11 16:47:30 +00:00
Chris Lattner
b6d5dcd181 nuke blank line 
llvm-svn: 24278
 2005-11-10 18:49:46 +00:00
Chris Lattner
4868465cb6 Get rid of casts by #including the right header 
llvm-svn: 24275
 2005-11-10 18:36:17 +00:00
Chris Lattner
aa86c10fe6 Compile C strings to: 
l1__2E_str_1:                           ; '.str_1'
        .asciz  "foo"

not:

        .align  0
l1__2E_str_1:                           ; '.str_1'
        .asciz  "foo"

llvm-svn: 24273
 2005-11-10 18:09:27 +00:00
Chris Lattner
88c7013f18 add support for .asciz, and enable it by default. If your target assemblerdoesn't support .asciz, just set AscizDirective to null in your asmprinter. 
This compiles C strings to:

l1__2E_str_1:                           ; '.str_1'
        .asciz  "foo"

instead of:

l1__2E_str_1:                           ; '.str_1'
        .ascii  "foo\000"

llvm-svn: 24272
 2005-11-10 18:06:33 +00:00