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05c784cc30
Commit Graph

519 Commits

Author SHA1 Message Date
Evan Cheng
05c784cc30 Update. 
llvm-svn: 38513
 2007-07-10 21:49:47 +00:00
Evan Cheng
abcf3842bb Remove clobbersPred. Add an OptionalDefOperand to instructions which have the 's' bit. 
llvm-svn: 38501
 2007-07-10 18:08:01 +00:00
Chris Lattner
4810c53b05 The various "getModuleMatchQuality" implementations should return 
zero if they see a target triple they don't understand.

llvm-svn: 38463
 2007-07-09 17:25:29 +00:00
Evan Cheng
d9d3be078c No need for ccop anymore. 
llvm-svn: 37965
 2007-07-06 23:34:09 +00:00
Evan Cheng
92e624a6f7 Incorrect check. 
llvm-svn: 37962
 2007-07-06 23:23:19 +00:00
Evan Cheng
3b1b3eba6a Do away with ImmutablePredicateOperand. 
llvm-svn: 37961
 2007-07-06 23:22:46 +00:00
Evan Cheng
721b83bbe6 Print the s bit if the instruction is toggled to its CPSR setting form. 
llvm-svn: 37932
 2007-07-06 01:01:34 +00:00
Evan Cheng
c2c0b495ed PredicateDefOperand -> OptionalDefOperand. 
llvm-svn: 37931
 2007-07-06 01:00:49 +00:00
Evan Cheng
96254545ae Initial ARM JIT support by Raul Fernandes Herbster. 
llvm-svn: 37926
 2007-07-05 21:15:40 +00:00
Evan Cheng
a59422068f Unbreak the build. 
llvm-svn: 37914
 2007-07-05 17:13:19 +00:00
Gabor Greif
5f705671e4 Here is the bulk of the sanitizing. 
Almost all occurrences of "bytecode" in the sources have been eliminated.

llvm-svn: 37913
 2007-07-05 17:07:56 +00:00
Evan Cheng
be54fdf431 Reflects the chanegs made to PredicateOperand. 
llvm-svn: 37898
 2007-07-05 07:18:20 +00:00
Evan Cheng
3d2cfd8bb1 Added ARM::CPSR to represent ARM CPSR status register. 
llvm-svn: 37897
 2007-07-05 07:17:13 +00:00
Evan Cheng
2403cc41ea Unfortunately we now require C++ code to isel Bcc, conditional moves, etc. 
llvm-svn: 37896
 2007-07-05 07:15:27 +00:00
Evan Cheng
ef8a1bcbc3 Each ARM use predicate operand is now made up of two components. The new component is the CPSR register. 
llvm-svn: 37895
 2007-07-05 07:13:32 +00:00
Evan Cheng
4af116139b Added ARM::CPSR to represent ARM CPSR status register. 
llvm-svn: 37894
 2007-07-05 07:11:03 +00:00
John Criswell
57e5ed4b5a Convert .cvsignore files 
llvm-svn: 37801
 2007-06-29 16:35:07 +00:00
Evan Cheng
5506831e5b Silence a warning. 
llvm-svn: 37737
 2007-06-26 18:31:22 +00:00
Dan Gohman
9cbc3fb1ab Revert the earlier change that removed the M_REMATERIALIZABLE machine 
instruction flag, and use the flag along with a virtual member function
hook for targets to override if there are instructions that are only
trivially rematerializable with specific operands (i.e. constant pool
loads).

llvm-svn: 37728
 2007-06-26 00:48:07 +00:00
Owen Anderson
89558a0db6 Fix the build. 
llvm-svn: 37705
 2007-06-22 16:59:54 +00:00
Dan Gohman
a62327ea40 Move ComputeMaskedBits, MaskedValueIsZero, and ComputeNumSignBits from 
TargetLowering to SelectionDAG so that they have more convenient
access to the current DAG, in preparation for the ValueType routines
being changed from standalone functions to members of SelectionDAG for
the pre-legalize vector type changes.

llvm-svn: 37704
 2007-06-22 14:59:07 +00:00
Dale Johannesen
e1c767df50 Quote complex names for Darwin X86 and ARM. 
llvm-svn: 37700
 2007-06-22 00:54:56 +00:00
Evan Cheng
5da7b6f0fc Be more conservative of duplicating blocks. 
llvm-svn: 37669
 2007-06-19 23:55:02 +00:00
Evan Cheng
c49382e48f Allow predicated immediate ARM to ARM calls. 
llvm-svn: 37659
 2007-06-19 21:05:09 +00:00
Dan Gohman
b60d8a92c9 Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoad 
with a general target hook to identify rematerializable instructions. Some
instructions are only rematerializable with specific operands, such as loads
from constant pools, while others are always rematerializable. This hook
allows both to be identified as being rematerializable with the same
mechanism.

llvm-svn: 37644
 2007-06-19 01:48:05 +00:00
Evan Cheng
12b3002673 Replace TargetInstrInfo::CanBeDuplicated() with a M_NOT_DUPLICABLE bit. 
llvm-svn: 37643
 2007-06-19 01:26:51 +00:00
Evan Cheng
e6d0631c68 Instructions with unique labels or embedded jumptables cannot be duplicated during ifcvt. 
llvm-svn: 37606
 2007-06-15 21:15:00 +00:00
Dale Johannesen
7e3253f115 Handle blocks with 2 unconditional branches in AnalyzeBranch. 
llvm-svn: 37571
 2007-06-13 17:59:52 +00:00
Evan Cheng
1a6c0341fd Add a utility routine to check for unpredicated terminator instruction. 
llvm-svn: 37528
 2007-06-08 21:59:56 +00:00
Lauro Ramos Venancio
ec8ae8443a Define AsmTransCBE for ARM. 
llvm-svn: 37527
 2007-06-08 21:06:23 +00:00
Evan Cheng
4c6df8ba37 Fix ARM condition code subsumission check. 
llvm-svn: 37517
 2007-06-08 09:14:47 +00:00
Evan Cheng
8eff719058 tBcc is not a barrier. 
llvm-svn: 37516
 2007-06-08 09:13:23 +00:00
Evan Cheng
9f23724d53 Stupid cut-n-paste bug caused me soooo much grief. Why wasn't there a compilation warning? I blame it on the FE folks. 
llvm-svn: 37484
 2007-06-07 01:37:54 +00:00
Evan Cheng
7b433a2954 Mark these instructions clobbersPred. They modify the condition code register. 
llvm-svn: 37468
 2007-06-06 10:17:05 +00:00
Evan Cheng
886c1f49ca Print predicate of the second instruction of the two-piece constant MI. 
llvm-svn: 37437
 2007-06-05 18:55:18 +00:00
Evan Cheng
820e352652 PIC label asm printing cosmetic changes. 
llvm-svn: 37434
 2007-06-05 07:36:38 +00:00
Chris Lattner
8a38eebb69 update this entry, now that Anton implemented shift/and lowering for 
switches.  There is one really easy isel thing here with tst we are not
getting.

llvm-svn: 37400
 2007-06-02 18:45:14 +00:00
Evan Cheng
8a52b80cdf Opcode modifier s comes after condition code. e.g. addlts, not addslt. 
llvm-svn: 37388
 2007-06-01 20:51:29 +00:00
Evan Cheng
8589b95a33 Set ARM ifcvt duplication limit to 3 for now. 
llvm-svn: 37385
 2007-06-01 08:28:59 +00:00
Evan Cheng
c2fec89f4a Make jumptable non-predicable for now. 
llvm-svn: 37381
 2007-06-01 00:56:15 +00:00
Chris Lattner
72e07238ba Fix the asmprinter so that a globalvalue can specify an explicit alignment 
smaller than the preferred alignment, but so that the target can actually
specify a minimum alignment if needed.  This fixes some objc protocol
failures Devang tracked down.

llvm-svn: 37373
 2007-05-31 18:57:45 +00:00
Evan Cheng
3672d15956 For VFP2 fldm, fstm instructions, the condition code is printed after the address mode and size specifier. e.g. fstmiaseq, not fstmeqias. 
llvm-svn: 37351
 2007-05-29 23:34:19 +00:00
Evan Cheng
5df14b3451 For ldrb, strh, etc., the condition code is before the width specifier. e.g. streqh, not strheq. 
llvm-svn: 37349
 2007-05-29 23:32:06 +00:00
Evan Cheng
ff31eed2be Add missing const qualifiers. 
llvm-svn: 37342
 2007-05-29 18:42:18 +00:00
Evan Cheng
80122ab529 Hooks for predication support. 
llvm-svn: 37308
 2007-05-23 07:22:05 +00:00
Evan Cheng
f448047ec2 Fix some -march=thumb regressions. tBR_JTr is not predicable. 
llvm-svn: 37272
 2007-05-21 23:17:32 +00:00
Dale Johannesen
f01566b705 Use AXI3 not AXI2 for appropriate PIC PC-relative loads and stores. Cosmetic. 
llvm-svn: 37271
 2007-05-21 22:42:04 +00:00
Dale Johannesen
8f484d16b0 Add some patterns for PIC PC-relative loads and stores. 
llvm-svn: 37269
 2007-05-21 22:14:33 +00:00
Evan Cheng
d173398eee BlockHasNoFallThrough() now returns true if block ends with a return instruction; AnalyzeBranch() should ignore predicated instructionsd. 
llvm-svn: 37268
 2007-05-21 18:56:31 +00:00
Evan Cheng
e875732104 Mark calls non-predicable for now. Need to ensure it's the last instruction in the if-converted block or make sure it preserve condition code. 
llvm-svn: 37199
 2007-05-18 01:53:54 +00:00