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Author SHA1 Message Date
Manman Ren
06642dda56 Debug Info: use null instead of "i32 0" in DIBuilder. 
For context field of subroutine_type and when creating artificial types.

llvm-svn: 190270
 2013-09-08 06:00:42 +00:00
Manman Ren
ff3c6f3af6 Debug Info: pass in DIScope instead of DIDescriptor in createMemberType. 
Improve readability. No functionality change.

llvm-svn: 190269
 2013-09-08 04:07:59 +00:00
Manman Ren
fa420c3e35 Debug Info Testing: update context from empty string to null. 
Context should be either null or MDNode.

llvm-svn: 190267
 2013-09-08 03:11:54 +00:00
Craig Topper
ac623f26d9 Add neverHasSideEffects=1 on a couple move instructions. 
llvm-svn: 190259
 2013-09-08 00:50:45 +00:00
Craig Topper
9f2cedc02b Using popcount should check the popcount feature flag not the SSE41 feature flag. 
llvm-svn: 190258
 2013-09-08 00:47:31 +00:00
Bill Wendling
e36b8e4d0f Run clang-format on these header files. Part of a WIP. 
llvm-svn: 190250
 2013-09-07 11:55:36 +00:00
Akira Hatanaka
3fb22c57eb [mips] Fix typos. 
llvm-svn: 190236
 2013-09-07 01:14:42 +00:00
Akira Hatanaka
3eef445630 [mips] Enhance command line option "-mno-ldc1-sdc1" to expand base+index double 
precision loads and stores as well as reg+imm double precision loads and stores.

Previously, expansion of loads and stores was done after register allocation,
but now it takes place during legalization. As a result, users will see double
precision stores and loads being emitted to spill and restore 64-bit FP registers.

llvm-svn: 190235
 2013-09-07 00:52:30 +00:00
Akira Hatanaka
dec2e8eaf5 [mips] Place parentheses around && to silence warning. 
llvm-svn: 190234
 2013-09-07 00:26:26 +00:00
Richard Smith
8f327c0a19 Remove verifier check that attribute 'builtin' is only applied to calls to 
functions marked 'nobuiltin'. That approach doesn't play well with LTO, and
there's no harm in marking a call as 'builtin' if it was going to be a builtin
regardless.

llvm-svn: 190233
 2013-09-07 00:25:48 +00:00
Akira Hatanaka
609795bca8 [mips] Add definition of instruction "drotr32" (double rotate right plus 32). 
llvm-svn: 190232
 2013-09-07 00:18:01 +00:00
Manman Ren
efdb887d1f Debug Info: Use identifier to reference DIType in containing type field of 
a DISubprogram.
    
Verifier is updated accordingly.

llvm-svn: 190229
 2013-09-07 00:04:05 +00:00
Akira Hatanaka
c11e303acd [mips] Use uimm5 and uimm6 instead of shamt and imm, if the immediate has to fit 
into a 5-bit or 6-bit field.

llvm-svn: 190226
 2013-09-07 00:02:02 +00:00
Manman Ren
77b027d507 Debug Info: pass in VTableHolder as DIType instead of MDNode *. 
Remove one cast and improve readability. No functionality change.

llvm-svn: 190225
 2013-09-06 23:54:23 +00:00
Akira Hatanaka
df8ec492f1 [mips] Define "trap" as a pseudo instruction that turns into "break 0, 0". 
llvm-svn: 190224
 2013-09-06 23:52:46 +00:00
Akira Hatanaka
4d3cb5afc3 [mips] Delete unused classes and defs. 
llvm-svn: 190221
 2013-09-06 23:42:58 +00:00
Akira Hatanaka
e685abb384 [mips] Make "b" (unconditional branch) a pseudo. "b" is an assembly idiom, which is 
equivalent to "beq $zero, $zero, offset".

llvm-svn: 190220
 2013-09-06 23:40:15 +00:00
Akira Hatanaka
b84769b3d7 [mips] Set instruction itineraries of loads, stores and conditional moves. 
llvm-svn: 190219
 2013-09-06 23:28:24 +00:00
Manman Ren
de03bcdbec TBAA: add isTBAAVtableAccess to MDNode so clients can call the function 
instead of having its own implementation.

The implementation of isTBAAVtableAccess is in TypeBasedAliasAnalysis.cpp
since it is related to the format of TBAA metadata.

The path for struct-path tbaa will be exercised by
test/Instrumentation/ThreadSanitizer/read_from_global.ll, vptr_read.ll, and
vptr_update.ll when struct-path tbaa is on by default.

llvm-svn: 190216
 2013-09-06 22:47:05 +00:00
Manman Ren
450526b5a9 Debug Info Testing: updated to use NULL instead of "i32 0" in a few fields. 
Field 2 of DIType (Context), field 9 of DIDerivedType (TypeDerivedFrom),
field 12 of DICompositeType (ContainingType), fields 2, 7, 12 of DISubprogram
(Context, Type, ContainingType).

llvm-svn: 190205
 2013-09-06 21:03:58 +00:00
Aaron Watry
e4512c5eff R600: Add support for LDS atomic subtract 
Signed-off-by: Aaron Watry <awatry@gmail.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 190200
 2013-09-06 20:17:42 +00:00
Manman Ren
43a86dc31f Debug Info: Use identifier to reference DIType in containing type field of 
a DICompositeType.
    
Verifier is updated accordingly.

llvm-svn: 190190
 2013-09-06 18:46:00 +00:00
Manman Ren
e1b6e40ead Debug Info: Move a helper function getTypeIdentifier from DIBuilder to be part 
of DIType.
    
Implement DIType::generateRef to return a type reference. This function will be
used in setContaintingType and in DIBuilder to generete the type reference.
    
No functionality change.

llvm-svn: 190188
 2013-09-06 18:27:00 +00:00
Manman Ren
3a3457bef0 Debug Info Testing: Updated to use null instead of "i32 0" for containing-type 
field of DICompositeType.

This will help the follow-on patch of using DITypeRef for containing-type field.

llvm-svn: 190187
 2013-09-06 18:13:59 +00:00
Adrian Prantl
271495ae9a debuginfo-tests: Add support for an lldb wrapper script 
to be used on darwin in lieu of gdb.

llvm-svn: 190186
 2013-09-06 18:12:01 +00:00
Andrew Trick
0d8da69006 mi-sched: cleanup register pressure update, remove a FIXME. 
llvm-svn: 190181
 2013-09-06 17:32:47 +00:00
Andrew Trick
2792f17795 mi-sched: improve regpressure tracing. 
llvm-svn: 190180
 2013-09-06 17:32:44 +00:00
Andrew Trick
6f423c533c mi-sched: print tree size in -view-misched-dags 
llvm-svn: 190179
 2013-09-06 17:32:42 +00:00
Andrew Trick
735ce8c85e mi-sched: register pressure update tracing. 
llvm-svn: 190178
 2013-09-06 17:32:39 +00:00
Andrew Trick
0c6ae850b7 mi-sched: Reorder Cyclicpath (latency) and CriticalMax (pressure) heuristics. 
The latency based scheduling could induce spills in some cases.

llvm-svn: 190177
 2013-09-06 17:32:36 +00:00
Andrew Trick
bf56e1926d Added MachineSchedPolicy. 
Allow subtargets to customize the generic scheduling strategy.
This is convenient for targets that don't need to add new heuristics
by specializing the strategy.

llvm-svn: 190176
 2013-09-06 17:32:34 +00:00
Hans Wennborg
5265ac9dbf msbuild integration: provide separate files for VS2010 and VS2012 
The previous msbuild integration only worked if VS2010 was installed. This patch
renames the current integration to LLVM-vs2010 and adds LLVM-vs2012.

Differential Revision: http://llvm-reviews.chandlerc.com/D1614

llvm-svn: 190173
 2013-09-06 17:05:46 +00:00
Matthias Braun
667850a4b2 avoid unnecessary direct access to LiveInterval::ranges 
llvm-svn: 190170
 2013-09-06 16:44:32 +00:00
Matthias Braun
c8c6a4ff0d remove unused argument from LiveRanges::join() 
llvm-svn: 190169
 2013-09-06 16:44:29 +00:00
Matthias Braun
df0ba22e8a remove pointless assert 
The if above it ensures the property anyway.

llvm-svn: 190168
 2013-09-06 16:44:27 +00:00
Matthias Braun
3de3ef9ed7 fix comment 
There's no 'B3' in the example.

llvm-svn: 190167
 2013-09-06 16:44:25 +00:00
Matthias Braun
15fb34e896 fix typo in comment 
llvm-svn: 190165
 2013-09-06 16:19:22 +00:00
Daniel Sanders
10a7da8f65 [mips][msa] Indentation 
llvm-svn: 190156
 2013-09-06 13:25:06 +00:00
Daniel Sanders
11008ea159 [mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance 
Tested with 'llvm-tblgen -print-records' which outputs identical records before
and after this patch.

llvm-svn: 190155
 2013-09-06 13:15:05 +00:00
Vladimir Medic
d17f16c84f This patch adds support for microMIPS Multiply and Add/Sub instructions. Test cases are included in patch. 
llvm-svn: 190154
 2013-09-06 13:08:00 +00:00
Daniel Sanders
22d0137a75 [mips][msa] Made the operand register sets optional for the VEC formats 
Their default is to be the same as the result register set.

No functional change

llvm-svn: 190153
 2013-09-06 13:01:47 +00:00
Vladimir Medic
c122b6c139 This patch adds support for microMIPS Move to/from HI/LO instructions. Test cases are included in patch. 
llvm-svn: 190152
 2013-09-06 12:53:21 +00:00
Daniel Sanders
0eb9e53280 [mips][msa] Made the operand register sets optional for the ELM_INSVE formats 
Their default is to be the same as the result register set.

No functional change

llvm-svn: 190151
 2013-09-06 12:50:52 +00:00
Daniel Sanders
cb68899283 [mips][msa] Made the operand register sets optional for the 3RF_4RF format 
Their default is to be the same as the result register set.

No functional change

llvm-svn: 190150
 2013-09-06 12:44:13 +00:00
Vladimir Medic
a00506588f This patch adds support for microMIPS Move Conditional instructions. Test cases are included in patch. 
llvm-svn: 190148
 2013-09-06 12:41:17 +00:00
Tim Northover
5e921518f7 SelectionDAG: create correct BooleanContent constants 
Occasionally DAGCombiner can spot that a SETCC operation is completely
redundant and reduce it to "all true" or "all false". If this happens to a
vector, the value produced has to take account of what a normal comparison
would have produced, which may be an all-1s bitmask.

The fix in SelectionDAG.cpp is tested, however, as far as I can see the code in
TargetLowering.cpp is possibly unreachable and almost certainly irrelevant when
triggered so there are no tests. However, I believe it's still clearly the
right change and may save someone else some hassle if it suddenly becomes
reachable. So I'm doing it anyway.

llvm-svn: 190147
 2013-09-06 12:38:12 +00:00
Daniel Sanders
d9577fe859 [mips][msa] Made the operand register sets optional for the 3RF formats 
Their default is to be the same as the result register set.

No functional change

llvm-svn: 190146
 2013-09-06 12:32:57 +00:00
Daniel Sanders
6089833291 [mips][msa] Made the operand register sets optional for the 3R_4R format 
Their default is to be the same as the result register set.

No functional change

llvm-svn: 190145
 2013-09-06 12:30:43 +00:00
Vladimir Medic
0c18f0f6ce This patch adds support for microMIPS disassembler and disassembler make check tests. 
llvm-svn: 190144
 2013-09-06 12:30:36 +00:00
Daniel Sanders
e8f95344a5 [mips][msa] Made the operand register sets optional for the 2RF format 
Their default is to be the same as the result register set.

No functional change

llvm-svn: 190143
 2013-09-06 12:28:13 +00:00