Elena Demikhovsky
4e301fd23f
AVX-512: Fixed masked load / store instruction selection for KNL.
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Patterns were missing for KNL target for <8 x i32>, <8 x float> masked load/store.
This intrinsic comes with all legal types:
<8 x float> @llvm.masked.load.v8f32(<8 x float>* %addr, i32 align, <8 x i1> %mask, <8 x float> %passThru),
but still requires lowering, because VMASKMOVPS, VMASKMOVDQU32 work with 512-bit vectors only.
All data operands should be widened to 512-bit vector.
The mask operand should be widened to v16i1 with zeroes.
Differential Revision: http://reviews.llvm.org/D15265
llvm-svn: 254909
2015-12-07 13:39:24 +00:00
Igor Breger
2e5da39635
AVX-512: implement kunpck intrinsics.
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Differential Revision: http://reviews.llvm.org/D14821
llvm-svn: 254908
2015-12-07 13:25:18 +00:00
Asaf Badouh
903869d4c1
[X86][AVX512] add vmovss/sd missing encoding
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Differential Revision: http://reviews.llvm.org/D14701
llvm-svn: 254875
2015-12-06 13:26:56 +00:00
Asaf Badouh
d6d08d5567
[X86][AVX512] add comi with Sae
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add builtin_ia32_vcomisd and builtin_ia32_vcomisd
Differential Revision: http://reviews.llvm.org/D14331
llvm-svn: 254493
2015-12-02 08:17:51 +00:00
Elena Demikhovsky
a67f2cd5e4
AVX-512: fixed asm string of vsqrtss
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(vvsqrtss was generated before)
llvm-svn: 254411
2015-12-01 12:43:46 +00:00
Craig Topper
32bf88a844
[AVX512] The vpermi2 instructions require an integer vector for the index vector. This is reflected correctly in the intrinsics, but was not refelected in the isel patterns.
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For the floating point types, this requires adding a bitcast to the index vector when its passed through to the output.
llvm-svn: 254277
2015-11-30 00:13:24 +00:00
Igor Breger
31205fdf6a
AVX512:Implemented encoding for the vmovq.s instruction.
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Differential Revision: http://reviews.llvm.org/D14810
llvm-svn: 254248
2015-11-29 07:41:26 +00:00
Craig Topper
c5257f522e
[X86] Pair a NoVLX with HasAVX512 to match the others and remove a unique predicate check in the isel tables. NFC
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llvm-svn: 254191
2015-11-27 05:44:02 +00:00
Craig Topper
c259757ddf
[X86] Now that X86VPermt2 is used in all the avx512_perm_t_sizes just hardcode it into the patterns instead of passing as an argument. NFC
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llvm-svn: 254177
2015-11-26 20:21:29 +00:00
Craig Topper
f284e70884
[X86] Merge X86VPermt2Fp and X86VPermt2Int back together by weakening them just enough. The SDTCisSameSizeAs introduced in r254138 helps here.
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llvm-svn: 254176
2015-11-26 20:02:01 +00:00
Elena Demikhovsky
f792042843
AVX-512: Fixed a bug in VPERMT2* intrinsic.
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It was wrong order of operands (from intrinsic to DAG node).
I added more strict type specification for instruction selection.
Differential Revision: http://reviews.llvm.org/D14942
llvm-svn: 254059
2015-11-25 08:17:56 +00:00
Cong Hou
c0bb26286b
[X86] Fix several issues related to X86's psadbw instruction.
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This patch fixes the following issues:
1. Fix the return type of X86psadbw: it should not be the same type of inputs.
For vNi8 inputs the output should be vMi64, where M = N/8.
2. Fix the return type of int_x86_avx512_psad_bw_512 accordingly.
3. Fix the definiton of PSADBW, VPSADBW, and VPSADBWY accordingly.
4. Adjust the return type when building a DAG node of X86ISD::PSADBW type.
5. Update related tests.
Differential revision: http://reviews.llvm.org/D14897
llvm-svn: 254010
2015-11-24 19:51:26 +00:00
Elena Demikhovsky
678dc46339
AVX-512: Optimized INSERT_SUBVECTOR for i1 vector types
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ISERT_SUBVECTOR for i1 vectors may be done with shifts, when we insert into the lower part, or into the upper part, on into all-zero vector.
CONCAT_VECTORS uses ISERT_SUBVECTOR.
Differential Revision: http://reviews.llvm.org/D14815
llvm-svn: 253819
2015-11-22 13:57:38 +00:00
Igor Breger
0a68600909
AVX512: Implemented encoding, intrinsics and DAG lowering for VMOVDDUP instructions.
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Differential Revision: http://reviews.llvm.org/D14702
llvm-svn: 253548
2015-11-19 08:26:56 +00:00
Igor Breger
fb07c48ef1
AVX512: Implemented encoding for the vmovss.s and vmovsd.s instructions.
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Differential Revision: http://reviews.llvm.org/D14771
llvm-svn: 253547
2015-11-19 07:58:33 +00:00
Igor Breger
8a3c708d1f
AVX512: Implemented encoding for the follow instructions.
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vmovapd.s, vmovaps.s, vmovdqa32.s, vmovdqa64.s, vmovdqu16.s, vmovdqu32.s, vmovdqu64.s, vmovdqu8.s, vmovupd.s, vmovups.s
Differential Revision: http://reviews.llvm.org/D14768
llvm-svn: 253546
2015-11-19 07:43:43 +00:00
Asaf Badouh
e49f73285d
[X86][AVX512CD] add mask broadcast intrinsics
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Differential Revision: http://reviews.llvm.org/D14573
llvm-svn: 253450
2015-11-18 09:42:45 +00:00
Igor Breger
d09bcb79bc
AVX512: Implemented encoding for vpextrw.s instruction.
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Differential Revision: http://reviews.llvm.org/D14766
llvm-svn: 253447
2015-11-18 08:46:16 +00:00
Igor Breger
06ae954df6
AVX512: Implemented encoding and intrinsics for VMOVSHDUP/VMOVSLDUP instructions.
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Differential Revision: http://reviews.llvm.org/D14322
llvm-svn: 253185
2015-11-16 07:22:00 +00:00
Igor Breger
02e6595c76
Revert r253160.
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It broke layering violation. Reproducible with BUILD_SHARED_LIBS=ON.
llvm-svn: 253163
2015-11-15 12:19:11 +00:00
Igor Breger
3ec0d86d6a
AVX512: Implemented encoding and intrinsics for VMOVSHDUP/VMOVSLDUP instructions.
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Differential Revision: http://reviews.llvm.org/D14322
llvm-svn: 253160
2015-11-15 07:23:13 +00:00
Igor Breger
bfb07ae48a
AVX512 : Implemented encoding and DAG lowering for VMOVHPS/PD and VMOVLPS/PD instructions.
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Differential Revision: http://reviews.llvm.org/D14492
llvm-svn: 252592
2015-11-10 07:09:07 +00:00
Asaf Badouh
f3f551dd7e
revert rev. 252153 due to build failure on ubuntu
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[X86][AVX512] add comi with Sae
llvm-svn: 252154
2015-11-05 08:55:54 +00:00
Asaf Badouh
c9c8bfa4c4
[X86][AVX512] add comi with Sae
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add builtin_ia32_vcomisd and builtin_ia32_vcomisd
Differential Revision: http://reviews.llvm.org/D14331
llvm-svn: 252153
2015-11-05 08:45:06 +00:00
Asaf Badouh
e9eadcdf13
[X86][AVX512] small bugfix in VPBROADCASTM
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VPBROADCASTMW2D and VPBROADCASTMB2Q
Differential Revision: http://reviews.llvm.org/D14335
llvm-svn: 252151
2015-11-05 08:08:21 +00:00
Igor Breger
207c14b67f
AVX512: add encoding tests for vmovq/d instructions.
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llvm-svn: 251903
2015-11-03 07:30:17 +00:00
Igor Breger
dd070c17bb
AVX512: Implemented encoding and intrinsics for VBROADCASTI32x2 and VBROADCASTF32x2 instructions.
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Differential Revision: http://reviews.llvm.org/D14216
llvm-svn: 251781
2015-11-02 07:39:36 +00:00
Elena Demikhovsky
f42814b247
AVX-512: Optimized SIMD truncate operations for AVX512F set.
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Optimized <8 x i32> to <8 x i16>
<4 x i64> to < 4 x i32>
<16 x i16> to <16 x i8>
All these oprtrations use now AVX512F set (KNL). Before this change it was implemented with AVX2 set.
Differential Revision: http://reviews.llvm.org/D14108
llvm-svn: 251764
2015-11-01 11:45:47 +00:00
Asaf Badouh
2110df5fda
[X86][AVX512] [X86][AVX512] add convert float to half
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convert float to half with mask/maskz for the reg to reg version and mask for the reg to mem version (there is no maskz version for reg to mem).
Differential Revision: http://reviews.llvm.org/D14113
llvm-svn: 251409
2015-10-27 15:37:17 +00:00
Igor Breger
1ab3a1be2f
AVX-512: Use correct extract vector length.
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Bug https://llvm.org/bugs/show_bug.cgi?id=25318
Differential Revision: http://reviews.llvm.org/D14062
llvm-svn: 251285
2015-10-26 12:26:34 +00:00
Asaf Badouh
99f2354837
[X86][AVX512] extend vcvtph2ps to support xmm/ymm and sae versions
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Differential Revision: http://reviews.llvm.org/D13945
llvm-svn: 251018
2015-10-22 14:01:16 +00:00
Igor Breger
c385abd09d
AVX512: Implemented encoding and intrinsics for VPBROADCASTB/W/D/Q instructions.
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Differential Revision: http://reviews.llvm.org/D13884
llvm-svn: 250819
2015-10-20 11:56:42 +00:00
Asaf Badouh
381b11d5f2
[X86][AVX512DQ] add scalar fpclass
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Differential Revision: http://reviews.llvm.org/D13769
llvm-svn: 250650
2015-10-18 11:04:38 +00:00
Igor Breger
c4af5733a0
AVX512: Lowering i8/i16 vector CTLZ using the dword LZCNT vector instruction
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Differential Revision: http://reviews.llvm.org/D13632
llvm-svn: 250649
2015-10-18 09:56:39 +00:00
Igor Breger
6e29702ee8
AVX512: Implemented encoding and intrinsics for vpternlogd/q.
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Differential Revision: http://reviews.llvm.org/D13768
llvm-svn: 250396
2015-10-15 12:33:24 +00:00
Igor Breger
63cd1bda1b
AVX512: vpextrb/w/d/q and vpinsrb/w/d/q implementation.
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This instructions doesn't have intrincis.
Added tests for lowering and encoding.
Differential Revision: http://reviews.llvm.org/D12317
llvm-svn: 249688
2015-10-08 12:55:01 +00:00
Igor Breger
495e2a8625
AVX512: Change encoding of vpshuflw and vpshufhw instructions. Implement WIG as W0 and not W1, like all other instruction have been implemented.
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Add encoding tests.
Differential Revision: http://reviews.llvm.org/D13471
llvm-svn: 249521
2015-10-07 06:31:18 +00:00
Igor Breger
38dd6d8710
AVX512: Implemented encoding and intrinsics for VPERMILPS/PD instructions.
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Added tests for intrinsics and encoding.
Differential Revision: http://reviews.llvm.org/D12690
llvm-svn: 249261
2015-10-04 07:20:41 +00:00
Asaf Badouh
8011b4b495
[X86][AVX512] add masked version for RSQRT14 & RCP14 Scalar FP
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Differential Revision: http://reviews.llvm.org/D12524
llvm-svn: 248147
2015-09-21 10:23:53 +00:00
Igor Breger
a833017e0d
AVX512: Implemented encoding and intrinsics for vcmpss/sd.
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Added tests for intrinsics and encoding.
Differential Revision: http://reviews.llvm.org/D12593
llvm-svn: 248121
2015-09-20 15:15:10 +00:00
Asaf Badouh
4ce11a0a36
[X86][AVX512] extend support in Scalar conversion
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add scalar FP to Int conversion with truncation intrinsics
add scalar conversion FP32 from/to FP64 intrinsics
add rounding mode and SAE mode encoding for these intrinsics
Differential Revision: http://reviews.llvm.org/D12665
llvm-svn: 248117
2015-09-20 14:31:19 +00:00
Igor Breger
6c78cd17ac
AVX512: vsqrtss/sd encoding and intrinsics implementation.
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Added tests for intrinsics and encoding.
Differential Revision: http://reviews.llvm.org/D12102
llvm-svn: 248116
2015-09-20 09:13:41 +00:00
Asaf Badouh
981ab82bef
[X86][AVX512DQ] Add fpclass instruction
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Differential Revision: http://reviews.llvm.org/D12931
llvm-svn: 248115
2015-09-20 08:46:07 +00:00
Igor Breger
43e0d98a01
AVX512: Implement instructions encoding, lowering and intrinsics
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vinserti64x4, vinserti64x2, vinserti32x8, vinserti32x4, vinsertf64x4, vinsertf64x2, vinsertf32x8, vinsertf32x4
Added tests for encoding, lowering and intrinsics.
Differential Revision: http://reviews.llvm.org/D11893
llvm-svn: 248111
2015-09-20 06:52:42 +00:00
Igor Breger
eeecfc6724
AVX512: Implemented encoding and intrinsics for
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vextracti64x4 ,vextracti64x2, vextracti32x8, vextracti32x4, vextractf64x4, vextractf64x2, vextractf32x8, vextractf32x4
Added tests for intrinsics and encoding.
Differential Revision: http://reviews.llvm.org/D11802
llvm-svn: 247276
2015-09-10 12:54:54 +00:00
Renato Golin
32a92f6d16
Revert "AVX512: Implemented encoding and intrinsics for vextracti64x4 ,vextracti64x2, vextracti32x8, vextracti32x4, vextractf64x4, vextractf64x2, vextractf32x8, vextractf32x4 Added tests for intrinsics and encoding."
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This reverts commit r247149, as it was breaking numerous buildbots of varied architectures.
llvm-svn: 247177
2015-09-09 19:44:40 +00:00
Igor Breger
1a3ef530c1
AVX512: Implemented encoding and intrinsics for
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vextracti64x4 ,vextracti64x2, vextracti32x8, vextracti32x4, vextractf64x4, vextractf64x2, vextractf32x8, vextractf32x4
Added tests for intrinsics and encoding.
Differential Revision: http://reviews.llvm.org/D11802
llvm-svn: 247149
2015-09-09 14:35:09 +00:00
Igor Breger
2caf00654a
AVX512: kunpck encoding implementation
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Added tests for encoding.
Differential Revision: http://reviews.llvm.org/D12061
llvm-svn: 247010
2015-09-08 13:10:00 +00:00
Igor Breger
63fab329a2
AVX512: Implemented encoding and intrinsics for vplzcntq, vplzcntd, vpconflictq, vpconflictd
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Added tests for intrinsics and encoding.
Differential Revision: http://reviews.llvm.org/D11931
llvm-svn: 246750
2015-09-03 09:05:31 +00:00
Asaf Badouh
70ff5c87a7
[X86][AVX512VLBW] add support in byte shift and SAD
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add byte shift left/right
add SAD - compute sum of absolute differences
Differential Revision: http://reviews.llvm.org/D12479
llvm-svn: 246654
2015-09-02 14:21:54 +00:00